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NMSIS-Core
Version 1.2.0
NMSIS-Core support for Nuclei processor-based devices
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19 #ifndef __CORE_FEATURE_BASE__
20 #define __CORE_FEATURE_BASE__
37 #include "nmsis_compiler.h"
48 #define __RISCV_XLEN 32
50 #define __RISCV_XLEN __riscv_xlen
94 #if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
110 #if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
152 #if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
173 #if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
191 #if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
208 #if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
239 #if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
285 #if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
463 #define __RV_CSR_SWAP(csr, val) \
465 rv_csr_t __v = (unsigned long)(val); \
466 __ASM volatile("csrrw %0, " STRINGIFY(csr) ", %1" \
481 #define __RV_CSR_READ(csr) \
484 __ASM volatile("csrr %0, " STRINGIFY(csr) \
499 #define __RV_CSR_WRITE(csr, val) \
501 rv_csr_t __v = (rv_csr_t)(val); \
502 __ASM volatile("csrw " STRINGIFY(csr) ", %0" \
518 #define __RV_CSR_READ_SET(csr, val) \
520 rv_csr_t __v = (rv_csr_t)(val); \
521 __ASM volatile("csrrs %0, " STRINGIFY(csr) ", %1" \
536 #define __RV_CSR_SET(csr, val) \
538 rv_csr_t __v = (rv_csr_t)(val); \
539 __ASM volatile("csrs " STRINGIFY(csr) ", %0" \
555 #define __RV_CSR_READ_CLEAR(csr, val) \
557 rv_csr_t __v = (rv_csr_t)(val); \
558 __ASM volatile("csrrc %0, " STRINGIFY(csr) ", %1" \
573 #define __RV_CSR_CLEAR(csr, val) \
575 rv_csr_t __v = (rv_csr_t)(val); \
576 __ASM volatile("csrc " STRINGIFY(csr) ", %0" \
583 #include <intrinsics.h>
585 #define __RV_CSR_SWAP __write_csr
586 #define __RV_CSR_READ __read_csr
587 #define __RV_CSR_WRITE __write_csr
588 #define __RV_CSR_READ_SET __set_bits_csr
589 #define __RV_CSR_SET __set_bits_csr
590 #define __RV_CSR_READ_CLEAR __clear_bits_csr
591 #define __RV_CSR_CLEAR __clear_bits_csr
607 unsigned long val = 0;
622 __ASM volatile(
"mv sp, %0" ::
"r"(stack));
624 __ASM volatile(
"mret");
679 #if __RISCV_XLEN == 32
680 volatile uint32_t high0, low, high;
689 full = (((uint64_t)high) << 32) | low;
691 #elif __RISCV_XLEN == 64
693 #else // TODO Need cover for XLEN=128 case in future
706 #if __RISCV_XLEN == 32
707 volatile uint32_t high0, low, high;
716 full = (((uint64_t)high) << 32) | low;
718 #elif __RISCV_XLEN == 64
720 #else // TODO Need cover for XLEN=128 case in future
734 #if __RISCV_XLEN == 32
735 volatile uint32_t high0, low, high;
744 full = (((uint64_t)high) << 32) | low;
746 #elif __RISCV_XLEN == 64
748 #else // TODO Need cover for XLEN=128 case in future
779 #ifdef __HARTID_OFFSET
824 __ASM volatile(
"nop");
839 __ASM volatile(
"wfi");
852 __ASM volatile(
"wfi");
865 __ASM volatile(
"ebreak");
876 __ASM volatile(
"ecall");
885 } WFI_SleepMode_Type;
1115 #if __RISCV_XLEN == 32
1204 #elif __RISCV_XLEN == 64
1251 #if __RISCV_XLEN == 32
1252 volatile uint32_t high0, low, high;
1262 full = (((uint64_t)high) << 32) | low;
return full;
1267 full = (((uint64_t)high) << 32) | low;
return full;
1272 full = (((uint64_t)high) << 32) | low;
return full;
1277 full = (((uint64_t)high) << 32) | low;
return full;
1282 full = (((uint64_t)high) << 32) | low;
return full;
1287 full = (((uint64_t)high) << 32) | low;
return full;
1292 full = (((uint64_t)high) << 32) | low;
return full;
1297 full = (((uint64_t)high) << 32) | low;
return full;
1302 full = (((uint64_t)high) << 32) | low;
return full;
1307 full = (((uint64_t)high) << 32) | low;
return full;
1312 full = (((uint64_t)high) << 32) | low;
return full;
1317 full = (((uint64_t)high) << 32) | low;
return full;
1322 full = (((uint64_t)high) << 32) | low;
return full;
1327 full = (((uint64_t)high) << 32) | low;
return full;
1332 full = (((uint64_t)high) << 32) | low;
return full;
1337 full = (((uint64_t)high) << 32) | low;
return full;
1342 full = (((uint64_t)high) << 32) | low;
return full;
1347 full = (((uint64_t)high) << 32) | low;
return full;
1352 full = (((uint64_t)high) << 32) | low;
return full;
1357 full = (((uint64_t)high) << 32) | low;
return full;
1362 full = (((uint64_t)high) << 32) | low;
return full;
1367 full = (((uint64_t)high) << 32) | low;
return full;
1372 full = (((uint64_t)high) << 32) | low;
return full;
1377 full = (((uint64_t)high) << 32) | low;
return full;
1382 full = (((uint64_t)high) << 32) | low;
return full;
1387 full = (((uint64_t)high) << 32) | low;
return full;
1392 full = (((uint64_t)high) << 32) | low;
return full;
1397 full = (((uint64_t)high) << 32) | low;
return full;
1402 full = (((uint64_t)high) << 32) | low;
return full;
1404 #elif __RISCV_XLEN == 64
1467 #define __FENCE(p, s) __ASM volatile ("fence " #p "," #s : : : "memory")
1477 __ASM volatile(
"fence.i");
1481 #define __RWMB() __FENCE(iorw,iorw)
1484 #define __RMB() __FENCE(ir,ir)
1487 #define __WMB() __FENCE(ow,ow)
1490 #define __SMP_RWMB() __FENCE(rw,rw)
1493 #define __SMP_RMB() __FENCE(r,r)
1496 #define __SMP_WMB() __FENCE(w,w)
1499 #define __CPU_RELAX() __ASM volatile ("" : : : "memory")
1513 __ASM volatile (
"lb %0, 0(%1)" :
"=r" (result) :
"r" (addr));
1527 __ASM volatile (
"lh %0, 0(%1)" :
"=r" (result) :
"r" (addr));
1541 __ASM volatile (
"lw %0, 0(%1)" :
"=r" (result) :
"r" (addr));
1545 #if __RISCV_XLEN != 32
1556 __ASM volatile (
"ld %0, 0(%1)" :
"=r" (result) :
"r" (addr));
1569 __ASM volatile (
"sb %0, 0(%1)" : :
"r" (val),
"r" (addr));
1580 __ASM volatile (
"sh %0, 0(%1)" : :
"r" (val),
"r" (addr));
1591 __ASM volatile (
"sw %0, 0(%1)" : :
"r" (val),
"r" (addr));
1594 #if __RISCV_XLEN != 32
1603 __ASM volatile (
"sd %0, 0(%1)" : :
"r" (val),
"r" (addr));
1624 "0: lr.w %0, %2 \n" \
1625 " bne %0, %z3, 1f \n" \
1626 " sc.w %1, %z4, %2 \n" \
1629 :
"=&r"(result),
"=&r"(rc),
"+A"(*addr) \
1630 :
"r"(oldval),
"r"(newval) \
1646 __ASM volatile (
"amoswap.w %0, %2, %1" : \
1647 "=r"(result),
"+A"(*addr) :
"r"(newval) :
"memory");
1662 __ASM volatile (
"amoadd.w %0, %2, %1" : \
1663 "=r"(result),
"+A"(*addr) :
"r"(value) :
"memory");
1678 __ASM volatile (
"amoand.w %0, %2, %1" : \
1679 "=r"(result),
"+A"(*addr) :
"r"(value) :
"memory");
1694 __ASM volatile (
"amoor.w %0, %2, %1" : \
1695 "=r"(result),
"+A"(*addr) :
"r"(value) :
"memory");
1710 __ASM volatile (
"amoxor.w %0, %2, %1" : \
1711 "=r"(result),
"+A"(*addr) :
"r"(value) :
"memory");
1726 __ASM volatile (
"amomaxu.w %0, %2, %1" : \
1727 "=r"(result),
"+A"(*addr) :
"r"(value) :
"memory");
1742 __ASM volatile (
"amomax.w %0, %2, %1" : \
1743 "=r"(result),
"+A"(*addr) :
"r"(value) :
"memory");
1758 __ASM volatile (
"amominu.w %0, %2, %1" : \
1759 "=r"(result),
"+A"(*addr) :
"r"(value) :
"memory");
1774 __ASM volatile (
"amomin.w %0, %2, %1" : \
1775 "=r"(result),
"+A"(*addr) :
"r"(value) :
"memory");
1779 #if __RISCV_XLEN == 64
1791 __STATIC_FORCEINLINE uint64_t __CAS_D(
volatile uint64_t *addr, uint64_t oldval, uint64_t newval)
1797 "0: lr.d %0, %2 \n" \
1798 " bne %0, %z3, 1f \n" \
1799 " sc.d %1, %z4, %2 \n" \
1802 :
"=&r"(result),
"=&r"(rc),
"+A"(*addr) \
1803 :
"r"(oldval),
"r"(newval) \
1819 __ASM volatile (
"amoswap.d %0, %2, %1" : \
1820 "=r"(result),
"+A"(*addr) :
"r"(newval) :
"memory");
1835 __ASM volatile (
"amoadd.d %0, %2, %1" : \
1836 "=r"(result),
"+A"(*addr) :
"r"(value) :
"memory");
1851 __ASM volatile (
"amoand.d %0, %2, %1" : \
1852 "=r"(result),
"+A"(*addr) :
"r"(value) :
"memory");
1867 __ASM volatile (
"amoor.d %0, %2, %1" : \
1868 "=r"(result),
"+A"(*addr) :
"r"(value) :
"memory");
1883 __ASM volatile (
"amoxor.d %0, %2, %1" : \
1884 "=r"(result),
"+A"(*addr) :
"r"(value) :
"memory");
1899 __ASM volatile (
"amomaxu.d %0, %2, %1" : \
1900 "=r"(result),
"+A"(*addr) :
"r"(value) :
"memory");
1915 __ASM volatile (
"amomax.d %0, %2, %1" : \
1916 "=r"(result),
"+A"(*addr) :
"r"(value) :
"memory");
1931 __ASM volatile (
"amominu.d %0, %2, %1" : \
1932 "=r"(result),
"+A"(*addr) :
"r"(value) :
"memory");
1947 __ASM volatile (
"amomin.d %0, %2, %1" : \
1948 "=r"(result),
"+A"(*addr) :
"r"(value) :
"memory");
rv_csr_t d
Type used for csr data access.
rv_csr_t mpp2
bit: 9..10 privilede mode of second level NMI/exception nestting
#define CSR_MHPMCOUNTER15H
rv_csr_t c
bit: 2 Compressed extension
rv_csr_t ppi_bpa
PPI base address.
rv_csr_t _reserved1
Reserved.
__STATIC_FORCEINLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value)
Atomic unsigned MIN with 32bit value.
__STATIC_FORCEINLINE unsigned long __get_hart_index(void)
Get hart index of current cluster.
#define CSR_MHPMCOUNTER16
WFI_SleepMode
WFI Sleep Mode enumeration.
rv_csr_t d
Type used for csr data access.
rv_csr_t _reserved0
Reserved.
rv_csr_t addr
bit: 6..31 mtvec address
rv_csr_t d
bit: 3 Double-precision floating-point extension
rv_csr_t u
bit: 20 User mode implemented
rv_csr_t sramid
Indicate 1bit ECC error, software can clear these bits.
rv_csr_t cache_ecc
D-Cache ECC present.
rv_csr_t ic_en
I-Cache enable.
#define CSR_MHPMCOUNTER22H
rv_csr_t _reserved1
Reserved.
rv_csr_t d
Type used for csr data access.
rv_csr_t dlm_rwecc
Control mecc_code write to dlm, simulate error injection.
__STATIC_FORCEINLINE void __enable_mhpm_counters(unsigned long mask)
Enable hardware performance counters with mask.
rv_csr_t ppi_size
PPI size, need to be 2^n size.
#define CSR_MHPMCOUNTER20H
#define CSR_MHPMCOUNTER23H
rv_csr_t dc_ecc_en
D-Cache ECC enable.
rv_csr_t s
bit: 18 Supervisor mode implemented
__STATIC_FORCEINLINE void __disable_mcycle_counter(void)
Disable MCYCLE counter.
rv_csr_t dcache
DCache present.
rv_csr_t typ
bit: 6..7 current trap type
#define CSR_MHPMCOUNTER14
rv_csr_t lsize
I-Cache line size.
#define CSR_MHPMCOUNTER17H
#define CSR_MHPMCOUNTER21
rv_csr_t d
Type used for csr data access.
rv_csr_t _reserved0
Reserved.
rv_csr_t _reserved0
bit: 0 Reserved
rv_csr_t ic_ecc_excp_en
I-Cache 2bit ECC error exception enable.
__STATIC_FORCEINLINE void __enable_irq_s(void)
Enable IRQ Interrupts in supervisor mode.
__STATIC_FORCEINLINE void __NOP(void)
NOP Instruction.
#define __RV_CSR_CLEAR(csr, val)
CSR operation Macro for csrc instruction.
rv_csr_t mpie2
bit: 8 interrupt enable flag of second level NMI/exception nestting
Union type to access MFIOCFG_INFO CSR register.
rv_csr_t _reserved0
Reserved.
Union type to access MCACHE_CTL CSR register.
rv_csr_t ilm_en
ILM enable.
rv_csr_t xs
bit: XS status flag
rv_csr_t dc_en
DCache enable.
rv_csr_t _reserved2
bit: 16..31 Reserved
__STATIC_FORCEINLINE unsigned long __get_hpm_event(unsigned long idx)
Get event for selected high performance monitor event.
rv_csr_t mode
bit: 0..5 interrupt mode control
rv_csr_t _reserved1
bit: 26..24 Reserved
__STATIC_FORCEINLINE void __ECALL(void)
Environment Call Instruction.
#define CSR_MHPMCOUNTER22
#define CSR_MHPMCOUNTER31
rv_csr_t misalign
bit: 6 misaligned access support flag
Union type to access MECC_CODE CSR register.
Union type to access MCOUNTINHIBIT CSR register.
Union type to access MICFG_INFO CSR register.
rv_csr_t _reserved0
bit: 1 Reserved
#define CSR_MHPMCOUNTER27H
rv_csr_t _reserved3
bit: Reserved
#define CSR_MHPMCOUNTER13
__STATIC_FORCEINLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value)
Atomic And with 32bit value.
rv_csr_t ptyp1
bit: 6..7 NMI/exception type of before first nestting
rv_csr_t _reserved1
Reserved.
#define CSR_MHPMCOUNTER10H
Union type to access MCFG_INFO CSR register.
#define CSR_MHPMCOUNTER14H
rv_csr_t spie
bit: 3 Supervisor Privilede mode interrupt enable flag
rv_csr_t clic
CLIC present.
#define CSR_MHPMCOUNTER13H
rv_csr_t mpp1
bit: 1..2 privilede mode of fisrt level NMI/exception nestting
__STATIC_FORCEINLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value)
Atomic XOR with 32bit value.
rv_csr_t _reserved1
bit: 2 Reserved
rv_csr_t fio_size
FIO size, need to be 2^n size.
__STATIC_FORCEINLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value)
Atomic signed MAX with 32bit value.
Union type to access MDCFG_INFO CSR register.
Union type to access MCAUSE CSR register.
rv_csr_t d
Type used for csr data access.
rv_csr_t mpil
bit: 23..16 Previous interrupt level
rv_csr_t ptyp
bit: 8..9 previous trap type
Union type to access MISA CSR register.
#define CSR_MHPMCOUNTER20
__STATIC_FORCEINLINE void __set_wfi_sleepmode(WFI_SleepMode_Type mode)
Set Sleep mode of WFI.
#define CSR_MHPMCOUNTER8H
rv_csr_t _reserved1
bit: 4..5 Reserved
rv_csr_t t
bit: 19 Tentatively reserved for Transactional Memory extension
rv_csr_t ptyp2
bit: 14..15 NMI/exception type of before second nestting
rv_csr_t mxl
bit: 30..31 Machine XLEN
rv_csr_t _reserved1
bit: 11..13 Reserved
#define __RV_CSR_WRITE(csr, val)
CSR operation Macro for csrw instruction.
rv_csr_t f
bit: 5 Single-precision floating-point extension
Union type to access MDLM_CTL CSR register.
rv_csr_t ilm_bpa
ILM base address.
rv_csr_t d
Type used for csr data access.
rv_csr_t j
bit: 9 Tentatively reserved for Dynamically Translated Languages extension
__STATIC_FORCEINLINE void __set_hpm_event(unsigned long idx, unsigned long event)
Set event for selected high performance monitor event.
rv_csr_t lm_xonly
ILM Execute only permission.
__STATIC_FORCEINLINE uint16_t __LH(volatile void *addr)
Load 16bit value from address (16 bit)
rv_csr_t g
bit: 6 Additional standard extensions present
__STATIC_FORCEINLINE uint32_t __LW(volatile void *addr)
Load 32bit value from address (32 bit)
CSR_MMISCCTRL_Type CSR_MMISCCTL_Type
rv_csr_t dlm_en
DLM enable.
rv_csr_t dlm_ecc_excp_en
DLM ECC exception enable.
rv_csr_t mpie1
bit: 0 interrupt enable flag of fisrt level NMI/exception nestting
rv_csr_t d
Type used for csr data access.
rv_csr_t fs
bit: FS status flag
#define CSR_MHPMCOUNTER17
rv_csr_t lm_ecc
DLM ECC present.
rv_csr_t _reserved2
bit: 7..8 Reserved
__STATIC_FORCEINLINE unsigned long __get_hart_id(void)
Get hart id of current cluster.
rv_csr_t mpie
bit: 27 Interrupt enable flag before enter interrupt
rv_csr_t d
Type used for csr data access.
Union type to access MSUBM CSR register.
#define CSR_MHPMCOUNTER19H
__STATIC_FORCEINLINE void __disable_irq_s(void)
Disable IRQ Interrupts in supervisor mode.
rv_csr_t cy
bit: 0 1 means disable mcycle counter
rv_csr_t l
bit: 11 Tentatively reserved for Decimal Floating-Point extension
rv_csr_t ic_ecc_en
I-Cache ECC enable.
Union type to access MTVEC CSR register.
rv_csr_t dlm_ecc_en
DLM ECC eanble.
__STATIC_FORCEINLINE void __disable_all_counter(void)
Disable all MCYCLE & MINSTRET & MHPMCOUNTER counter.
Union type to access MMISC_CTRL CSR register.
#define CSR_MHPMCOUNTER18H
__STATIC_FORCEINLINE void __SB(volatile void *addr, uint8_t val)
Write 8bit value to address (8 bit)
rv_csr_t icache
ICache present.
__STATIC_FORCEINLINE void __disable_mhpm_counters(unsigned long mask)
Disable hardware performance counters with mask.
rv_csr_t sum
bit: Supervisor Mode load and store protection
#define CSR_MHPMCOUNTER24
rv_csr_t h
bit: 7 Hypervisor extension
rv_csr_t b
bit: 1 Tentatively reserved for Bit-Manipulation extension
rv_csr_t lm_size
DLM size, need to be 2^n size.
rv_csr_t ic_rwtecc
Control I-Cache Tag Ram ECC code injection.
__STATIC_FORCEINLINE uint64_t __get_rv_time(void)
Read whole 64 bits value of real-time clock.
rv_csr_t ic_scpd_mod
Scratchpad mode, 0: Scratchpad as ICache Data RAM, 1: Scratchpad as ILM SRAM.
rv_csr_t minhv
bit: 30 Machine interrupt vector table
rv_csr_t lm_ecc
ILM ECC present.
rv_csr_t _reserved1
bit: 10 Reserved
#define CSR_MHPMCOUNTER30H
__STATIC_FORCEINLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value)
Atomic unsigned MAX with 32bit value.
__STATIC_FORCEINLINE void __WFI(void)
Wait For Interrupt.
rv_csr_t code
Used to inject ECC check code.
rv_csr_t mpie
bit: mirror of MIE flag
rv_csr_t d
Type used for csr data access.
__STATIC_FORCEINLINE void __enable_mcycle_counter(void)
Enable MCYCLE counter.
__STATIC_FORCEINLINE void __disable_irq(void)
Disable IRQ Interrupts.
rv_csr_t ilm_rwecc
Control mecc_code write to ilm, simulate error injection.
__STATIC_FORCEINLINE void __enable_mhpm_counter(unsigned long idx)
Enable selected hardware performance monitor counter.
rv_csr_t cache_ecc
I-Cache ECC present.
rv_csr_t _reserved0
Reserved.
@ WFI_SHALLOW_SLEEP
Shallow sleep mode, the core_clk will poweroff.
rv_csr_t ilm_ecc_en
ILM ECC eanble.
Union type to access MECC_LOCK CSR register.
__STATIC_FORCEINLINE uint32_t __CAS_W(volatile uint32_t *addr, uint32_t oldval, uint32_t newval)
Compare and Swap 32bit value using LR and SC.
__STATIC_FORCEINLINE uint64_t __get_rv_cycle(void)
Read whole 64 bits value of mcycle counter.
#define CSR_MHPMCOUNTER16H
rv_csr_t _reserved2
Reserved.
__STATIC_FORCEINLINE void __switch_mode(uint8_t mode, uintptr_t stack, void(*entry_point)(void))
switch privilege from machine mode to others.
__STATIC_FORCEINLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value)
Atomic OR with 32bit value.
rv_csr_t d
Type used for csr data access.
rv_csr_t ecc_lock
RW permission, ECC Lock configure.
rv_csr_t set
I-Cache sets per way.
__STATIC_FORCEINLINE void __SH(volatile void *addr, uint16_t val)
Write 16bit value to address (16 bit)
rv_csr_t exccode
bit: 11..0 exception or interrupt code
#define CSR_MHPMCOUNTER4H
#define CSR_MHPMCOUNTER12
#define CSR_MHPMCOUNTER28H
#define CSR_MHPMCOUNTER25
rv_csr_t ir
bit: 2 1 means disable minstret counter
#define CSR_MHPMCOUNTER9H
rv_csr_t mpp
bit: mirror of Privilege Mode
#define CSR_MHPMCOUNTER11
#define CSR_MHPMCOUNTER7H
rv_csr_t dlm_bpa
DLM base address.
__STATIC_FORCEINLINE void __enable_irq(void)
Enable IRQ Interrupts.
#define CSR_MHPMCOUNTER27
#define __STATIC_FORCEINLINE
Define a static function that should be always inlined by the compiler.
rv_csr_t dc_rwtecc
Control D-Cache Tag Ram ECC code injection.
#define CSR_MCOUNTINHIBIT
#define CSR_MHPMCOUNTER5H
__STATIC_FORCEINLINE unsigned long __get_cluster_id(void)
Get cluster id of current cluster.
rv_csr_t dc_ecc_excp_en
D-Cache 2bit ECC error exception enable.
rv_csr_t _reserved0
bit: 0..2 Reserved
Union type to access MSTATUS CSR register.
rv_csr_t d
Type used for csr data access.
rv_csr_t d
Type used for csr data access.
__STATIC_FORCEINLINE void __TXEVT(void)
Send TX Event.
__STATIC_FORCEINLINE void __EBREAK(void)
Breakpoint Instruction.
#define CSR_MHPMCOUNTER29H
#define CSR_MHPMCOUNTER12H
rv_csr_t dc_rwdecc
Control D-Cache Data Ram ECC code injection.
__STATIC_FORCEINLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval)
Atomic Swap 32bit value into memory.
Union type to access MDCAUSE CSR register.
rv_csr_t set
D-Cache sets per way.
#define __RV_CSR_READ(csr)
CSR operation Macro for csrr instruction.
rv_csr_t bpu
bit: 3 dynamic prediction enable flag
rv_csr_t plic
PLIC present.
rv_csr_t _reserved0
Reserved.
#define CSR_MHPMCOUNTER24H
rv_csr_t mdcause
bit: 0..1 More detailed exception information as MCAUSE supplement
__STATIC_FORCEINLINE unsigned long __get_hpm_counter(unsigned long idx)
Get value of selected high performance monitor couner.
rv_csr_t _reserved4
bit: Reserved
#define CSR_MHPMCOUNTER3H
__STATIC_FORCEINLINE void __disable_minstret_counter(void)
Disable MINSTRET counter.
#define CSR_MHPMCOUNTER15
rv_csr_t a
bit: 0 Atomic extension
rv_csr_t w
Type used for csr data access.
#define CSR_MHPMCOUNTER19
__STATIC_FORCEINLINE void __enable_all_counter(void)
Enable all MCYCLE & MINSTRET & MHPMCOUNTER counter.
rv_csr_t mprv
bit: Machine mode PMP
#define CSR_MHPMCOUNTER11H
__STATIC_FORCEINLINE void __enable_minstret_counter(void)
Enable MINSTRET counter.
#define CSR_MHPMCOUNTER23
#define CSR_MHPMCOUNTER26H
rv_csr_t _reserved6
bit: 19..30 Reserved
rv_csr_t p
bit: 15 Tentatively reserved for Packed-SIMD extension
#define __RV_CSR_SET(csr, val)
CSR operation Macro for csrs instruction.
#define CSR_MHPMCOUNTER31H
#define CSR_MHPMCOUNTER21H
__STATIC_FORCEINLINE void __WFE(void)
Wait For Event.
rv_csr_t d
Type used for csr data access.
rv_csr_t _reserved4
bit: 22 Reserved
#define CSR_MHPMCOUNTER28
rv_csr_t m
bit: 12 Integer Multiply/Divide extension
rv_csr_t _reserved0
bit: 15..12 Reserved
#define CSR_MHPMCOUNTER29
rv_csr_t _reserved5
bit: 24..29 Reserved
rv_csr_t d
Type used for csr data access.
__STATIC_FORCEINLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value)
Atomic Add with 32bit value.
rv_csr_t fio_bpa
FIO base address.
__STATIC_FORCEINLINE uint8_t __LB(volatile void *addr)
Load 8bit value from address (8 bit)
rv_csr_t _reserved0
bit: 0..5 Reserved
#define CSR_MHPMCOUNTER30
rv_csr_t sd
bit: Dirty status for XS or FS
rv_csr_t _reserved2
bit: 14 Reserved
#define __RISCV_XLEN
Refer to the width of an integer register in bits(either 32 or 64)
rv_csr_t _reserved2
bit: 4 Reserved
rv_csr_t q
bit: 16 Quad-precision floating-point extension
rv_csr_t sie
bit: 1 supervisor interrupt enable flag
rv_csr_t ilm_ecc_excp_en
ILM ECC exception enable.
__STATIC_FORCEINLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value)
Atomic signed MIN with 32bit value.
rv_csr_t _reserved1
bit: 10..31 Reserved
rv_csr_t _reserved3
bit: 10..31 Reserved
__STATIC_FORCEINLINE void __set_medeleg(unsigned long mask)
Set exceptions delegation to S mode.
rv_csr_t _reserved1
bit: 3..31 Reserved
rv_csr_t d
Type used for csr data access.
Union type to access MSAVESTATUS CSR register.
__STATIC_FORCEINLINE void __set_hpm_counter(unsigned long idx, uint64_t value)
Set value for selected high performance monitor counter.
rv_csr_t d
Type used for csr data access.
rv_csr_t v
bit: 21 Tentatively reserved for Vector extension
rv_csr_t d
Type used for csr data access.
rv_csr_t lm_xonly
DLM Execute only permission.
__STATIC_FORCEINLINE void __SW(volatile void *addr, uint32_t val)
Write 32bit value to address (32 bit)
rv_csr_t interrupt
bit: 31 trap type.
rv_csr_t ramid
Indicate 2bit ECC error, software can clear these bits.
Union type to access MPPICFG_INFO CSR register.
rv_csr_t _reserved0
bit: 2..XLEN-1 Reserved
#define CSR_MHPMCOUNTER25H
#define __ASM
Pass information from the compiler to the assembler.
__STATIC_FORCEINLINE uint64_t __get_rv_instret(void)
Read whole 64 bits value of machine instruction-retired counter.
@ WFI_DEEP_SLEEP
Deep sleep mode, the core_clk and core_ano_clk will poweroff.
rv_csr_t _reserved0
bit: 3..5 Reserved
rv_csr_t e
bit: 4 RV32E base ISA
Union type to access MILM_CTL CSR register.
__STATIC_FORCEINLINE void __FENCE_I(void)
Fence.i Instruction.
rv_csr_t lm_size
ILM size, need to be 2^n size.
unsigned long rv_csr_t
Type of Control and Status Register(CSR), depends on the XLEN defined in RISC-V.
rv_csr_t nice
NICE present.
#define CSR_MHPMCOUNTER10
#define CSR_MHPMCOUNTER18
rv_csr_t lsize
D-Cache line size.
rv_csr_t mpp
bit: 29..28 Privilede mode flag before enter interrupt
__STATIC_FORCEINLINE void __disable_mhpm_counter(unsigned long idx)
Disable selected hardware performance monitor counter.
#define CSR_MHPMCOUNTER6H
rv_csr_t n
bit: 13 User-level interrupts supported
rv_csr_t _reserved0
Reserved.
#define CSR_MHPMCOUNTER26
rv_csr_t nmi_cause
bit: 9 mnvec control and nmi mcase exccode
rv_csr_t mie
bit: 3 Machine mode interrupt enable flag
rv_csr_t x
bit: 23 Non-standard extensions present
rv_csr_t ic_rwdecc
Control I-Cache Data Ram ECC code injection.
rv_csr_t i
bit: 8 RV32I/64I/128I base ISA
rv_csr_t _resreved3
bit: 17 Reserved