core_feature_base.h

/*
 * Copyright (c) 2019 Nuclei Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
 
#ifndef __CORE_FEATURE_BASE__
#define __CORE_FEATURE_BASE__
/*
 * Core Base Feature Configuration Macro:
 * 1. __HARTID_OFFSET:  Optional, define this macro when your cpu system first hart hartid and hart index is different.
 *    eg. If your cpu system, first hart hartid is 2, hart index is 0, then set this macro to 2
 *
 */
#include <stdint.h>
 
#ifdef __cplusplus
 extern "C" {
#endif
 
#include "nmsis_compiler.h"
 
#ifndef __RISCV_XLEN
  #ifndef __riscv_xlen
    #define __RISCV_XLEN    32
  #else
    #define __RISCV_XLEN    __riscv_xlen
  #endif
#endif /* __RISCV_XLEN */
 
typedef unsigned long rv_csr_t;
 /* End of Doxygen Group NMSIS_Core_Registers */
typedef union {
    struct {
        rv_csr_t a:1;                           
        rv_csr_t b:1;                           
        rv_csr_t c:1;                           
        rv_csr_t d:1;                           
        rv_csr_t e:1;                           
        rv_csr_t f:1;                           
        rv_csr_t g:1;                           
        rv_csr_t h:1;                           
        rv_csr_t i:1;                           
        rv_csr_t j:1;                           
        rv_csr_t k:1;                           
        rv_csr_t l:1;                           
        rv_csr_t m:1;                           
        rv_csr_t n:1;                           
        rv_csr_t o:1;                           
        rv_csr_t p:1;                           
        rv_csr_t q:1;                           
        rv_csr_t r:1;                           
        rv_csr_t s:1;                           
        rv_csr_t t:1;                           
        rv_csr_t u:1;                           
        rv_csr_t v:1;                           
        rv_csr_t w:1;                           
        rv_csr_t x:1;                           
        rv_csr_t y:1;                           
        rv_csr_t z:1;                           
        rv_csr_t _reserved0:__RISCV_XLEN-28;    
        rv_csr_t mxl:2;                         
    } b;                                        
    rv_csr_t d;                                 
} CSR_MISA_Type;
 
typedef union {
    struct {
        rv_csr_t _reserved0:1;                  
        rv_csr_t sie:1;                         
        rv_csr_t _reserved1:1;                  
        rv_csr_t mie:1;                         
        rv_csr_t _reserved2:1;                  
        rv_csr_t spie:1;                        
        rv_csr_t ube:1;                         
        rv_csr_t mpie:1;                        
        rv_csr_t spp:1;                         
        rv_csr_t vs:2;                          
        rv_csr_t mpp:2;                         
        rv_csr_t fs:2;                          
        rv_csr_t xs:2;                          
        rv_csr_t mprv:1;                        
        rv_csr_t sum:1;                         
        rv_csr_t mxr:1;                         
        rv_csr_t tvm:1;                         
        rv_csr_t tw:1;                          
        rv_csr_t tsr:1;                         
        rv_csr_t spelp:1;                       
        rv_csr_t sdt:1;                         
#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
        rv_csr_t _reserved3:7;                  
        rv_csr_t uxl:2;                         
        rv_csr_t sxl:2;                         
        rv_csr_t sbe:1;                         
        rv_csr_t mbe:1;                         
        rv_csr_t gva:1;                         
        rv_csr_t mpv:1;                         
        rv_csr_t _reserved4:1;                  
        rv_csr_t mpelp:1;                       
        rv_csr_t mdt:1;                         
        rv_csr_t _reserved5:20;                 
        rv_csr_t sd:1;                          
#else
        rv_csr_t _reserved3:6;                  
        rv_csr_t sd:1;                          
#endif
    } b;                                        
    rv_csr_t d;                                 
} CSR_MSTATUS_Type;
 
#if defined(__RISCV_XLEN) && __RISCV_XLEN == 32
typedef union {
    struct {
        rv_csr_t _reserved0:4;                  
        rv_csr_t sbe:1;                         
        rv_csr_t mbe:1;                         
        rv_csr_t gva:1;                         
        rv_csr_t mpv:1;                         
        rv_csr_t _reserved1:1;                  
        rv_csr_t mpelp:1;                       
        rv_csr_t mdt:1;                         
        rv_csr_t _reserved5:21;                 
    } b;                                        
    rv_csr_t d;                                 
} CSR_MSTATUSH_Type;
#endif
 
typedef union {
    struct {
        rv_csr_t mode:6;                        
        rv_csr_t addr:__RISCV_XLEN-6;           
    } b;                                        
    rv_csr_t d;                                 
} CSR_MTVEC_Type;
 
typedef union {
    struct {
        rv_csr_t exccode:12;                    
        rv_csr_t _reserved0:4;                  
        rv_csr_t mpil:8;                        
        rv_csr_t _reserved1:3;                  
        rv_csr_t mpie:1;                        
        rv_csr_t mpp:2;                         
        rv_csr_t minhv:1;                       
#if defined(__RISCV_XLEN) && __RISCV_XLEN == 64
        rv_csr_t _reserved2:__RISCV_XLEN-32;    
#endif
        rv_csr_t interrupt:1;                   
    } b;                                        
    rv_csr_t d;                                 
} CSR_MCAUSE_Type;
 
typedef union {
    struct {
        rv_csr_t cy:1;                          
        rv_csr_t _reserved0:1;                  
        rv_csr_t ir:1;                          
        rv_csr_t _reserved1:__RISCV_XLEN-3;     
    } b;                                        
    rv_csr_t d;                                 
} CSR_MCOUNTINHIBIT_Type;
 
typedef union {
    struct {
        rv_csr_t _reserved0:6;                  
        rv_csr_t typ:2;                         
        rv_csr_t ptyp:2;                        
        rv_csr_t _reserved1:__RISCV_XLEN-10;    
    } b;                                        
    rv_csr_t d;                                 
} CSR_MSUBM_Type;
 
typedef union {
    struct {
        rv_csr_t mdcause:3;                     
        rv_csr_t _reserved0:__RISCV_XLEN-3;     
    } b;                                        
    rv_csr_t d;                                 
} CSR_MDCAUSE_Type;
 
typedef union {
    struct {
        rv_csr_t _reserved0:1;                  
        rv_csr_t zclsd_en:1;                    
        rv_csr_t _reserved1:1;                  
        rv_csr_t bpu:1;                         
        rv_csr_t _reserved2:2;                  
        rv_csr_t misalign:1;                    
        rv_csr_t zcmt_zcmp:1;                   
        rv_csr_t core_buserr:1;                 
        rv_csr_t nmi_cause:1;                   
        rv_csr_t imreturn_en:1;                 
        rv_csr_t sijump_en:1;                   
        rv_csr_t ldspec_en:1;                   
        rv_csr_t _reserved3:1;                  
        rv_csr_t dbg_sec:1;                     
        rv_csr_t _reserved4:2;                  
        rv_csr_t csr_excl_enable:1;             
        rv_csr_t _reserved5:__RISCV_XLEN-18;    
    } b;                                        
    rv_csr_t d;                                 
} CSR_MMISCCTRL_Type;
 
typedef CSR_MMISCCTRL_Type CSR_MMISCCTL_Type;
typedef CSR_MMISCCTRL_Type CSR_MMISC_CTL_Type;
 
typedef union {
    struct {
        rv_csr_t ic_en:1;                       
        rv_csr_t ic_scpd_mod:1;                 
        rv_csr_t ic_ecc_en:1;                   
        rv_csr_t ic_ecc_excp_en:1;              
        rv_csr_t ic_rwtecc:1;                   
        rv_csr_t ic_rwdecc:1;                   
        rv_csr_t ic_pf_en:1;                    
        rv_csr_t ic_cancel_en:1;                
        rv_csr_t ic_ecc_chk_en:1;               
        rv_csr_t ic_prefetch_en:1;              
        rv_csr_t ic_burst_type:1;               
        rv_csr_t _reserved0:5;                  
        rv_csr_t dc_en:1;                       
        rv_csr_t dc_ecc_en:1;                   
        rv_csr_t dc_ecc_excp_en:1;              
        rv_csr_t dc_rwtecc:1;                   
        rv_csr_t dc_rwdecc:1;                   
        rv_csr_t dc_ecc_chk_en:1;               
        rv_csr_t dc_prefetch_en:1;              
        rv_csr_t dc_burst_type:1;               
        rv_csr_t _reserved1:__RISCV_XLEN-24;    
    } b;                                        
    rv_csr_t d;                                 
} CSR_MCACHECTL_Type;
 
typedef CSR_MCACHECTL_Type CSR_MCACHE_CTL_Type;
 
typedef union {
    struct {
        rv_csr_t mpie1:1;                       
        rv_csr_t mpp1:2;                        
        rv_csr_t _reserved0:3;                  
        rv_csr_t ptyp1:2;                       
        rv_csr_t mpie2:1;                       
        rv_csr_t mpp2:2;                        
        rv_csr_t _reserved1:3;                  
        rv_csr_t ptyp2:2;                       
        rv_csr_t _reserved2:__RISCV_XLEN-16;    
    } b;                                        
    rv_csr_t w;                                 
} CSR_MSAVESTATUS_Type;
 
typedef union {
    struct {
        rv_csr_t ilm_en:1;                      
        rv_csr_t ilm_ecc_en:1;                  
        rv_csr_t ilm_ecc_excp_en:1;             
        rv_csr_t ilm_rwecc:1;                   
        rv_csr_t ilm_ecc_chk_en:1;              
        rv_csr_t ilm_va_en:1;                   
        rv_csr_t _reserved0:4;                  
        rv_csr_t ilm_bpa:__RISCV_XLEN-10;       
    } b;                                        
    rv_csr_t d;                                 
} CSR_MILMCTL_Type;
 
typedef CSR_MILMCTL_Type CSR_MILM_CTL_Type;
 
typedef union {
    struct {
        rv_csr_t dlm_en:1;                      
        rv_csr_t dlm_ecc_en:1;                  
        rv_csr_t dlm_ecc_excp_en:1;             
        rv_csr_t dlm_rwecc:1;                   
        rv_csr_t dlm_ecc_chk_en:1;              
        rv_csr_t _reserved0:5;                  
        rv_csr_t dlm_bpa:__RISCV_XLEN-10;       
    } b;                                        
    rv_csr_t d;                                 
} CSR_MDLMCTL_Type;
 
typedef CSR_MDLMCTL_Type CSR_DILM_CTL_Type;
 
typedef union {
    struct {
        rv_csr_t tee:1;                         
        rv_csr_t ecc:1;                         
        rv_csr_t clic:1;                        
        rv_csr_t plic:1;                        
        rv_csr_t fio:1;                         
        rv_csr_t ppi:1;                         
        rv_csr_t nice:1;                        
        rv_csr_t ilm:1;                         
        rv_csr_t dlm:1;                         
        rv_csr_t icache:1;                      
        rv_csr_t dcache:1;                      
        rv_csr_t smp:1;                         
        rv_csr_t dsp_n1:1;                      
        rv_csr_t dsp_n2:1;                      
        rv_csr_t dsp_n3:1;                      
        rv_csr_t zc_xlcz:1;                     
        rv_csr_t iregion:1;                     
        rv_csr_t vpu_degree:2;                  
        rv_csr_t sec_mode:1;                    
        rv_csr_t etrace:1;                      
        rv_csr_t safety_mecha:2;                
        rv_csr_t vnice:1;                       
        rv_csr_t xlcz:1;                        
        rv_csr_t zilsd:1;                       
        rv_csr_t sstc:1;                        
        rv_csr_t _reserved1:__RISCV_XLEN-27;    
    } b;                                        
    rv_csr_t d;                                 
} CSR_MCFGINFO_Type;
 
typedef CSR_MCFGINFO_Type CSR_MCFG_INFO_Type;
 
typedef union {
    struct {
        rv_csr_t set:4;                         
        rv_csr_t way:3;                         
        rv_csr_t lsize:3;                       
        rv_csr_t ecc:1;                         
        rv_csr_t _reserved0:5;                  
        rv_csr_t lm_size:5;                     
        rv_csr_t lm_xonly:1;                    
        rv_csr_t lm_ecc:1;                      
        rv_csr_t _reserved1:__RISCV_XLEN-23;    
    } b;                                        
    rv_csr_t d;                                 
} CSR_MICFGINFO_Type;
 
typedef CSR_MICFGINFO_Type CSR_MICFG_INFO_Type;
 
typedef union {
    struct {
        rv_csr_t set:4;                         
        rv_csr_t way:3;                         
        rv_csr_t lsize:3;                       
        rv_csr_t ecc:1;                         
        rv_csr_t _reserved0:5;                  
        rv_csr_t lm_size:5;                     
        rv_csr_t lm_ecc:1;                      
        rv_csr_t _reserved1:__RISCV_XLEN-22;    
    } b;                                        
    rv_csr_t d;                                 
} CSR_MDCFGINFO_Type;
 
typedef CSR_MDCFGINFO_Type CSR_MDCFG_INFO_Type;
 
typedef union {
    struct {
        rv_csr_t set:4;                         
        rv_csr_t way:3;                         
        rv_csr_t lsize:3;                       
        rv_csr_t ecc:1;                         
        rv_csr_t napot:1;                       
        rv_csr_t _reserved1:4;                  
        rv_csr_t i_size:3;                      
        rv_csr_t d_size:3;                      
        rv_csr_t _reserved2:__RISCV_XLEN-22;    
    } b;                                        
    rv_csr_t d;                                 
} CSR_MTLBCFGINFO_Type;
 
typedef CSR_MTLBCFGINFO_Type CSR_MTLBCFG_INFO_Type;
 
typedef union {
    struct {
        rv_csr_t _reserved0:1;                  
        rv_csr_t ppi_size:5;                    
        rv_csr_t _reserved1:3;                  
        rv_csr_t ppi_en:1;                      
        rv_csr_t ppi_bpa:__RISCV_XLEN-10;       
    } b;                                        
    rv_csr_t d;                                 
} CSR_MPPICFGINFO_Type;
 
typedef CSR_MPPICFGINFO_Type CSR_MPPICFG_INFO_Type;
 
typedef union {
    struct {
        rv_csr_t _reserved0:1;                  
        rv_csr_t fio_size:5;                    
        rv_csr_t _reserved1:4;                  
        rv_csr_t fio_bpa:__RISCV_XLEN-10;       
    } b;                                        
    rv_csr_t d;                                 
} CSR_MFIOCFGINFO_Type;
 
typedef CSR_MFIOCFGINFO_Type CSR_MFIOCFG_INFO_Type;
 
typedef union {
    struct {
        rv_csr_t ecc_lock:1;                    
        rv_csr_t _reserved0:__RISCV_XLEN-1;     
    } b;                                        
    rv_csr_t d;                                 
} CSR_MECCLOCK_Type;
 
typedef CSR_MECCLOCK_Type CSR_MECC_LOCK_Type;
 
typedef union {
    struct {
        rv_csr_t code:9;                        
        rv_csr_t _reserved0:7;                  
        rv_csr_t ramid:5;                       
        rv_csr_t _reserved1:3;                  
        rv_csr_t sramid:5;                      
        rv_csr_t _reserved2:__RISCV_XLEN-29;    
    } b;                                        
    rv_csr_t d;                                 
} CSR_MECCCODE_Type;
 
typedef CSR_MECCCODE_Type CSR_MECC_CODE_Type;
 
typedef union {
    struct {
        rv_csr_t ilm_fch_msk:1;                 
        rv_csr_t ilm_acc_msk:1;                 
        rv_csr_t dlm_acc_msk:1;                 
        rv_csr_t ic_fch_msk:1;                  
        rv_csr_t dc_acc_msk:1;                  
        rv_csr_t ilm_ext_msk:1;                 
        rv_csr_t dlm_ext_msk:1;                 
        rv_csr_t ic_ccm_msk:1;                  
        rv_csr_t dc_ccm_msk:1;                  
        rv_csr_t dc_cpbk_msk:1;                 
        rv_csr_t _reserved0:__RISCV_XLEN-10;    
    } b;                                        
    rv_csr_t d;                                 
} CSR_MECC_CTL_Type;
 
typedef union {
    struct {
        rv_csr_t ilm_fch_err:1;                 
        rv_csr_t ilm_acc_err:1;                 
        rv_csr_t dlm_acc_err:1;                 
        rv_csr_t ic_fch_err:1;                  
        rv_csr_t dc_acc_err:1;                  
        rv_csr_t ilm_ext_err:1;                 
        rv_csr_t dlm_ext_err:1;                 
        rv_csr_t ic_ccm_err:1;                  
        rv_csr_t dc_ccm_err:1;                  
        rv_csr_t dc_cpbk_err:1;                 
        rv_csr_t _reserved0:__RISCV_XLEN-10;    
    } b;                                        
    rv_csr_t d;                                 
} CSR_MECC_STATUS_Type;
 
typedef union {
    struct {
        rv_csr_t _reserved0:1;                  
        rv_csr_t iregion_size:5;                
        rv_csr_t _reserved1:4;                  
        rv_csr_t iregion_base:__RISCV_XLEN-10;  
    } b;                                        
    rv_csr_t d;                                 
} CSR_MIRGB_INFO_Type;
 
typedef union {
    struct {
        rv_csr_t ovf_track_en:1;                
        rv_csr_t udf_en:1;                      
        rv_csr_t mode:1;                        
        rv_csr_t _reserved0:__RISCV_XLEN-3;     
    } b;                                        
    rv_csr_t d;                                 
} CSR_MSTACK_CTL_Type;
 
typedef union {
    struct {
        rv_csr_t tlb_ecc_en:1;                  
        rv_csr_t tlb_ecc_excp_en:1;             
        rv_csr_t tlb_tram_ecc_inj_en:1;         
        rv_csr_t tlb_dram_ecc_inj_en:1;         
        rv_csr_t _reserved0:2;                  
        rv_csr_t tlb_ecc_chk_en:1;              
        rv_csr_t napot_en:1;                    
        rv_csr_t _reserved1:__RISCV_XLEN-8;     
    } b;                                        
    rv_csr_t d;                                 
} CSR_MTLB_CTL_Type;
 
 /* End of Doxygen Group NMSIS_Core_Base_Registers */
 
/* ###########################  Core Function Access  ########################### */
#ifndef __ASSEMBLY__
 
#ifndef __ICCRISCV__
 
#define __RV_CSR_SWAP(csr, val)                                 \
    ({                                                          \
        rv_csr_t __v = (unsigned long)(val);                    \
        __ASM volatile("csrrw %0, " STRINGIFY(csr) ", %1"       \
                     : "=r"(__v)                                \
                     : "rK"(__v)                                \
                     : "memory");                               \
        __v;                                                    \
    })
 
#define __RV_CSR_READ(csr)                                      \
    ({                                                          \
        rv_csr_t __v;                                           \
        __ASM volatile("csrr %0, " STRINGIFY(csr)               \
                     : "=r"(__v)                                \
                     :                                          \
                     : "memory");                               \
        __v;                                                    \
    })
 
#define __RV_CSR_WRITE(csr, val)                                \
    ({                                                          \
        rv_csr_t __v = (rv_csr_t)(val);                         \
        __ASM volatile("csrw " STRINGIFY(csr) ", %0"            \
                     :                                          \
                     : "rK"(__v)                                \
                     : "memory");                               \
    })
 
#define __RV_CSR_READ_SET(csr, val)                             \
    ({                                                          \
        rv_csr_t __v = (rv_csr_t)(val);                         \
        __ASM volatile("csrrs %0, " STRINGIFY(csr) ", %1"       \
                     : "=r"(__v)                                \
                     : "rK"(__v)                                \
                     : "memory");                               \
        __v;                                                    \
    })
 
#define __RV_CSR_SET(csr, val)                                  \
    ({                                                          \
        rv_csr_t __v = (rv_csr_t)(val);                         \
        __ASM volatile("csrs " STRINGIFY(csr) ", %0"            \
                     :                                          \
                     : "rK"(__v)                                \
                     : "memory");                               \
    })
 
#define __RV_CSR_READ_CLEAR(csr, val)                           \
    ({                                                          \
        rv_csr_t __v = (rv_csr_t)(val);                         \
        __ASM volatile("csrrc %0, " STRINGIFY(csr) ", %1"       \
                     : "=r"(__v)                                \
                     : "rK"(__v)                                \
                     : "memory");                               \
        __v;                                                    \
    })
 
#define __RV_CSR_CLEAR(csr, val)                                \
    ({                                                          \
        rv_csr_t __v = (rv_csr_t)(val);                         \
        __ASM volatile("csrc " STRINGIFY(csr) ", %0"            \
                     :                                          \
                     : "rK"(__v)                                \
                     : "memory");                               \
    })
#else
 
#include <intrinsics.h>
 
#define __RV_CSR_SWAP         __write_csr
#define __RV_CSR_READ         __read_csr
#define __RV_CSR_WRITE        __write_csr
#define __RV_CSR_READ_SET     __set_bits_csr
#define __RV_CSR_SET          __set_bits_csr
#define __RV_CSR_READ_CLEAR   __clear_bits_csr
#define __RV_CSR_CLEAR        __clear_bits_csr
 
#endif /* __ICCRISCV__ */
 
#endif /* __ASSEMBLY__ */
 
__STATIC_FORCEINLINE void __switch_mode(uint8_t mode, uintptr_t stack, void(*entry_point)(void))
{
    unsigned long val = 0;
 
    /* Set MPP to the requested privilege mode */
    val = __RV_CSR_READ(CSR_MSTATUS);
    val = __RV_INSERT_FIELD(val, MSTATUS_MPP, mode);
 
    /* Set previous MIE disabled */
    val = __RV_INSERT_FIELD(val, MSTATUS_MPIE, 0);
 
    __RV_CSR_WRITE(CSR_MSTATUS, val);
 
    /* Set the entry point in MEPC */
    __RV_CSR_WRITE(CSR_MEPC, (unsigned long)entry_point);
 
    /* Set the register file */
    __ASM volatile("mv sp, %0" ::"r"(stack));
 
    __ASM volatile("mret");
}
 
__STATIC_FORCEINLINE void __enable_irq(void)
{
    __RV_CSR_SET(CSR_MSTATUS, MSTATUS_MIE);
}
 
__STATIC_FORCEINLINE void __disable_irq(void)
{
    __RV_CSR_CLEAR(CSR_MSTATUS, MSTATUS_MIE);
}
 
__STATIC_FORCEINLINE void __enable_ext_irq(void)
{
    __RV_CSR_SET(CSR_MIE, MIE_MEIE);
}
 
__STATIC_FORCEINLINE void __disable_ext_irq(void)
{
    __RV_CSR_CLEAR(CSR_MIE, MIE_MEIE);
}
 
__STATIC_FORCEINLINE void __enable_timer_irq(void)
{
    __RV_CSR_SET(CSR_MIE, MIE_MTIE);
}
 
__STATIC_FORCEINLINE void __disable_timer_irq(void)
{
    __RV_CSR_CLEAR(CSR_MIE, MIE_MTIE);
}
 
__STATIC_FORCEINLINE void __enable_sw_irq(void)
{
    __RV_CSR_SET(CSR_MIE, MIE_MSIE);
}
 
__STATIC_FORCEINLINE void __disable_sw_irq(void)
{
    __RV_CSR_CLEAR(CSR_MIE, MIE_MSIE);
}
 
__STATIC_FORCEINLINE void __disable_core_irq(uint32_t irq)
{
    __RV_CSR_CLEAR(CSR_MIE, 1UL << irq);
}
 
__STATIC_FORCEINLINE void __enable_core_irq(uint32_t irq)
{
    __RV_CSR_SET(CSR_MIE, 1UL << irq);
}
 
__STATIC_FORCEINLINE uint32_t __get_core_irq_pending(uint32_t irq)
{
    return ((__RV_CSR_READ(CSR_MIP) >> irq) & 0x1);
}
 
__STATIC_FORCEINLINE void __clear_core_irq_pending(uint32_t irq)
{
    __RV_CSR_CLEAR(CSR_MIP, 1UL << irq);
}
 
__STATIC_FORCEINLINE void __enable_irq_s(void)
{
    __RV_CSR_SET(CSR_SSTATUS, SSTATUS_SIE);
}
 
__STATIC_FORCEINLINE void __disable_irq_s(void)
{
    __RV_CSR_CLEAR(CSR_SSTATUS, SSTATUS_SIE);
}
 
__STATIC_FORCEINLINE void __enable_ext_irq_s(void)
{
    __RV_CSR_SET(CSR_SIE, MIE_SEIE);
}
 
__STATIC_FORCEINLINE void __disable_ext_irq_s(void)
{
    __RV_CSR_CLEAR(CSR_SIE, MIE_SEIE);
}
 
__STATIC_FORCEINLINE void __enable_timer_irq_s(void)
{
    __RV_CSR_SET(CSR_SIE, MIE_STIE);
}
 
__STATIC_FORCEINLINE void __disable_timer_irq_s(void)
{
    __RV_CSR_CLEAR(CSR_SIE, MIE_STIE);
}
 
__STATIC_FORCEINLINE void __enable_sw_irq_s(void)
{
    __RV_CSR_SET(CSR_SIE, MIE_SSIE);
}
 
__STATIC_FORCEINLINE void __disable_sw_irq_s(void)
{
    __RV_CSR_CLEAR(CSR_SIE, MIE_SSIE);
}
 
__STATIC_FORCEINLINE void __disable_core_irq_s(uint32_t irq)
{
    __RV_CSR_CLEAR(CSR_SIE, 1UL << irq);
}
 
__STATIC_FORCEINLINE void __enable_core_irq_s(uint32_t irq)
{
    __RV_CSR_SET(CSR_SIE, 1UL << irq);
}
 
__STATIC_FORCEINLINE uint32_t __get_core_irq_pending_s(uint32_t irq)
{
    return ((__RV_CSR_READ(CSR_SIP) >> irq) & 0x1);
}
 
__STATIC_FORCEINLINE void __clear_core_irq_pending_s(uint32_t irq)
{
    __RV_CSR_CLEAR(CSR_SIP, 1UL << irq);
}
 
__STATIC_FORCEINLINE uint64_t __get_rv_cycle(void)
{
#if __RISCV_XLEN == 32
    volatile uint32_t high0, low, high;
    uint64_t full;
 
    high0 = __RV_CSR_READ(CSR_MCYCLEH);
    low = __RV_CSR_READ(CSR_MCYCLE);
    high = __RV_CSR_READ(CSR_MCYCLEH);
    if (high0 != high) {
        low = __RV_CSR_READ(CSR_MCYCLE);
    }
    full = (((uint64_t)high) << 32) | low;
    return full;
#elif __RISCV_XLEN == 64
    return (uint64_t)__RV_CSR_READ(CSR_MCYCLE);
#else // TODO Need cover for XLEN=128 case in future
    return (uint64_t)__RV_CSR_READ(CSR_MCYCLE);
#endif
}
 
__STATIC_FORCEINLINE void __set_rv_cycle(uint64_t cycle)
{
#if __RISCV_XLEN == 32
    __RV_CSR_WRITE(CSR_MCYCLE, 0); // prevent carry
    __RV_CSR_WRITE(CSR_MCYCLEH, (uint32_t)(cycle >> 32));
    __RV_CSR_WRITE(CSR_MCYCLE, (uint32_t)(cycle));
#elif __RISCV_XLEN == 64
    __RV_CSR_WRITE(CSR_MCYCLE, cycle);
#else // TODO Need cover for XLEN=128 case in future
#endif
}
 
__STATIC_FORCEINLINE uint64_t __get_rv_instret(void)
{
#if __RISCV_XLEN == 32
    volatile uint32_t high0, low, high;
    uint64_t full;
 
    high0 = __RV_CSR_READ(CSR_MINSTRETH);
    low = __RV_CSR_READ(CSR_MINSTRET);
    high = __RV_CSR_READ(CSR_MINSTRETH);
    if (high0 != high) {
        low = __RV_CSR_READ(CSR_MINSTRET);
    }
    full = (((uint64_t)high) << 32) | low;
    return full;
#elif __RISCV_XLEN == 64
    return (uint64_t)__RV_CSR_READ(CSR_MINSTRET);
#else // TODO Need cover for XLEN=128 case in future
    return (uint64_t)__RV_CSR_READ(CSR_MINSTRET);
#endif
}
 
__STATIC_FORCEINLINE void __set_rv_instret(uint64_t instret)
{
#if __RISCV_XLEN == 32
    __RV_CSR_WRITE(CSR_MINSTRET, 0); // prevent carry
    __RV_CSR_WRITE(CSR_MINSTRETH, (uint32_t)(instret >> 32));
    __RV_CSR_WRITE(CSR_MINSTRET, (uint32_t)(instret));
#elif __RISCV_XLEN == 64
    __RV_CSR_WRITE(CSR_MINSTRET, instret);
#else // TODO Need cover for XLEN=128 case in future
#endif
}
 
__STATIC_FORCEINLINE uint64_t __get_rv_time(void)
{
#if __RISCV_XLEN == 32
    volatile uint32_t high0, low, high;
    uint64_t full;
 
    high0 = __RV_CSR_READ(CSR_TIMEH);
    low = __RV_CSR_READ(CSR_TIME);
    high = __RV_CSR_READ(CSR_TIMEH);
    if (high0 != high) {
        low = __RV_CSR_READ(CSR_TIME);
    }
    full = (((uint64_t)high) << 32) | low;
    return full;
#elif __RISCV_XLEN == 64
    return (uint64_t)__RV_CSR_READ(CSR_TIME);
#else // TODO Need cover for XLEN=128 case in future
    return (uint64_t)__RV_CSR_READ(CSR_TIME);
#endif
}
 
__STATIC_FORCEINLINE unsigned long __read_cycle_csr()
{
    return __RV_CSR_READ(CSR_CYCLE);
}
 
__STATIC_FORCEINLINE unsigned long __read_instret_csr()
{
    return __RV_CSR_READ(CSR_INSTRET);
}
 
__STATIC_FORCEINLINE unsigned long __read_time_csr()
{
    return __RV_CSR_READ(CSR_TIME);
}
 
__STATIC_FORCEINLINE unsigned long __get_cluster_id(void)
{
    unsigned long id;
 
    id = (__RV_CSR_READ(CSR_MHARTID) >> 8) & 0xFF;
    return id;
}
 
__STATIC_FORCEINLINE unsigned long __get_hart_index(void)
{
    unsigned long id;
#ifdef __HARTID_OFFSET
    id = __RV_CSR_READ(CSR_MHARTID) - __HARTID_OFFSET;
#else
    id = __RV_CSR_READ(CSR_MHARTID);
#endif
    return id;
}
 
__STATIC_FORCEINLINE unsigned long __get_hart_id(void)
{
    unsigned long id;
    id = __RV_CSR_READ(CSR_MHARTID);
    return id;
}
 
 
__STATIC_FORCEINLINE unsigned long __get_cluster_id_s(void)
{
    unsigned long id;
 
    id = (__RV_CSR_READ(CSR_SHARTID) >> 8) & 0xFF;
    return id;
}
 
__STATIC_FORCEINLINE unsigned long __get_hart_index_s(void)
{
    unsigned long id;
#ifdef __HARTID_OFFSET
    id = __RV_CSR_READ(CSR_SHARTID) - __HARTID_OFFSET;
#else
    id = __RV_CSR_READ(CSR_SHARTID);
#endif
    return id;
}
 
__STATIC_FORCEINLINE unsigned long __get_hart_id_s(void)
{
    unsigned long id;
    id = __RV_CSR_READ(CSR_SHARTID);
    return id;
}
 /* End of Doxygen Group NMSIS_Core_CSR_Register_Access */
 
/* ###########################  CPU Intrinsic Functions ########################### */
__STATIC_FORCEINLINE void __NOP(void)
{
    __ASM volatile("nop");
}
 
__STATIC_FORCEINLINE void __WFI(void)
{
    __RV_CSR_CLEAR(CSR_WFE, WFE_WFE);
    __ASM volatile("wfi");
}
 
__STATIC_FORCEINLINE void __WFE(void)
{
    __RV_CSR_SET(CSR_WFE, WFE_WFE);
    __ASM volatile("wfi");
    __RV_CSR_CLEAR(CSR_WFE, WFE_WFE);
}
 
__STATIC_FORCEINLINE void __EBREAK(void)
{
    __ASM volatile("ebreak");
}
 
__STATIC_FORCEINLINE void __ECALL(void)
{
    __ASM volatile("ecall");
}
 
typedef enum WFI_SleepMode {
    WFI_SHALLOW_SLEEP = 0,      
    WFI_DEEP_SLEEP = 1          
} WFI_SleepMode_Type;
 
__STATIC_FORCEINLINE void __set_wfi_sleepmode(WFI_SleepMode_Type mode)
{
    __RV_CSR_WRITE(CSR_SLEEPVALUE, mode);
}
 
__STATIC_FORCEINLINE void __TXEVT(void)
{
    __RV_CSR_SET(CSR_TXEVT, 0x1);
}
 
__STATIC_FORCEINLINE void __enable_mcycle_counter(void)
{
    __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_CY);
}
 
__STATIC_FORCEINLINE void __disable_mcycle_counter(void)
{
    __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_CY);
}
 
__STATIC_FORCEINLINE void __enable_minstret_counter(void)
{
    __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR);
}
 
__STATIC_FORCEINLINE void __disable_minstret_counter(void)
{
    __RV_CSR_SET(CSR_MCOUNTINHIBIT, MCOUNTINHIBIT_IR);
}
 
__STATIC_FORCEINLINE void __enable_mhpm_counter(unsigned long idx)
{
    __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, (1UL << idx));
}
 
__STATIC_FORCEINLINE void __disable_mhpm_counter(unsigned long idx)
{
    __RV_CSR_SET(CSR_MCOUNTINHIBIT, (1UL << idx));
}
 
__STATIC_FORCEINLINE void __enable_mhpm_counters(unsigned long mask)
{
    __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, mask);
}
 
__STATIC_FORCEINLINE void __disable_mhpm_counters(unsigned long mask)
{
    __RV_CSR_SET(CSR_MCOUNTINHIBIT, mask);
}
 
__STATIC_FORCEINLINE void __enable_all_counter(void)
{
    __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, 0xFFFFFFFF);
}
 
__STATIC_FORCEINLINE void __disable_all_counter(void)
{
    __RV_CSR_SET(CSR_MCOUNTINHIBIT, 0xFFFFFFFF);
}
 
__STATIC_FORCEINLINE void __set_hpm_event(unsigned long idx, unsigned long event)
{
    switch (idx) {
        case 3: __RV_CSR_WRITE(CSR_MHPMEVENT3, event); break;
        case 4: __RV_CSR_WRITE(CSR_MHPMEVENT4, event); break;
        case 5: __RV_CSR_WRITE(CSR_MHPMEVENT5, event); break;
        case 6: __RV_CSR_WRITE(CSR_MHPMEVENT6, event); break;
        case 7: __RV_CSR_WRITE(CSR_MHPMEVENT7, event); break;
        case 8: __RV_CSR_WRITE(CSR_MHPMEVENT8, event); break;
        case 9: __RV_CSR_WRITE(CSR_MHPMEVENT9, event); break;
        case 10: __RV_CSR_WRITE(CSR_MHPMEVENT10, event); break;
        case 11: __RV_CSR_WRITE(CSR_MHPMEVENT11, event); break;
        case 12: __RV_CSR_WRITE(CSR_MHPMEVENT12, event); break;
        case 13: __RV_CSR_WRITE(CSR_MHPMEVENT13, event); break;
        case 14: __RV_CSR_WRITE(CSR_MHPMEVENT14, event); break;
        case 15: __RV_CSR_WRITE(CSR_MHPMEVENT15, event); break;
        case 16: __RV_CSR_WRITE(CSR_MHPMEVENT16, event); break;
        case 17: __RV_CSR_WRITE(CSR_MHPMEVENT17, event); break;
        case 18: __RV_CSR_WRITE(CSR_MHPMEVENT18, event); break;
        case 19: __RV_CSR_WRITE(CSR_MHPMEVENT19, event); break;
        case 20: __RV_CSR_WRITE(CSR_MHPMEVENT20, event); break;
        case 21: __RV_CSR_WRITE(CSR_MHPMEVENT21, event); break;
        case 22: __RV_CSR_WRITE(CSR_MHPMEVENT22, event); break;
        case 23: __RV_CSR_WRITE(CSR_MHPMEVENT23, event); break;
        case 24: __RV_CSR_WRITE(CSR_MHPMEVENT24, event); break;
        case 25: __RV_CSR_WRITE(CSR_MHPMEVENT25, event); break;
        case 26: __RV_CSR_WRITE(CSR_MHPMEVENT26, event); break;
        case 27: __RV_CSR_WRITE(CSR_MHPMEVENT27, event); break;
        case 28: __RV_CSR_WRITE(CSR_MHPMEVENT28, event); break;
        case 29: __RV_CSR_WRITE(CSR_MHPMEVENT29, event); break;
        case 30: __RV_CSR_WRITE(CSR_MHPMEVENT30, event); break;
        case 31: __RV_CSR_WRITE(CSR_MHPMEVENT31, event); break;
        default: break;
    }
}
 
__STATIC_FORCEINLINE unsigned long __get_hpm_event(unsigned long idx)
{
    switch (idx) {
        case 3: return __RV_CSR_READ(CSR_MHPMEVENT3);
        case 4: return __RV_CSR_READ(CSR_MHPMEVENT4);
        case 5: return __RV_CSR_READ(CSR_MHPMEVENT5);
        case 6: return __RV_CSR_READ(CSR_MHPMEVENT6);
        case 7: return __RV_CSR_READ(CSR_MHPMEVENT7);
        case 8: return __RV_CSR_READ(CSR_MHPMEVENT8);
        case 9: return __RV_CSR_READ(CSR_MHPMEVENT9);
        case 10: return __RV_CSR_READ(CSR_MHPMEVENT10);
        case 11: return __RV_CSR_READ(CSR_MHPMEVENT11);
        case 12: return __RV_CSR_READ(CSR_MHPMEVENT12);
        case 13: return __RV_CSR_READ(CSR_MHPMEVENT13);
        case 14: return __RV_CSR_READ(CSR_MHPMEVENT14);
        case 15: return __RV_CSR_READ(CSR_MHPMEVENT15);
        case 16: return __RV_CSR_READ(CSR_MHPMEVENT16);
        case 17: return __RV_CSR_READ(CSR_MHPMEVENT17);
        case 18: return __RV_CSR_READ(CSR_MHPMEVENT18);
        case 19: return __RV_CSR_READ(CSR_MHPMEVENT19);
        case 20: return __RV_CSR_READ(CSR_MHPMEVENT20);
        case 21: return __RV_CSR_READ(CSR_MHPMEVENT21);
        case 22: return __RV_CSR_READ(CSR_MHPMEVENT22);
        case 23: return __RV_CSR_READ(CSR_MHPMEVENT23);
        case 24: return __RV_CSR_READ(CSR_MHPMEVENT24);
        case 25: return __RV_CSR_READ(CSR_MHPMEVENT25);
        case 26: return __RV_CSR_READ(CSR_MHPMEVENT26);
        case 27: return __RV_CSR_READ(CSR_MHPMEVENT27);
        case 28: return __RV_CSR_READ(CSR_MHPMEVENT28);
        case 29: return __RV_CSR_READ(CSR_MHPMEVENT29);
        case 30: return __RV_CSR_READ(CSR_MHPMEVENT30);
        case 31: return __RV_CSR_READ(CSR_MHPMEVENT31);
        default: return 0;
    }
}
 
__STATIC_FORCEINLINE void __set_hpm_counter(unsigned long idx, uint64_t value)
{
    switch (idx) {
#if __RISCV_XLEN == 32
        case 3: __RV_CSR_WRITE(CSR_MHPMCOUNTER3, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER3H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER3, (uint32_t)(value)); break;
        case 4: __RV_CSR_WRITE(CSR_MHPMCOUNTER4, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER4H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER4, (uint32_t)(value)); break;
        case 5: __RV_CSR_WRITE(CSR_MHPMCOUNTER5, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER5H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER5, (uint32_t)(value)); break;
        case 6: __RV_CSR_WRITE(CSR_MHPMCOUNTER6, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER6H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER6, (uint32_t)(value)); break;
        case 7: __RV_CSR_WRITE(CSR_MHPMCOUNTER7, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER7H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER7, (uint32_t)(value)); break;
        case 8: __RV_CSR_WRITE(CSR_MHPMCOUNTER8, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER8H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER8, (uint32_t)(value)); break;
        case 9: __RV_CSR_WRITE(CSR_MHPMCOUNTER9, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER9H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER9, (uint32_t)(value)); break;
        case 10: __RV_CSR_WRITE(CSR_MHPMCOUNTER10, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER10H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER10, (uint32_t)(value)); break;
        case 11: __RV_CSR_WRITE(CSR_MHPMCOUNTER11, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER11H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER11, (uint32_t)(value)); break;
        case 12: __RV_CSR_WRITE(CSR_MHPMCOUNTER12, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER12H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER12, (uint32_t)(value)); break;
        case 13: __RV_CSR_WRITE(CSR_MHPMCOUNTER13, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER13H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER13, (uint32_t)(value)); break;
        case 14: __RV_CSR_WRITE(CSR_MHPMCOUNTER14, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER14H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER14, (uint32_t)(value)); break;
        case 15: __RV_CSR_WRITE(CSR_MHPMCOUNTER15, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER15H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER15, (uint32_t)(value)); break;
        case 16: __RV_CSR_WRITE(CSR_MHPMCOUNTER16, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER16H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER16, (uint32_t)(value)); break;
        case 17: __RV_CSR_WRITE(CSR_MHPMCOUNTER17, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER17H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER17, (uint32_t)(value)); break;
        case 18: __RV_CSR_WRITE(CSR_MHPMCOUNTER18, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER18H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER18, (uint32_t)(value)); break;
        case 19: __RV_CSR_WRITE(CSR_MHPMCOUNTER19, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER19H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER19, (uint32_t)(value)); break;
        case 20: __RV_CSR_WRITE(CSR_MHPMCOUNTER20, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER20H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER20, (uint32_t)(value)); break;
        case 21: __RV_CSR_WRITE(CSR_MHPMCOUNTER21, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER21H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER21, (uint32_t)(value)); break;
        case 22: __RV_CSR_WRITE(CSR_MHPMCOUNTER22, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER22H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER22, (uint32_t)(value)); break;
        case 23: __RV_CSR_WRITE(CSR_MHPMCOUNTER23, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER23H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER23, (uint32_t)(value)); break;
        case 24: __RV_CSR_WRITE(CSR_MHPMCOUNTER24, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER24H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER24, (uint32_t)(value)); break;
        case 25: __RV_CSR_WRITE(CSR_MHPMCOUNTER25, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER25H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER25, (uint32_t)(value)); break;
        case 26: __RV_CSR_WRITE(CSR_MHPMCOUNTER26, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER26H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER26, (uint32_t)(value)); break;
        case 27: __RV_CSR_WRITE(CSR_MHPMCOUNTER27, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER27H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER27, (uint32_t)(value)); break;
        case 28: __RV_CSR_WRITE(CSR_MHPMCOUNTER28, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER28H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER28, (uint32_t)(value)); break;
        case 29: __RV_CSR_WRITE(CSR_MHPMCOUNTER29, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER29H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER29, (uint32_t)(value)); break;
        case 30: __RV_CSR_WRITE(CSR_MHPMCOUNTER30, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER30H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER30, (uint32_t)(value)); break;
        case 31: __RV_CSR_WRITE(CSR_MHPMCOUNTER31, 0); // prevent carry
            __RV_CSR_WRITE(CSR_MHPMCOUNTER31H, (uint32_t)(value >> 32));
            __RV_CSR_WRITE(CSR_MHPMCOUNTER31, (uint32_t)(value)); break;
 
#elif __RISCV_XLEN == 64
        case 3: __RV_CSR_WRITE(CSR_MHPMCOUNTER3, (value)); break;
        case 4: __RV_CSR_WRITE(CSR_MHPMCOUNTER4, (value)); break;
        case 5: __RV_CSR_WRITE(CSR_MHPMCOUNTER5, (value)); break;
        case 6: __RV_CSR_WRITE(CSR_MHPMCOUNTER6, (value)); break;
        case 7: __RV_CSR_WRITE(CSR_MHPMCOUNTER7, (value)); break;
        case 8: __RV_CSR_WRITE(CSR_MHPMCOUNTER8, (value)); break;
        case 9: __RV_CSR_WRITE(CSR_MHPMCOUNTER9, (value)); break;
        case 10: __RV_CSR_WRITE(CSR_MHPMCOUNTER10, (value)); break;
        case 11: __RV_CSR_WRITE(CSR_MHPMCOUNTER11, (value)); break;
        case 12: __RV_CSR_WRITE(CSR_MHPMCOUNTER12, (value)); break;
        case 13: __RV_CSR_WRITE(CSR_MHPMCOUNTER13, (value)); break;
        case 14: __RV_CSR_WRITE(CSR_MHPMCOUNTER14, (value)); break;
        case 15: __RV_CSR_WRITE(CSR_MHPMCOUNTER15, (value)); break;
        case 16: __RV_CSR_WRITE(CSR_MHPMCOUNTER16, (value)); break;
        case 17: __RV_CSR_WRITE(CSR_MHPMCOUNTER17, (value)); break;
        case 18: __RV_CSR_WRITE(CSR_MHPMCOUNTER18, (value)); break;
        case 19: __RV_CSR_WRITE(CSR_MHPMCOUNTER19, (value)); break;
        case 20: __RV_CSR_WRITE(CSR_MHPMCOUNTER20, (value)); break;
        case 21: __RV_CSR_WRITE(CSR_MHPMCOUNTER21, (value)); break;
        case 22: __RV_CSR_WRITE(CSR_MHPMCOUNTER22, (value)); break;
        case 23: __RV_CSR_WRITE(CSR_MHPMCOUNTER23, (value)); break;
        case 24: __RV_CSR_WRITE(CSR_MHPMCOUNTER24, (value)); break;
        case 25: __RV_CSR_WRITE(CSR_MHPMCOUNTER25, (value)); break;
        case 26: __RV_CSR_WRITE(CSR_MHPMCOUNTER26, (value)); break;
        case 27: __RV_CSR_WRITE(CSR_MHPMCOUNTER27, (value)); break;
        case 28: __RV_CSR_WRITE(CSR_MHPMCOUNTER28, (value)); break;
        case 29: __RV_CSR_WRITE(CSR_MHPMCOUNTER29, (value)); break;
        case 30: __RV_CSR_WRITE(CSR_MHPMCOUNTER30, (value)); break;
        case 31: __RV_CSR_WRITE(CSR_MHPMCOUNTER31, (value)); break;
 
#else
#endif
        default: break;
    }
}
 
__STATIC_FORCEINLINE uint64_t __get_hpm_counter(unsigned long idx)
{
#if __RISCV_XLEN == 32
    volatile uint32_t high0, low, high;
    uint64_t full;
 
    switch (idx) {
        case 0: return __get_rv_cycle();
        case 2: return __get_rv_instret();
        case 3: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER3H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER3);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER3H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER3); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 4: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER4H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER4);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER4H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER4); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 5: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER5H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER5);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER5H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER5); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 6: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER6H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER6);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER6H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER6); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 7: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER7H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER7);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER7H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER7); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 8: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER8H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER8);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER8H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER8); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 9: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER9H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER9);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER9H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER9); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 10: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER10H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER10);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER10H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER10); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 11: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER11H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER11);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER11H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER11); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 12: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER12H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER12);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER12H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER12); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 13: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER13H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER13);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER13H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER13); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 14: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER14H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER14);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER14H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER14); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 15: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER15H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER15);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER15H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER15); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 16: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER16H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER16);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER16H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER16); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 17: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER17H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER17);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER17H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER17); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 18: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER18H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER18);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER18H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER18); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 19: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER19H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER19);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER19H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER19); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 20: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER20H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER20);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER20H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER20); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 21: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER21H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER21);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER21H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER21); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 22: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER22H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER22);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER22H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER22); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 23: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER23H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER23);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER23H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER23); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 24: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER24H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER24);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER24H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER24); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 25: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER25H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER25);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER25H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER25); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 26: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER26H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER26);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER26H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER26); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 27: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER27H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER27);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER27H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER27); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 28: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER28H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER28);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER28H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER28); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 29: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER29H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER29);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER29H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER29); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 30: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER30H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER30);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER30H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER30); }
            full = (((uint64_t)high) << 32) | low; return full;
        case 31: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER31H);
            low = __RV_CSR_READ(CSR_MHPMCOUNTER31);
            high = __RV_CSR_READ(CSR_MHPMCOUNTER31H);
            if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER31); }
            full = (((uint64_t)high) << 32) | low; return full;
 
#elif __RISCV_XLEN == 64
    switch (idx) {
        case 0: return __get_rv_cycle();
        case 2: return __get_rv_instret();
        case 3: return __RV_CSR_READ(CSR_MHPMCOUNTER3);
        case 4: return __RV_CSR_READ(CSR_MHPMCOUNTER4);
        case 5: return __RV_CSR_READ(CSR_MHPMCOUNTER5);
        case 6: return __RV_CSR_READ(CSR_MHPMCOUNTER6);
        case 7: return __RV_CSR_READ(CSR_MHPMCOUNTER7);
        case 8: return __RV_CSR_READ(CSR_MHPMCOUNTER8);
        case 9: return __RV_CSR_READ(CSR_MHPMCOUNTER9);
        case 10: return __RV_CSR_READ(CSR_MHPMCOUNTER10);
        case 11: return __RV_CSR_READ(CSR_MHPMCOUNTER11);
        case 12: return __RV_CSR_READ(CSR_MHPMCOUNTER12);
        case 13: return __RV_CSR_READ(CSR_MHPMCOUNTER13);
        case 14: return __RV_CSR_READ(CSR_MHPMCOUNTER14);
        case 15: return __RV_CSR_READ(CSR_MHPMCOUNTER15);
        case 16: return __RV_CSR_READ(CSR_MHPMCOUNTER16);
        case 17: return __RV_CSR_READ(CSR_MHPMCOUNTER17);
        case 18: return __RV_CSR_READ(CSR_MHPMCOUNTER18);
        case 19: return __RV_CSR_READ(CSR_MHPMCOUNTER19);
        case 20: return __RV_CSR_READ(CSR_MHPMCOUNTER20);
        case 21: return __RV_CSR_READ(CSR_MHPMCOUNTER21);
        case 22: return __RV_CSR_READ(CSR_MHPMCOUNTER22);
        case 23: return __RV_CSR_READ(CSR_MHPMCOUNTER23);
        case 24: return __RV_CSR_READ(CSR_MHPMCOUNTER24);
        case 25: return __RV_CSR_READ(CSR_MHPMCOUNTER25);
        case 26: return __RV_CSR_READ(CSR_MHPMCOUNTER26);
        case 27: return __RV_CSR_READ(CSR_MHPMCOUNTER27);
        case 28: return __RV_CSR_READ(CSR_MHPMCOUNTER28);
        case 29: return __RV_CSR_READ(CSR_MHPMCOUNTER29);
        case 30: return __RV_CSR_READ(CSR_MHPMCOUNTER30);
        case 31: return __RV_CSR_READ(CSR_MHPMCOUNTER31);
 
#else
    switch (idx) {
#endif
        default: return 0;
    }
}
 
__STATIC_FORCEINLINE unsigned long __read_hpm_counter(unsigned long idx)
{
    switch (idx) {
        case 0: return __read_cycle_csr();
        case 2: return __read_instret_csr();
        case 3: return __RV_CSR_READ(CSR_MHPMCOUNTER3);
        case 4: return __RV_CSR_READ(CSR_MHPMCOUNTER4);
        case 5: return __RV_CSR_READ(CSR_MHPMCOUNTER5);
        case 6: return __RV_CSR_READ(CSR_MHPMCOUNTER6);
        case 7: return __RV_CSR_READ(CSR_MHPMCOUNTER7);
        case 8: return __RV_CSR_READ(CSR_MHPMCOUNTER8);
        case 9: return __RV_CSR_READ(CSR_MHPMCOUNTER9);
        case 10: return __RV_CSR_READ(CSR_MHPMCOUNTER10);
        case 11: return __RV_CSR_READ(CSR_MHPMCOUNTER11);
        case 12: return __RV_CSR_READ(CSR_MHPMCOUNTER12);
        case 13: return __RV_CSR_READ(CSR_MHPMCOUNTER13);
        case 14: return __RV_CSR_READ(CSR_MHPMCOUNTER14);
        case 15: return __RV_CSR_READ(CSR_MHPMCOUNTER15);
        case 16: return __RV_CSR_READ(CSR_MHPMCOUNTER16);
        case 17: return __RV_CSR_READ(CSR_MHPMCOUNTER17);
        case 18: return __RV_CSR_READ(CSR_MHPMCOUNTER18);
        case 19: return __RV_CSR_READ(CSR_MHPMCOUNTER19);
        case 20: return __RV_CSR_READ(CSR_MHPMCOUNTER20);
        case 21: return __RV_CSR_READ(CSR_MHPMCOUNTER21);
        case 22: return __RV_CSR_READ(CSR_MHPMCOUNTER22);
        case 23: return __RV_CSR_READ(CSR_MHPMCOUNTER23);
        case 24: return __RV_CSR_READ(CSR_MHPMCOUNTER24);
        case 25: return __RV_CSR_READ(CSR_MHPMCOUNTER25);
        case 26: return __RV_CSR_READ(CSR_MHPMCOUNTER26);
        case 27: return __RV_CSR_READ(CSR_MHPMCOUNTER27);
        case 28: return __RV_CSR_READ(CSR_MHPMCOUNTER28);
        case 29: return __RV_CSR_READ(CSR_MHPMCOUNTER29);
        case 30: return __RV_CSR_READ(CSR_MHPMCOUNTER30);
        case 31: return __RV_CSR_READ(CSR_MHPMCOUNTER31);
        default: return 0;
    }
}
 
__STATIC_FORCEINLINE void __set_medeleg(unsigned long mask)
{
    __RV_CSR_WRITE(CSR_MEDELEG, mask);
}
 
__STATIC_FORCEINLINE void __set_mideleg(unsigned long mask)
{
    __RV_CSR_WRITE(CSR_MIDELEG, mask);
}
 
#define __FENCE(p, s) __ASM volatile ("fence " #p "," #s : : : "memory")
 
__STATIC_FORCEINLINE void __FENCE_I(void)
{
    __ASM volatile("fence.i");
}
 
#define __RWMB()        __FENCE(iorw,iorw)
 
#define __RMB()         __FENCE(ir,ir)
 
#define __WMB()         __FENCE(ow,ow)
 
#define __SMP_RWMB()    __FENCE(rw,rw)
 
#define __SMP_RMB()     __FENCE(r,r)
 
#define __SMP_WMB()     __FENCE(w,w)
 
#define __CPU_RELAX()   __ASM volatile ("" : : : "memory")
 
 
/* ===== Load/Store Operations ===== */
__STATIC_FORCEINLINE uint8_t __LB(volatile void *addr)
{
    uint8_t result;
 
    __ASM volatile ("lb %0, 0(%1)" : "=r" (result) : "r" (addr));
    return result;
}
 
__STATIC_FORCEINLINE uint16_t __LH(volatile void *addr)
{
    uint16_t result;
 
    __ASM volatile ("lh %0, 0(%1)" : "=r" (result) : "r" (addr));
    return result;
}
 
__STATIC_FORCEINLINE uint32_t __LW(volatile void *addr)
{
    uint32_t result;
 
    __ASM volatile ("lw %0, 0(%1)" : "=r" (result) : "r" (addr));
    return result;
}
 
#if __RISCV_XLEN != 32
__STATIC_FORCEINLINE uint64_t __LD(volatile void *addr)
{
    uint64_t result;
    __ASM volatile ("ld %0, 0(%1)" : "=r" (result) : "r" (addr));
    return result;
}
#endif
 
__STATIC_FORCEINLINE void __SB(volatile void *addr, uint8_t val)
{
    __ASM volatile ("sb %0, 0(%1)" : : "r" (val), "r" (addr));
}
 
__STATIC_FORCEINLINE void __SH(volatile void *addr, uint16_t val)
{
    __ASM volatile ("sh %0, 0(%1)" : : "r" (val), "r" (addr));
}
 
__STATIC_FORCEINLINE void __SW(volatile void *addr, uint32_t val)
{
    __ASM volatile ("sw %0, 0(%1)" : : "r" (val), "r" (addr));
}
 
#if __RISCV_XLEN != 32
__STATIC_FORCEINLINE void __SD(volatile void *addr, uint64_t val)
{
    __ASM volatile ("sd %0, 0(%1)" : : "r" (val), "r" (addr));
}
#endif
 
__STATIC_FORCEINLINE uint32_t __CAS_W(volatile uint32_t *addr, uint32_t oldval, uint32_t newval)
{
    uint32_t result;
    uint32_t rc;
 
    __ASM volatile (                                \
            "0:     lr.w %0, %2      \n"            \
            "       bne  %0, %z3, 1f \n"            \
            "       sc.w %1, %z4, %2 \n"            \
            "       bnez %1, 0b      \n"            \
            "1:\n"                                  \
            : "=&r"(result), "=&r"(rc), "+A"(*addr) \
            : "r"(oldval), "r"(newval)              \
            : "memory");
    return result;
}
 
__STATIC_FORCEINLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval)
{
    uint32_t result;
 
    __ASM volatile ("amoswap.w %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(newval) : "memory");
    return result;
}
 
__STATIC_FORCEINLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value)
{
    int32_t result;
 
    __ASM volatile ("amoadd.w %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}
 
__STATIC_FORCEINLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value)
{
    int32_t result;
 
    __ASM volatile ("amoand.w %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}
 
__STATIC_FORCEINLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value)
{
    int32_t result;
 
    __ASM volatile ("amoor.w %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}
 
__STATIC_FORCEINLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value)
{
    int32_t result;
 
    __ASM volatile ("amoxor.w %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}
 
__STATIC_FORCEINLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value)
{
    uint32_t result;
 
    __ASM volatile ("amomaxu.w %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}
 
__STATIC_FORCEINLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value)
{
    int32_t result;
 
    __ASM volatile ("amomax.w %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}
 
__STATIC_FORCEINLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value)
{
    uint32_t result;
 
    __ASM volatile ("amominu.w %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}
 
__STATIC_FORCEINLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value)
{
    int32_t result;
 
    __ASM volatile ("amomin.w %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}
 
#if __RISCV_XLEN == 64
__STATIC_FORCEINLINE uint64_t __CAS_D(volatile uint64_t *addr, uint64_t oldval, uint64_t newval)
{
    uint64_t result;
    uint64_t rc;
 
    __ASM volatile (                                \
            "0:     lr.d %0, %2      \n"            \
            "       bne  %0, %z3, 1f \n"            \
            "       sc.d %1, %z4, %2 \n"            \
            "       bnez %1, 0b      \n"            \
            "1:\n"                                  \
            : "=&r"(result), "=&r"(rc), "+A"(*addr) \
            : "r"(oldval), "r"(newval)              \
            : "memory");
    return result;
}
 
__STATIC_FORCEINLINE uint64_t __AMOSWAP_D(volatile uint64_t *addr, uint64_t newval)
{
    uint64_t result;
 
    __ASM volatile ("amoswap.d %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(newval) : "memory");
    return result;
}
 
__STATIC_FORCEINLINE int64_t __AMOADD_D(volatile int64_t *addr, int64_t value)
{
    int64_t result;
 
    __ASM volatile ("amoadd.d %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}
 
__STATIC_FORCEINLINE int64_t __AMOAND_D(volatile int64_t *addr, int64_t value)
{
    int64_t result;
 
    __ASM volatile ("amoand.d %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}
 
__STATIC_FORCEINLINE int64_t __AMOOR_D(volatile int64_t *addr, int64_t value)
{
    int64_t result;
 
    __ASM volatile ("amoor.d %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}
 
__STATIC_FORCEINLINE int64_t __AMOXOR_D(volatile int64_t *addr, int64_t value)
{
    int64_t result;
 
    __ASM volatile ("amoxor.d %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}
 
__STATIC_FORCEINLINE uint64_t __AMOMAXU_D(volatile uint64_t *addr, uint64_t value)
{
    uint64_t result;
 
    __ASM volatile ("amomaxu.d %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}
 
__STATIC_FORCEINLINE int64_t __AMOMAX_D(volatile int64_t *addr, int64_t value)
{
    int64_t result;
 
    __ASM volatile ("amomax.d %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}
 
__STATIC_FORCEINLINE uint64_t __AMOMINU_D(volatile uint64_t *addr, uint64_t value)
{
    uint64_t result;
 
    __ASM volatile ("amominu.d %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}
 
__STATIC_FORCEINLINE int64_t __AMOMIN_D(volatile int64_t *addr, int64_t value)
{
    int64_t result;
 
    __ASM volatile ("amomin.d %0, %2, %1" : \
            "=r"(result), "+A"(*addr) : "r"(value) : "memory");
    return *addr;
}
#endif /* __RISCV_XLEN == 64  */
 /* End of Doxygen Group NMSIS_Core_CPU_Intrinsic */
 
#ifdef __cplusplus
}
#endif
#endif /* __CORE_FEATURE_BASE__ */