NMSIS-Core
Version 1.2.0
NMSIS-Core support for Nuclei processor-based devices
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Union type to access MICFG_INFO CSR register. More...
Data Fields | |
struct { | |
rv_csr_t set:4 | |
I-Cache sets per way. More... | |
rv_csr_t way:3 | |
I-Cache way. More... | |
rv_csr_t lsize:3 | |
I-Cache line size. More... | |
rv_csr_t cache_ecc:1 | |
I-Cache ECC present. More... | |
rv_csr_t _reserved0:5 | |
rv_csr_t lm_size:5 | |
ILM size, need to be 2^n size. More... | |
rv_csr_t lm_xonly:1 | |
ILM Execute only permission. More... | |
rv_csr_t lm_ecc:1 | |
ILM ECC present. More... | |
rv_csr_t _reserved1:__RISCV_XLEN-23 | |
} | b |
Structure used for bit access. More... | |
rv_csr_t | d |
Type used for csr data access. More... | |
Union type to access MICFG_INFO CSR register.
Definition at line 348 of file core_feature_base.h.
rv_csr_t CSR_MICFGINFO_Type::_reserved0 |
Definition at line 354 of file core_feature_base.h.
rv_csr_t CSR_MICFGINFO_Type::_reserved1 |
Definition at line 358 of file core_feature_base.h.
struct { ... } CSR_MICFGINFO_Type::b |
Structure used for bit access.
Referenced by GetICacheInfo().
rv_csr_t CSR_MICFGINFO_Type::cache_ecc |
I-Cache ECC present.
Definition at line 353 of file core_feature_base.h.
rv_csr_t CSR_MICFGINFO_Type::d |
Type used for csr data access.
Definition at line 360 of file core_feature_base.h.
rv_csr_t CSR_MICFGINFO_Type::lm_ecc |
ILM ECC present.
Definition at line 357 of file core_feature_base.h.
rv_csr_t CSR_MICFGINFO_Type::lm_size |
ILM size, need to be 2^n size.
Definition at line 355 of file core_feature_base.h.
rv_csr_t CSR_MICFGINFO_Type::lm_xonly |
ILM Execute only permission.
Definition at line 356 of file core_feature_base.h.
rv_csr_t CSR_MICFGINFO_Type::lsize |
I-Cache line size.
Definition at line 352 of file core_feature_base.h.
Referenced by GetICacheInfo().
rv_csr_t CSR_MICFGINFO_Type::set |
I-Cache sets per way.
Definition at line 350 of file core_feature_base.h.
Referenced by GetICacheInfo().
rv_csr_t CSR_MICFGINFO_Type::way |