NMSIS-Core  Version 1.5.0
NMSIS-Core support for Nuclei processor-based devices
core_feature_cache.h
1 /*
2  * Copyright (c) 2019 Nuclei Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Licensed under the Apache License, Version 2.0 (the License); you may
7  * not use this file except in compliance with the License.
8  * You may obtain a copy of the License at
9  *
10  * www.apache.org/licenses/LICENSE-2.0
11  *
12  * Unless required by applicable law or agreed to in writing, software
13  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15  * See the License for the specific language governing permissions and
16  * limitations under the License.
17  */
18 #ifndef __CORE_FEATURE_CACHE_H__
19 #define __CORE_FEATURE_CACHE_H__
24 /*
25  * Cache Feature Configuration Macro:
26  * 1. __ICACHE_PRESENT: Define whether I-Cache Unit is present or not.
27  * * 0: Not present
28  * * 1: Present
29  * 2. __DCACHE_PRESENT: Define whether D-Cache Unit is present or not.
30  * * 0: Not present
31  * * 1: Present
32  * 3. __CCM_PRESENT: Define whether Nuclei Cache Control and Maintainence(CCM) Unit is present or not.
33  * * 0: Not present
34  * * 1: Present
35  * 4. __SMPCC_PRESENT: Define whether SMP & Cluster Cache Unit is present or not.
36  * * 0: Not present
37  * * 1: Present
38  * 5. __SMPCC_BASEADDR: Base address of the SMP & Cluster Cache unit.
39  */
40 #ifdef __cplusplus
41  extern "C" {
42 #endif
43 
44 #include "core_feature_base.h"
45 
46 
47 #if defined(__CCM_PRESENT) && (__CCM_PRESENT == 1)
48 
49 #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1)
62 typedef struct {
63  __IM uint8_t RESERVED0[16];
64  __IOM uint32_t CC_CTRL;
65  __IOM uint32_t CC_mCMD;
66  __IM uint8_t RESERVED1[168];
67  __IOM uint32_t CC_sCMD;
68  __IOM uint32_t CC_uCMD;
69  __IM uint8_t RESERVED2[20];
70  __IOM uint32_t CC_INVALID_ALL;
72 
73 #define SMPCC_CMD_CTRL_SUP_EN_Pos 9U
74 #define SMPCC_CMD_CTRL_SUP_EN_Msk (0x1UL << SMPCC_CMD_CTRL_SUP_EN_Pos)
75 #define SMPCC_CMD_CTRL_SUP_EN_ENABLE 1U
76 #define SMPCC_CMD_CTRL_SUP_EN_DISABLE 0U
78 #define SMPCC_CMD_CTRL_USE_EN_Pos 10U
79 #define SMPCC_CMD_CTRL_USE_EN_Msk (0x1UL << SMPCC_CMD_CTRL_USE_EN_Pos)
80 #define SMPCC_CMD_CTRL_USE_EN_ENABLE 1U
81 #define SMPCC_CMD_CTRL_USE_EN_DISABLE 0U
83 #define SMPCC_CMD_xCMD_CMD_Pos 0U
84 #define SMPCC_CMD_xCMD_CMD_Msk (0x1FUL << SMPCC_CMD_xCMD_CMD_Pos)
85 #define SMPCC_CMD_xCMD_CMD_WB_ALL 0x7U
86 #define SMPCC_CMD_xCMD_CMD_WBINVAL_ALL 0x6U
88 #define SMPCC_CMD_xCMD_RESULT_Pos 26U
89 #define SMPCC_CMD_xCMD_RESULT_Msk (0x1FUL << SMPCC_CMD_xCMD_RESULT_Pos)
90 #define SMPCC_CMD_xCMD_RESULT_SUCCESS 0x0U
91 #define SMPCC_CMD_xCMD_RESULT_ENTRY_EXCEED_LIMIT 0x1U
92 #define SMPCC_CMD_xCMD_RESULT_REFILL_BUS_ERROR 0x3U
93 #define SMPCC_CMD_xCMD_RESULT_ECC_ERROR 0x4U
94 #define SMPCC_CMD_xCMD_RESULT_CPBACK_BUS_ERROR 0x5U
96 #define SMPCC_CMD_xCMD_COMPLETE_Pos 31U
97 #define SMPCC_CMD_xCMD_COMPLETE_Msk (0x1UL << SMPCC_CMD_xCMD_COMPLETE_Pos)
99 #define SMPCC_CMD_INVALID_ALL_Pos 0U
100 #define SMPCC_CMD_INVALID_ALL_Msk (0x1UL << SMPCC_CMD_INVALID_ALL_Pos)
102 #ifndef __SMPCC_BASEADDR
103 /* Base address of SMPCC(__SMPCC_BASEADDR) should be defined in <Device.h> */
104 #error "__SMPCC_BASEADDR is not defined, please check!"
105 #endif
106 
107 /* SMPCC CMD registers Memory mapping of Device */
108 #define SMPCC_CMD_BASE __SMPCC_BASEADDR
109 #define SMPCC_CMD ((SMPCC_CMD_Type *)SMPCC_CMD_BASE) /* End of Doxygen Group NMSIS_Core_CCache */
112 #endif /* #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1) */
113 
114 /* ########################## Cache functions #################################### */
139 typedef enum CCM_OP_FINFO {
144  CCM_OP_ECC_ERR = 0x4
146 
150 typedef enum CCM_CMD {
151  CCM_DC_INVAL = 0x0,
152  CCM_DC_WB = 0x1,
154  CCM_DC_LOCK = 0x3,
159  CCM_IC_INVAL = 0x8,
160  CCM_IC_LOCK = 0xb,
163  CCM_CC_LOCK = 0x13,
164  CCM_CC_UNLOCK = 0x12,
165 } CCM_CMD_Type;
166 
170 typedef struct CacheInfo {
171  uint32_t linesize;
172  uint32_t ways;
173  uint32_t setperway;
174  uint32_t size;
176 
177 #if __riscv_xlen == 32
178 #define CCM_SUEN_SUEN_Msk (0xFFFFFFFFUL)
179 #else
180 #define CCM_SUEN_SUEN_Msk (0xFFFFFFFFFFFFFFFFUL)
181 #endif
182 
196 {
198 #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1)
199  SMPCC_CMD->CC_CTRL |= _VAL2FLD(SMPCC_CMD_CTRL_SUP_EN, SMPCC_CMD_CTRL_SUP_EN_ENABLE) |
200  _VAL2FLD(SMPCC_CMD_CTRL_USE_EN, SMPCC_CMD_CTRL_USE_EN_ENABLE);
201 #endif /* #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1) */
202 }
203 
217 {
219 #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1)
220  SMPCC_CMD->CC_CTRL &= ~_VAL2FLD(SMPCC_CMD_CTRL_SUP_EN, SMPCC_CMD_CTRL_SUP_EN_DISABLE) &
221  ~_VAL2FLD(SMPCC_CMD_CTRL_USE_EN, SMPCC_CMD_CTRL_USE_EN_DISABLE);
222 #endif /* #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1) */
223 }
224 
235 {
237 } /* End of Doxygen Group NMSIS_Core_Cache */
239 
240 #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1)
256 __STATIC_INLINE unsigned long MLockCCacheLine(unsigned long addr)
257 {
260  FlushPipeCCM();
261  __RWMB();
263 }
264 
277 __STATIC_INLINE unsigned long MLockCCacheLines(unsigned long addr, unsigned long cnt)
278 {
279  if (cnt > 0) {
280  unsigned long i;
281  unsigned long fail_info = CCM_OP_SUCCESS;
283  for (i = 0; i < cnt; i++) {
285  FlushPipeCCM();
286  __RWMB();
287  fail_info = __RV_CSR_READ(CSR_CCM_MDATA);
288  if (CCM_OP_SUCCESS != fail_info) {
289  return fail_info;
290  }
291  }
292  }
293  return CCM_OP_SUCCESS;
294 }
295 
306 __STATIC_INLINE unsigned long SLockCCacheLine(unsigned long addr)
307 {
310  FlushPipeCCM();
311  __RWMB();
313 }
314 
327 __STATIC_INLINE unsigned long SLockCCacheLines(unsigned long addr, unsigned long cnt)
328 {
329  if (cnt > 0) {
330  unsigned long i;
331  unsigned long fail_info = CCM_OP_SUCCESS;
333  for (i = 0; i < cnt; i++) {
335  FlushPipeCCM();
336  __RWMB();
337  fail_info = __RV_CSR_READ(CSR_CCM_SDATA);
338  if (CCM_OP_SUCCESS != fail_info) {
339  return fail_info;
340  }
341  }
342  }
343  return CCM_OP_SUCCESS;
344 }
345 
356 __STATIC_INLINE unsigned long ULockCCacheLine(unsigned long addr)
357 {
360  FlushPipeCCM();
361  __RWMB();
363 }
364 
377 __STATIC_INLINE unsigned long ULockCCacheLines(unsigned long addr, unsigned long cnt)
378 {
379  if (cnt > 0) {
380  unsigned long i;
381  unsigned long fail_info = CCM_OP_SUCCESS;
383  for (i = 0; i < cnt; i++) {
385  FlushPipeCCM();
386  __RWMB();
387  fail_info = __RV_CSR_READ(CSR_CCM_UDATA);
388  if (CCM_OP_SUCCESS != fail_info) {
389  return fail_info;
390  }
391  }
392  }
393  return CCM_OP_SUCCESS;
394 }
395 
405 __STATIC_INLINE void MUnlockCCacheLine(unsigned long addr)
406 {
409  FlushPipeCCM();
410  __RWMB();
411 }
412 
424 __STATIC_INLINE void MUnlockCCacheLines(unsigned long addr, unsigned long cnt)
425 {
426  if (cnt > 0) {
427  unsigned long i;
429  for (i = 0; i < cnt; i++) {
431  }
432  FlushPipeCCM();
433  __RWMB();
434  }
435 }
436 
446 __STATIC_INLINE void SUnlockCCacheLine(unsigned long addr)
447 {
450  FlushPipeCCM();
451  __RWMB();
452 }
453 
465 __STATIC_INLINE void SUnlockCCacheLines(unsigned long addr, unsigned long cnt)
466 {
467  if (cnt > 0) {
468  unsigned long i;
470  for (i = 0; i < cnt; i++) {
472  }
473  FlushPipeCCM();
474  __RWMB();
475  }
476 }
477 
487 __STATIC_INLINE void UUnlockCCacheLine(unsigned long addr)
488 {
491  FlushPipeCCM();
492  __RWMB();
493 }
494 
506 __STATIC_INLINE void UUnlockCCacheLines(unsigned long addr, unsigned long cnt)
507 {
508  if (cnt > 0) {
509  unsigned long i;
511  for (i = 0; i < cnt; i++) {
513  }
514  FlushPipeCCM();
515  __RWMB();
516  }
517 }
518  /* End of Doxygen Group NMSIS_Core_CCache */
520 #endif /* defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1) */
521 
522 #endif /* defined(__CCM_PRESENT) && (__CCM_PRESENT == 1) */
523 
524 #if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1)
525 
543 {
545  return 1;
546  }
547  return 0;
548 }
549 
561 {
563 }
564 
576 {
578 }
579 
591 {
593 }
594 
606 {
608 }
609 
610 #if defined(__CCM_PRESENT) && (__CCM_PRESENT == 1)
622 {
623  if (info == NULL) {
624  return -1;
625  }
626  CSR_MICFGINFO_Type csr_ccfg;
627  csr_ccfg.d = __RV_CSR_READ(CSR_MICFG_INFO);
628  info->setperway = (1UL << csr_ccfg.b.set) << 3;
629  info->ways = (1 + csr_ccfg.b.way);
630  if (csr_ccfg.b.lsize == 0) {
631  info->linesize = 0;
632  } else {
633  info->linesize = (1UL << (csr_ccfg.b.lsize - 1)) << 3;
634  }
635  info->size = info->setperway * info->ways * info->linesize;
636  return 0;
637 }
638 
649 __STATIC_INLINE void MInvalICacheLine(unsigned long addr)
650 {
653  FlushPipeCCM();
654  __RWMB();
655 }
656 
668 __STATIC_INLINE void MInvalICacheLines(unsigned long addr, unsigned long cnt)
669 {
670  if (cnt > 0) {
671  unsigned long i;
673  for (i = 0; i < cnt; i++) {
675  }
676  FlushPipeCCM();
677  __RWMB();
678  }
679 }
680 
691 __STATIC_INLINE void SInvalICacheLine(unsigned long addr)
692 {
695  FlushPipeCCM();
696  __RWMB();
697 }
698 
710 __STATIC_INLINE void SInvalICacheLines(unsigned long addr, unsigned long cnt)
711 {
712  if (cnt > 0) {
713  unsigned long i;
715  for (i = 0; i < cnt; i++) {
717  }
718  FlushPipeCCM();
719  __RWMB();
720  }
721 }
722 
733 __STATIC_INLINE void UInvalICacheLine(unsigned long addr)
734 {
737  FlushPipeCCM();
738  __RWMB();
739 }
740 
752 __STATIC_INLINE void UInvalICacheLines(unsigned long addr, unsigned long cnt)
753 {
754  if (cnt > 0) {
755  unsigned long i;
757  for (i = 0; i < cnt; i++) {
759  }
760  FlushPipeCCM();
761  __RWMB();
762  }
763 }
764 
765 #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1)
776 __STATIC_INLINE void MInvalICacheCCacheLine(unsigned long addr)
777 {
780  /* Trigger Cluster Cache invalidation by DC_INVAL */
782  FlushPipeCCM();
783  __RWMB();
784 }
785 
797 __STATIC_INLINE void MInvalICacheCCacheLines(unsigned long addr, unsigned long cnt)
798 {
799  if (cnt > 0) {
800  unsigned long i;
802  for (i = 0; i < cnt; i++) {
804  /* Trigger Cluster Cache invalidation by DC_INVAL */
806  }
807  FlushPipeCCM();
808  __RWMB();
809  }
810 }
811 
822 __STATIC_INLINE void SInvalICacheCCacheLine(unsigned long addr)
823 {
826  /* Trigger Cluster Cache invalidation by DC_INVAL */
828  FlushPipeCCM();
829  __RWMB();
830 }
831 
843 __STATIC_INLINE void SInvalICacheCCacheLines(unsigned long addr, unsigned long cnt)
844 {
845  if (cnt > 0) {
846  unsigned long i;
848  for (i = 0; i < cnt; i++) {
850  /* Trigger Cluster Cache invalidation by DC_INVAL */
852  }
853  FlushPipeCCM();
854  __RWMB();
855  }
856 }
857 
868 __STATIC_INLINE void UInvalICacheCCacheLine(unsigned long addr)
869 {
872  /* Trigger Cluster Cache invalidation by DC_INVAL */
874  FlushPipeCCM();
875  __RWMB();
876 }
877 
889 __STATIC_INLINE void UInvalICacheCCacheLines(unsigned long addr, unsigned long cnt)
890 {
891  if (cnt > 0) {
892  unsigned long i;
894  for (i = 0; i < cnt; i++) {
896  /* Trigger Cluster Cache invalidation by DC_INVAL */
898  }
899  FlushPipeCCM();
900  __RWMB();
901  }
902 }
903 #endif /* #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1) */
904 
915 __STATIC_INLINE unsigned long MLockICacheLine(unsigned long addr)
916 {
919  FlushPipeCCM();
920  __RWMB();
922 }
923 
936 __STATIC_INLINE unsigned long MLockICacheLines(unsigned long addr, unsigned long cnt)
937 {
938  if (cnt > 0) {
939  unsigned long i;
940  unsigned long fail_info = CCM_OP_SUCCESS;
942  for (i = 0; i < cnt; i++) {
944  FlushPipeCCM();
945  __RWMB();
946  fail_info = __RV_CSR_READ(CSR_CCM_MDATA);
947  if (CCM_OP_SUCCESS != fail_info) {
948  return fail_info;
949  }
950  }
951  }
952  return CCM_OP_SUCCESS;
953 }
954 
965 __STATIC_INLINE unsigned long SLockICacheLine(unsigned long addr)
966 {
969  FlushPipeCCM();
970  __RWMB();
972 }
973 
986 __STATIC_INLINE unsigned long SLockICacheLines(unsigned long addr, unsigned long cnt)
987 {
988  if (cnt > 0) {
989  unsigned long i;
990  unsigned long fail_info = CCM_OP_SUCCESS;
992  for (i = 0; i < cnt; i++) {
994  FlushPipeCCM();
995  __RWMB();
996  fail_info = __RV_CSR_READ(CSR_CCM_SDATA);
997  if (CCM_OP_SUCCESS != fail_info) {
998  return fail_info;
999  }
1000  }
1001  }
1002  return CCM_OP_SUCCESS;
1003 }
1004 
1015 __STATIC_INLINE unsigned long ULockICacheLine(unsigned long addr)
1016 {
1019  FlushPipeCCM();
1020  __RWMB();
1021  return __RV_CSR_READ(CSR_CCM_UDATA);
1022 }
1023 
1036 __STATIC_INLINE unsigned long ULockICacheLines(unsigned long addr, unsigned long cnt)
1037 {
1038  if (cnt > 0) {
1039  unsigned long i;
1040  unsigned long fail_info = CCM_OP_SUCCESS;
1042  for (i = 0; i < cnt; i++) {
1044  FlushPipeCCM();
1045  __RWMB();
1046  fail_info = __RV_CSR_READ(CSR_CCM_UDATA);
1047  if (CCM_OP_SUCCESS != fail_info) {
1048  return fail_info;
1049  }
1050  }
1051  }
1052  return CCM_OP_SUCCESS;
1053 }
1054 
1064 __STATIC_INLINE void MUnlockICacheLine(unsigned long addr)
1065 {
1068  FlushPipeCCM();
1069  __RWMB();
1070 }
1071 
1083 __STATIC_INLINE void MUnlockICacheLines(unsigned long addr, unsigned long cnt)
1084 {
1085  if (cnt > 0) {
1086  unsigned long i;
1088  for (i = 0; i < cnt; i++) {
1090  }
1091  FlushPipeCCM();
1092  __RWMB();
1093  }
1094 }
1095 
1105 __STATIC_INLINE void SUnlockICacheLine(unsigned long addr)
1106 {
1109  FlushPipeCCM();
1110  __RWMB();
1111 }
1112 
1124 __STATIC_INLINE void SUnlockICacheLines(unsigned long addr, unsigned long cnt)
1125 {
1126  if (cnt > 0) {
1127  unsigned long i;
1129  for (i = 0; i < cnt; i++) {
1131  }
1132  FlushPipeCCM();
1133  __RWMB();
1134  }
1135 }
1136 
1146 __STATIC_INLINE void UUnlockICacheLine(unsigned long addr)
1147 {
1150  FlushPipeCCM();
1151  __RWMB();
1152 }
1153 
1165 __STATIC_INLINE void UUnlockICacheLines(unsigned long addr, unsigned long cnt)
1166 {
1167  if (cnt > 0) {
1168  unsigned long i;
1170  for (i = 0; i < cnt; i++) {
1172  }
1173  FlushPipeCCM();
1174  __RWMB();
1175  }
1176 }
1177 
1188 {
1190  FlushPipeCCM();
1191  __RWMB();
1192 }
1193 
1204 {
1206  FlushPipeCCM();
1207  __RWMB();
1208 }
1209 
1220 {
1222  FlushPipeCCM();
1223  __RWMB();
1224 }
1225 
1226 #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1)
1235 {
1236  SMPCC_CMD->CC_INVALID_ALL = _VAL2FLD(SMPCC_CMD_INVALID_ALL, 1);
1237  while(_FLD2VAL(SMPCC_CMD_INVALID_ALL, SMPCC_CMD->CC_INVALID_ALL));
1238  __RWMB();
1239 }
1240 
1249 {
1250  SMPCC_CMD->CC_INVALID_ALL = _VAL2FLD(SMPCC_CMD_INVALID_ALL, 1);
1251  while(_FLD2VAL(SMPCC_CMD_INVALID_ALL, SMPCC_CMD->CC_INVALID_ALL));
1252  __RWMB();
1253 }
1254 
1263 {
1264  SMPCC_CMD->CC_INVALID_ALL = _VAL2FLD(SMPCC_CMD_INVALID_ALL, 1);
1265  while(_FLD2VAL(SMPCC_CMD_INVALID_ALL, SMPCC_CMD->CC_INVALID_ALL));
1266  __RWMB();
1267 }
1268 
1278 {
1280  FlushPipeCCM();
1281  SMPCC_CMD->CC_INVALID_ALL = _VAL2FLD(SMPCC_CMD_INVALID_ALL, 1);
1282  while(_FLD2VAL(SMPCC_CMD_INVALID_ALL, SMPCC_CMD->CC_INVALID_ALL));
1283  __RWMB();
1284 }
1285 
1295 {
1297  FlushPipeCCM();
1298  SMPCC_CMD->CC_INVALID_ALL = _VAL2FLD(SMPCC_CMD_INVALID_ALL, 1);
1299  while(_FLD2VAL(SMPCC_CMD_INVALID_ALL, SMPCC_CMD->CC_INVALID_ALL));
1300  __RWMB();
1301 }
1302 
1312 {
1314  FlushPipeCCM();
1315  SMPCC_CMD->CC_INVALID_ALL = _VAL2FLD(SMPCC_CMD_INVALID_ALL, 1);
1316  while(_FLD2VAL(SMPCC_CMD_INVALID_ALL, SMPCC_CMD->CC_INVALID_ALL));
1317  __RWMB();
1318 }
1319 #endif /* #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1) */
1320 
1321 #endif /* defined(__CCM_PRESENT) && (__CCM_PRESENT == 1) */ /* End of Doxygen Group NMSIS_Core_ICache */
1323 #endif /* defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1) */
1324 
1325 #if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1)
1343 {
1345  return 1;
1346  }
1347  return 0;
1348 }
1349 
1361 {
1363 }
1364 
1376 {
1378 }
1379 
1391 {
1393 }
1394 
1406 {
1408 }
1409 
1410 #if defined(__CCM_PRESENT) && (__CCM_PRESENT == 1)
1422 {
1423  if (info == NULL) {
1424  return -1;
1425  }
1426  CSR_MDCFGINFO_Type csr_ccfg;
1427  csr_ccfg.d = __RV_CSR_READ(CSR_MDCFG_INFO);
1428  info->setperway = (1UL << csr_ccfg.b.set) << 3;
1429  info->ways = (1 + csr_ccfg.b.way);
1430  if (csr_ccfg.b.lsize == 0) {
1431  info->linesize = 0;
1432  } else {
1433  info->linesize = (1UL << (csr_ccfg.b.lsize - 1)) << 3;
1434  }
1435  info->size = info->setperway * info->ways * info->linesize;
1436  return 0;
1437 }
1438 
1449 __STATIC_INLINE void MInvalDCacheLine(unsigned long addr)
1450 {
1453  FlushPipeCCM();
1454  __RWMB();
1455 }
1456 
1468 __STATIC_INLINE void MInvalDCacheLines(unsigned long addr, unsigned long cnt)
1469 {
1470  if (cnt > 0) {
1471  unsigned long i;
1473  for (i = 0; i < cnt; i++) {
1475  }
1476  FlushPipeCCM();
1477  __RWMB();
1478  }
1479 }
1480 
1491 __STATIC_INLINE void SInvalDCacheLine(unsigned long addr)
1492 {
1495  FlushPipeCCM();
1496  __RWMB();
1497 }
1498 
1510 __STATIC_INLINE void SInvalDCacheLines(unsigned long addr, unsigned long cnt)
1511 {
1512  if (cnt > 0) {
1513  unsigned long i;
1515  for (i = 0; i < cnt; i++) {
1517  }
1518  FlushPipeCCM();
1519  __RWMB();
1520  }
1521 }
1522 
1533 __STATIC_INLINE void UInvalDCacheLine(unsigned long addr)
1534 {
1537  FlushPipeCCM();
1538  __RWMB();
1539 }
1540 
1552 __STATIC_INLINE void UInvalDCacheLines(unsigned long addr, unsigned long cnt)
1553 {
1554  if (cnt > 0) {
1555  unsigned long i;
1557  for (i = 0; i < cnt; i++) {
1559  }
1560  FlushPipeCCM();
1561  __RWMB();
1562  }
1563 }
1564 
1574 __STATIC_INLINE void MFlushDCacheLine(unsigned long addr)
1575 {
1578  FlushPipeCCM();
1579  __RWMB();
1580 }
1581 
1593 __STATIC_INLINE void MFlushDCacheLines(unsigned long addr, unsigned long cnt)
1594 {
1595  if (cnt > 0) {
1596  unsigned long i;
1598  for (i = 0; i < cnt; i++) {
1600  }
1601  FlushPipeCCM();
1602  __RWMB();
1603  }
1604 }
1605 
1615 __STATIC_INLINE void SFlushDCacheLine(unsigned long addr)
1616 {
1619  FlushPipeCCM();
1620  __RWMB();
1621 }
1622 
1634 __STATIC_INLINE void SFlushDCacheLines(unsigned long addr, unsigned long cnt)
1635 {
1636  if (cnt > 0) {
1637  unsigned long i;
1639  for (i = 0; i < cnt; i++) {
1641  }
1642  FlushPipeCCM();
1643  __RWMB();
1644  }
1645 }
1646 
1656 __STATIC_INLINE void UFlushDCacheLine(unsigned long addr)
1657 {
1660  FlushPipeCCM();
1661  __RWMB();
1662 }
1663 
1675 __STATIC_INLINE void UFlushDCacheLines(unsigned long addr, unsigned long cnt)
1676 {
1677  if (cnt > 0) {
1678  unsigned long i;
1680  for (i = 0; i < cnt; i++) {
1682  }
1683  FlushPipeCCM();
1684  __RWMB();
1685  }
1686 }
1687 
1697 __STATIC_INLINE void MFlushInvalDCacheLine(unsigned long addr)
1698 {
1701  FlushPipeCCM();
1702  __RWMB();
1703 }
1704 
1716 __STATIC_INLINE void MFlushInvalDCacheLines(unsigned long addr, unsigned long cnt)
1717 {
1718  if (cnt > 0) {
1719  unsigned long i;
1721  for (i = 0; i < cnt; i++) {
1723  }
1724  FlushPipeCCM();
1725  __RWMB();
1726  }
1727 }
1728 
1738 __STATIC_INLINE void SFlushInvalDCacheLine(unsigned long addr)
1739 {
1742  FlushPipeCCM();
1743  __RWMB();
1744 }
1745 
1757 __STATIC_INLINE void SFlushInvalDCacheLines(unsigned long addr, unsigned long cnt)
1758 {
1759  if (cnt > 0) {
1760  unsigned long i;
1762  for (i = 0; i < cnt; i++) {
1764  }
1765  FlushPipeCCM();
1766  __RWMB();
1767  }
1768 }
1769 
1779 __STATIC_INLINE void UFlushInvalDCacheLine(unsigned long addr)
1780 {
1783  FlushPipeCCM();
1784  __RWMB();
1785 }
1786 
1798 __STATIC_INLINE void UFlushInvalDCacheLines(unsigned long addr, unsigned long cnt)
1799 {
1800  if (cnt > 0) {
1801  unsigned long i;
1803  for (i = 0; i < cnt; i++) {
1805  }
1806  FlushPipeCCM();
1807  __RWMB();
1808  }
1809 }
1810 
1811 #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1)
1820 #define MInvalDCacheCCacheLine(addr) MInvalDCacheLine(addr)
1821 
1831 #define MInvalDCacheCCacheLines(addr, cnt) MInvalDCacheLines(addr, cnt)
1832 
1841 #define SInvalDCacheCCacheLine(addr) SInvalDCacheLine(addr)
1842 
1852 #define SInvalDCacheCCacheLines(addr, cnt) SInvalDCacheLines(addr, cnt)
1853 
1862 #define UInvalDCacheCCacheLine(addr) UInvalDCacheLine(addr)
1863 
1873 #define UInvalDCacheCCacheLines(addr, cnt) UInvalDCacheLines(addr, cnt)
1882 #define MFlushDCacheCCacheLine(addr) MFlushDCacheLine(addr)
1883 
1893 #define MFlushDCacheCCacheLines(addr, cnt) MFlushDCacheLines(addr, cnt)
1894 
1903 #define SFlushDCacheCCacheLine(addr) SFlushDCacheLine(addr)
1904 
1914 #define SFlushDCacheCCacheLines(addr, cnt) SFlushDCacheLines(addr, cnt)
1915 
1924 #define UFlushDCacheCCacheLine(addr) UFlushDCacheLine(addr)
1925 
1935 #define UFlushDCacheCCacheLines(addr, cnt) UFlushDCacheLines(addr, cnt)
1944 #define MFlushInvalDCacheCCacheLine(addr) MFlushInvalDCacheLine(addr)
1945 
1955 #define MFlushInvalDCacheCCacheLines(addr, cnt) MFlushInvalDCacheLines(addr, cnt)
1956 
1965 #define SFlushInvalDCacheCCacheLine(addr) SFlushInvalDCacheLine(addr)
1966 
1976 #define SFlushInvalDCacheCCacheLines(addr, cnt) SFlushInvalDCacheLines(addr, cnt)
1977 
1986 #define UFlushInvalDCacheCCacheLine(addr) UFlushInvalDCacheLine(addr)
1987 
1997 #define UFlushInvalDCacheCCacheLines(addr, cnt) UFlushInvalDCacheLines(addr, cnt)
1998 #endif /* #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1) */
1999 
2010 __STATIC_INLINE unsigned long MLockDCacheLine(unsigned long addr)
2011 {
2014  FlushPipeCCM();
2015  __RWMB();
2016  return __RV_CSR_READ(CSR_CCM_MDATA);
2017 }
2018 
2031 __STATIC_INLINE unsigned long MLockDCacheLines(unsigned long addr, unsigned long cnt)
2032 {
2033  if (cnt > 0) {
2034  unsigned long i;
2035  unsigned long fail_info = CCM_OP_SUCCESS;
2037  for (i = 0; i < cnt; i++) {
2039  FlushPipeCCM();
2040  __RWMB();
2041  fail_info = __RV_CSR_READ(CSR_CCM_MDATA);
2042  if (CCM_OP_SUCCESS != fail_info) {
2043  return fail_info;
2044  }
2045  }
2046  }
2047  return CCM_OP_SUCCESS;
2048 }
2049 
2060 __STATIC_INLINE unsigned long SLockDCacheLine(unsigned long addr)
2061 {
2064  FlushPipeCCM();
2065  __RWMB();
2066  return __RV_CSR_READ(CSR_CCM_SDATA);
2067 }
2068 
2081 __STATIC_INLINE unsigned long SLockDCacheLines(unsigned long addr, unsigned long cnt)
2082 {
2083  if (cnt > 0) {
2084  unsigned long i;
2085  unsigned long fail_info = CCM_OP_SUCCESS;
2087  for (i = 0; i < cnt; i++) {
2089  FlushPipeCCM();
2090  __RWMB();
2091  fail_info = __RV_CSR_READ(CSR_CCM_SDATA);
2092  if (CCM_OP_SUCCESS != fail_info) {
2093  return fail_info;
2094  }
2095  }
2096  }
2097  return CCM_OP_SUCCESS;
2098 }
2099 
2110 __STATIC_INLINE unsigned long ULockDCacheLine(unsigned long addr)
2111 {
2114  FlushPipeCCM();
2115  __RWMB();
2116  return __RV_CSR_READ(CSR_CCM_UDATA);
2117 }
2118 
2131 __STATIC_INLINE unsigned long ULockDCacheLines(unsigned long addr, unsigned long cnt)
2132 {
2133  if (cnt > 0) {
2134  unsigned long i;
2135  unsigned long fail_info = CCM_OP_SUCCESS;
2137  for (i = 0; i < cnt; i++) {
2139  FlushPipeCCM();
2140  __RWMB();
2141  fail_info = __RV_CSR_READ(CSR_CCM_UDATA);
2142  if (CCM_OP_SUCCESS != fail_info) {
2143  return fail_info;
2144  }
2145  }
2146  }
2147  return CCM_OP_SUCCESS;
2148 }
2149 
2159 __STATIC_INLINE void MUnlockDCacheLine(unsigned long addr)
2160 {
2163  FlushPipeCCM();
2164  __RWMB();
2165 }
2166 
2178 __STATIC_INLINE void MUnlockDCacheLines(unsigned long addr, unsigned long cnt)
2179 {
2180  if (cnt > 0) {
2181  unsigned long i;
2183  for (i = 0; i < cnt; i++) {
2185  }
2186  FlushPipeCCM();
2187  __RWMB();
2188  }
2189 }
2190 
2200 __STATIC_INLINE void SUnlockDCacheLine(unsigned long addr)
2201 {
2204  FlushPipeCCM();
2205  __RWMB();
2206 }
2207 
2219 __STATIC_INLINE void SUnlockDCacheLines(unsigned long addr, unsigned long cnt)
2220 {
2221  if (cnt > 0) {
2222  unsigned long i;
2224  for (i = 0; i < cnt; i++) {
2226  }
2227  FlushPipeCCM();
2228  __RWMB();
2229  }
2230 }
2231 
2241 __STATIC_INLINE void UUnlockDCacheLine(unsigned long addr)
2242 {
2245  FlushPipeCCM();
2246  __RWMB();
2247 }
2248 
2260 __STATIC_INLINE void UUnlockDCacheLines(unsigned long addr, unsigned long cnt)
2261 {
2262  if (cnt > 0) {
2263  unsigned long i;
2265  for (i = 0; i < cnt; i++) {
2267  }
2268  FlushPipeCCM();
2269  __RWMB();
2270  }
2271 }
2272 
2283 {
2285  FlushPipeCCM();
2286  __RWMB();
2287 }
2288 
2299 {
2301  FlushPipeCCM();
2302  __RWMB();
2303 }
2304 
2317 {
2319  FlushPipeCCM();
2320  __RWMB();
2321 }
2322 
2333 {
2335  FlushPipeCCM();
2336  __RWMB();
2337 }
2338 
2349 {
2351  FlushPipeCCM();
2352  __RWMB();
2353 }
2354 
2365 {
2367  FlushPipeCCM();
2368  __RWMB();
2369 }
2370 
2381 {
2383  FlushPipeCCM();
2384  __RWMB();
2385 }
2386 
2397 {
2399  FlushPipeCCM();
2400  __RWMB();
2401 }
2402 
2413 {
2415  FlushPipeCCM();
2416  __RWMB();
2417 }
2418 
2419 #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1)
2430 {
2431  SMPCC_CMD->CC_mCMD = (SMPCC_CMD->CC_mCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2432  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WB_ALL);
2433  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_mCMD) == 0);
2434  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_mCMD);
2435  __RWMB();
2436  return res;
2437 }
2438 
2449 {
2450  SMPCC_CMD->CC_sCMD = (SMPCC_CMD->CC_sCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2451  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WB_ALL);
2452  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_sCMD) == 0);
2453  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_sCMD);
2454  __RWMB();
2455  return res;
2456 }
2457 
2468 {
2469  SMPCC_CMD->CC_uCMD = (SMPCC_CMD->CC_uCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2470  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WB_ALL);
2471  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_uCMD) == 0);
2472  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_uCMD);
2473  __RWMB();
2474  return res;
2475 }
2476 
2487 {
2488  SMPCC_CMD->CC_mCMD = (SMPCC_CMD->CC_mCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2489  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WBINVAL_ALL);
2490  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_mCMD) == 0);
2491  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_mCMD);
2492  __RWMB();
2493  return res;
2494 }
2495 
2506 {
2507  SMPCC_CMD->CC_sCMD = (SMPCC_CMD->CC_sCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2508  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WBINVAL_ALL);
2509  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_sCMD) == 0);
2510  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_sCMD);
2511  __RWMB();
2512  return res;
2513 }
2514 
2525 {
2526  SMPCC_CMD->CC_uCMD = (SMPCC_CMD->CC_uCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2527  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WBINVAL_ALL);
2528  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_uCMD) == 0);
2529  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_uCMD);
2530  __RWMB();
2531  return res;
2532 }
2533 
2543 {
2545  FlushPipeCCM();
2546  SMPCC_CMD->CC_INVALID_ALL = _VAL2FLD(SMPCC_CMD_INVALID_ALL, 1);
2547  while(_FLD2VAL(SMPCC_CMD_INVALID_ALL, SMPCC_CMD->CC_INVALID_ALL));
2548  __RWMB();
2549 }
2550 
2560 {
2562  FlushPipeCCM();
2563  SMPCC_CMD->CC_INVALID_ALL = _VAL2FLD(SMPCC_CMD_INVALID_ALL, 1);
2564  while(_FLD2VAL(SMPCC_CMD_INVALID_ALL, SMPCC_CMD->CC_INVALID_ALL));
2565  __RWMB();
2566 }
2567 
2577 {
2579  FlushPipeCCM();
2580  SMPCC_CMD->CC_INVALID_ALL = _VAL2FLD(SMPCC_CMD_INVALID_ALL, 1);
2581  while(_FLD2VAL(SMPCC_CMD_INVALID_ALL, SMPCC_CMD->CC_INVALID_ALL));
2582  __RWMB();
2583 }
2584 
2595 {
2597  FlushPipeCCM();
2598  SMPCC_CMD->CC_mCMD = (SMPCC_CMD->CC_mCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2599  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WB_ALL);
2600  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_mCMD) == 0);
2601  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_mCMD);
2602  __RWMB();
2603  return res;
2604 }
2605 
2616 {
2618  FlushPipeCCM();
2619  SMPCC_CMD->CC_sCMD = (SMPCC_CMD->CC_sCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2620  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WB_ALL);
2621  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_sCMD) == 0);
2622  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_sCMD);
2623  __RWMB();
2624  return res;
2625 }
2626 
2637 {
2639  FlushPipeCCM();
2640  SMPCC_CMD->CC_uCMD = (SMPCC_CMD->CC_uCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2641  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WB_ALL);
2642  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_uCMD) == 0);
2643  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_uCMD);
2644  __RWMB();
2645  return res;
2646 }
2647 
2658 {
2660  FlushPipeCCM();
2661  SMPCC_CMD->CC_mCMD = (SMPCC_CMD->CC_mCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2662  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WBINVAL_ALL);
2663  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_mCMD) == 0);
2664  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_mCMD);
2665  __RWMB();
2666  return res;
2667 }
2668 
2679 {
2681  FlushPipeCCM();
2682  SMPCC_CMD->CC_sCMD = (SMPCC_CMD->CC_sCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2683  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WBINVAL_ALL);
2684  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_sCMD) == 0);
2685  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_sCMD);
2686  __RWMB();
2687  return res;
2688 }
2689 
2700 {
2702  FlushPipeCCM();
2703  SMPCC_CMD->CC_uCMD = (SMPCC_CMD->CC_uCMD & ~SMPCC_CMD_xCMD_CMD_Msk) |
2704  _VAL2FLD(SMPCC_CMD_xCMD_CMD, SMPCC_CMD_xCMD_CMD_WBINVAL_ALL);
2705  while(_FLD2VAL(SMPCC_CMD_xCMD_COMPLETE, SMPCC_CMD->CC_uCMD) == 0);
2706  int32_t res = _FLD2VAL(SMPCC_CMD_xCMD_RESULT, SMPCC_CMD->CC_uCMD);
2707  __RWMB();
2708  return res;
2709 }
2710 #endif /* #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1) */
2711 
2712 #endif /* defined(__CCM_PRESENT) && (__CCM_PRESENT == 1) */
2713  /* End of Doxygen Group NMSIS_Core_DCache */
2715 #endif /* defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1) */
2716 
2717 #ifdef __cplusplus
2718 }
2719 #endif
2720 #endif /* __CORE_FEATURE_CACHE_H__ */
__STATIC_INLINE void UUnlockCCacheLine(unsigned long addr)
Unlock one Cluster Cache line specified by address in U-Mode.
__STATIC_INLINE void SUnlockCCacheLine(unsigned long addr)
Unlock one Cluster Cache line specified by address in S-Mode.
#define SMPCC_CMD_CTRL_USE_EN_ENABLE
SMPCC_CMD CC_CTRL USE_EN Enable.
__STATIC_INLINE unsigned long MLockCCacheLine(unsigned long addr)
Lock one Cluster Cache line specified by address in M-Mode.
#define SMPCC_CMD
SMPCC CMD configuration struct.
__STATIC_INLINE unsigned long SLockCCacheLine(unsigned long addr)
Lock one Cluster Cache line specified by address in S-Mode.
__STATIC_INLINE void UUnlockCCacheLines(unsigned long addr, unsigned long cnt)
Unlock several Cluster Cache lines specified by address in U-Mode.
#define SMPCC_CMD_xCMD_CMD_WB_ALL
SMPCC_CMD xCMD CMD WB_ALL.
__STATIC_INLINE unsigned long MLockCCacheLines(unsigned long addr, unsigned long cnt)
Lock several Cluster Cache lines specified by address in M-Mode.
__STATIC_INLINE unsigned long ULockCCacheLine(unsigned long addr)
Lock one Cluster Cache line specified by address in U-Mode.
__STATIC_INLINE void SUnlockCCacheLines(unsigned long addr, unsigned long cnt)
Unlock several Cluster Cache lines specified by address in S-Mode.
__STATIC_INLINE void MUnlockCCacheLines(unsigned long addr, unsigned long cnt)
Unlock several Cluster Cache lines specified by address in M-Mode.
#define SMPCC_CMD_xCMD_CMD_WBINVAL_ALL
SMPCC_CMD xCMD CMD WBINVAL_ALL.
#define SMPCC_CMD_xCMD_CMD_Msk
SMPCC_CMD register xCMD field CMD Mask.
#define SMPCC_CMD_CTRL_USE_EN_DISABLE
SMPCC_CMD CC_CTRL USE_EN Disable.
#define SMPCC_CMD_CTRL_SUP_EN_DISABLE
SMPCC_CMD CC_CTRL SUP_EN Disable.
__STATIC_INLINE unsigned long ULockCCacheLines(unsigned long addr, unsigned long cnt)
Lock several Cluster Cache lines specified by address in U-Mode.
__STATIC_INLINE unsigned long SLockCCacheLines(unsigned long addr, unsigned long cnt)
Lock several Cluster Cache lines specified by address in S-Mode.
#define SMPCC_CMD_CTRL_SUP_EN_ENABLE
SMPCC_CMD CC_CTRL SUP_EN Enable.
__STATIC_INLINE void MUnlockCCacheLine(unsigned long addr)
Unlock one Cluster Cache line specified by address in M-Mode.
#define MCACHE_CTL_IC_EN
#define MCACHE_CTL_DC_ECC_EN
#define MCFG_INFO_DCACHE
#define MCACHE_CTL_IC_ECC_EN
#define MCFG_INFO_ICACHE
#define MCACHE_CTL_DC_EN
#define __RV_CSR_CLEAR(csr, val)
CSR operation Macro for csrc instruction.
#define __RV_CSR_READ(csr)
CSR operation Macro for csrr instruction.
#define __RWMB()
Read & Write Memory barrier.
#define __RV_CSR_WRITE(csr, val)
CSR operation Macro for csrw instruction.
#define __RV_CSR_SET(csr, val)
CSR operation Macro for csrs instruction.
#define CSR_CCM_MCOMMAND
#define CSR_CCM_SCOMMAND
#define CSR_MICFG_INFO
#define CSR_CCM_MBEGINADDR
#define CSR_CCM_UCOMMAND
#define CSR_CCM_SDATA
#define CSR_CCM_SUEN
#define CSR_CCM_MDATA
#define CSR_MCACHE_CTL
#define CSR_CCM_FPIPE
#define CSR_MCFG_INFO
#define CSR_CCM_SBEGINADDR
#define CSR_CCM_UBEGINADDR
#define CSR_MDCFG_INFO
#define CSR_CCM_UDATA
CCM_OP_FINFO_Type
Cache CCM Operation Fail Info.
__STATIC_FORCEINLINE void FlushPipeCCM(void)
Flush pipeline after CCM operation.
CCM_CMD_Type
Cache CCM Command Types.
__STATIC_FORCEINLINE void DisableSUCCM(void)
Disable CCM operation in Supervisor/User Mode.
#define CCM_SUEN_SUEN_Msk
CSR CCM_SUEN: SUEN Mask.
__STATIC_FORCEINLINE void EnableSUCCM(void)
Enable CCM operation in Supervisor/User Mode.
@ CCM_OP_REFILL_BUS_ERR
Refill has Bus Error.
@ CCM_OP_ECC_ERR
Deprecated, ECC Error, this error code is removed in later Nuclei CCM RTL design, please don't use it...
@ CCM_OP_PERM_CHECK_ERR
PMP/sPMP/Page-Table X(I-Cache)/R(D-Cache) permission check failed, or belong to Device/Non-Cacheable ...
@ CCM_OP_SUCCESS
Lock Succeed.
@ CCM_OP_EXCEED_ERR
Exceed the the number of lockable ways(N-Way I/D-Cache, lockable is N-1)
@ CCM_DC_WB
Flush the specific D-Cache line and Cluster Cache line specified by CSR CCM_XBEGINADDR.
@ CCM_DC_INVAL
Unlock and invalidate D-Cache line and Cluster Cache line specified by CSR CCM_XBEGINADDR.
@ CCM_DC_WBINVAL
Unlock, flush and invalidate the specific D-Cache line and Cluster Cache line specified by CSR CCM_XB...
@ CCM_DC_LOCK
Lock the specific D-Cache line specified by CSR CCM_XBEGINADDR.
@ CCM_IC_INVAL
Unlock and invalidate I-Cache line specified by CSR CCM_XBEGINADDR.
@ CCM_IC_LOCK
Lock the specific I-Cache line specified by CSR CCM_XBEGINADDR.
@ CCM_DC_WB_ALL
Flush all the valid and dirty D-Cache lines.
@ CCM_DC_INVAL_ALL
Unlock and invalidate all the D-Cache lines.
@ CCM_IC_INVAL_ALL
Unlock and invalidate all the I-Cache lines.
@ CCM_CC_LOCK
Lock the specific Cluster Cache line specified by CSR CCM_XBEGINADDR.
@ CCM_DC_WBINVAL_ALL
Unlock and flush and invalidate all the valid and dirty D-Cache lines.
@ CCM_DC_UNLOCK
Unlock the specific D-Cache line specified by CSR CCM_XBEGINADDR.
@ CCM_CC_UNLOCK
Unlock the specific Cluster Cache line specified by CSR CCM_XBEGINADDR.
@ CCM_IC_UNLOCK
Unlock the specific I-Cache line specified by CSR CCM_XBEGINADDR.
#define __STATIC_FORCEINLINE
Define a static function that should be always inlined by the compiler.
Definition: nmsis_gcc.h:70
#define __STATIC_INLINE
Define a static function that may be inlined by the compiler.
Definition: nmsis_gcc.h:65
__STATIC_INLINE void MFlushDCache(void)
Flush all D-Cache lines in M-Mode.
__STATIC_INLINE unsigned long SLockDCacheLine(unsigned long addr)
Lock one D-Cache line specified by address in S-Mode.
__STATIC_INLINE void MInvalDCacheLines(unsigned long addr, unsigned long cnt)
Invalidate several D-Cache lines specified by address in M-Mode.
__STATIC_INLINE void UInvalDCacheLine(unsigned long addr)
Invalidate one D-Cache line specified by address in U-Mode.
__STATIC_INLINE void UUnlockDCacheLine(unsigned long addr)
Unlock one D-Cache line specified by address in U-Mode.
__STATIC_INLINE void UInvalDCache(void)
Invalidate all D-Cache lines in U-Mode.
__STATIC_INLINE void UFlushDCacheLines(unsigned long addr, unsigned long cnt)
Flush several D-Cache lines specified by address in U-Mode.
__STATIC_INLINE int32_t SFlushDCacheCCache(void)
Flush all D-Cache and Cluster Cache in S-Mode.
__STATIC_INLINE void SInvalDCacheCCache(void)
Invalidate all D-Cache and Cluster Cache in S-Mode.
__STATIC_INLINE void MFlushDCacheLines(unsigned long addr, unsigned long cnt)
Flush several D-Cache lines specified by address in M-Mode.
__STATIC_INLINE unsigned long ULockDCacheLines(unsigned long addr, unsigned long cnt)
Lock several D-Cache lines specified by address in U-Mode.
__STATIC_INLINE int32_t UFlushDCacheCCache(void)
Flush all D-Cache and Cluster Cache in U-Mode.
__STATIC_INLINE void MInvalDCacheLine(unsigned long addr)
Invalidate one D-Cache line specified by address in M-Mode.
__STATIC_INLINE void SInvalDCacheLines(unsigned long addr, unsigned long cnt)
Invalidate several D-Cache lines specified by address in S-Mode.
__STATIC_INLINE int32_t GetDCacheInfo(CacheInfo_Type *info)
Get D-Cache Information.
__STATIC_INLINE int32_t SFlushInvalCCache(void)
Flush and invalidate all Cluster Cache in S-Mode.
__STATIC_INLINE void SUnlockDCacheLine(unsigned long addr)
Unlock one D-Cache line specified by address in S-Mode.
__STATIC_INLINE void UFlushDCache(void)
Flush all D-Cache lines in U-Mode.
__STATIC_INLINE void MUnlockDCacheLine(unsigned long addr)
Unlock one D-Cache line specified by address in M-Mode.
__STATIC_INLINE void MFlushInvalDCache(void)
Flush and invalidate all D-Cache lines in M-Mode.
__STATIC_INLINE void UFlushDCacheLine(unsigned long addr)
Flush one D-Cache line specified by address in U-Mode.
__STATIC_FORCEINLINE void EnableDCacheECC(void)
Enable DCache ECC.
__STATIC_INLINE void SUnlockDCacheLines(unsigned long addr, unsigned long cnt)
Unlock several D-Cache lines specified by address in S-Mode.
__STATIC_INLINE void MFlushInvalDCacheLine(unsigned long addr)
Flush and invalidate one D-Cache line specified by address in M-Mode.
__STATIC_INLINE void UFlushInvalDCacheLine(unsigned long addr)
Flush and invalidate one D-Cache line specified by address in U-Mode.
__STATIC_INLINE int32_t UFlushInvalDCacheCCache(void)
Flush and invalidate all D-Cache and Cluster Cache in U-Mode.
__STATIC_INLINE unsigned long ULockDCacheLine(unsigned long addr)
Lock one D-Cache line specified by address in U-Mode.
__STATIC_INLINE void SFlushInvalDCacheLine(unsigned long addr)
Flush and invalidate one D-Cache line specified by address in S-Mode.
__STATIC_INLINE void SFlushDCache(void)
Flush all D-Cache lines in S-Mode.
__STATIC_INLINE int32_t DCachePresent(void)
Check DCache Unit Present or Not.
__STATIC_INLINE void MUnlockDCacheLines(unsigned long addr, unsigned long cnt)
Unlock several D-Cache lines specified by address in M-Mode.
__STATIC_INLINE int32_t UFlushCCache(void)
Flush all Cluster Cache in U-Mode.
__STATIC_INLINE void SFlushInvalDCacheLines(unsigned long addr, unsigned long cnt)
Flush and invalidate several D-Cache lines specified by address in S-Mode.
__STATIC_INLINE void UUnlockDCacheLines(unsigned long addr, unsigned long cnt)
Unlock several D-Cache lines specified by address in U-Mode.
__STATIC_INLINE void MInvalDCacheCCache(void)
Invalidate all D-Cache and Cluster Cache in M-Mode.
__STATIC_INLINE int32_t SFlushInvalDCacheCCache(void)
Flush and invalidate all D-Cache and Cluster Cache in S-Mode.
__STATIC_INLINE void SFlushDCacheLines(unsigned long addr, unsigned long cnt)
Flush several D-Cache lines specified by address in S-Mode.
__STATIC_FORCEINLINE void DisableDCache(void)
Disable DCache.
__STATIC_INLINE unsigned long MLockDCacheLine(unsigned long addr)
Lock one D-Cache line specified by address in M-Mode.
__STATIC_INLINE void UInvalDCacheCCache(void)
Invalidate all D-Cache and Cluster Cache in U-Mode.
__STATIC_INLINE void MFlushInvalDCacheLines(unsigned long addr, unsigned long cnt)
Flush and invalidate several D-Cache lines specified by address in M-Mode.
__STATIC_INLINE void SInvalDCacheLine(unsigned long addr)
Invalidate one D-Cache line specified by address in S-Mode.
__STATIC_INLINE void UInvalDCacheLines(unsigned long addr, unsigned long cnt)
Invalidate several D-Cache lines specified by address in U-Mode.
__STATIC_INLINE void UFlushInvalDCache(void)
Flush and invalidate all D-Cache lines in U-Mode.
__STATIC_FORCEINLINE void DisableDCacheECC(void)
Disable DCache ECC.
__STATIC_INLINE unsigned long MLockDCacheLines(unsigned long addr, unsigned long cnt)
Lock several D-Cache lines specified by address in M-Mode.
__STATIC_INLINE int32_t UFlushInvalCCache(void)
Flush and invalidate all Cluster Cache in U-Mode.
__STATIC_INLINE void MFlushDCacheLine(unsigned long addr)
Flush one D-Cache line specified by address in M-Mode.
__STATIC_INLINE void SInvalDCache(void)
Invalidate all D-Cache lines in S-Mode.
__STATIC_INLINE int32_t SFlushCCache(void)
Flush all Cluster Cache in S-Mode.
__STATIC_INLINE int32_t MFlushDCacheCCache(void)
Flush all D-Cache and Cluster Cache in M-Mode.
__STATIC_INLINE void MInvalDCache(void)
Invalidate all D-Cache lines in M-Mode.
__STATIC_INLINE int32_t MFlushInvalCCache(void)
Flush and invalidate all Cluster Cache in M-Mode.
__STATIC_INLINE int32_t MFlushInvalDCacheCCache(void)
Flush and invalidate all D-Cache and Cluster Cache in M-Mode.
__STATIC_INLINE void SFlushInvalDCache(void)
Flush and invalidate all D-Cache lines in S-Mode.
__STATIC_INLINE void UFlushInvalDCacheLines(unsigned long addr, unsigned long cnt)
Flush and invalidate several D-Cache lines specified by address in U-Mode.
__STATIC_FORCEINLINE void EnableDCache(void)
Enable DCache.
__STATIC_INLINE unsigned long SLockDCacheLines(unsigned long addr, unsigned long cnt)
Lock several D-Cache lines specified by address in S-Mode.
__STATIC_INLINE int32_t MFlushCCache(void)
Flush all Cluster Cache in M-Mode.
__STATIC_INLINE void SFlushDCacheLine(unsigned long addr)
Flush one D-Cache line specified by address in S-Mode.
__STATIC_INLINE unsigned long MLockICacheLines(unsigned long addr, unsigned long cnt)
Lock several I-Cache lines specified by address in M-Mode.
__STATIC_INLINE void MInvalICacheLines(unsigned long addr, unsigned long cnt)
Invalidate several I-Cache lines specified by address in M-Mode.
__STATIC_INLINE void SInvalICacheCCache(void)
Invalidate all I-Cache and Cluster Cache in S-Mode.
__STATIC_INLINE void SInvalCCache(void)
Invalidate all Cluster Cache in S-Mode.
__STATIC_INLINE void MInvalCCache(void)
Invalidate all Cluster Cache in M-Mode.
__STATIC_INLINE void UUnlockICacheLines(unsigned long addr, unsigned long cnt)
Unlock several I-Cache lines specified by address in U-Mode.
__STATIC_INLINE void MInvalICacheCCache(void)
Invalidate all I-Cache and Cluster Cache in M-Mode.
__STATIC_INLINE void MInvalICacheCCacheLines(unsigned long addr, unsigned long cnt)
Invalidate several I-Cache and Cluster Cache lines specified by address in M-Mode.
__STATIC_INLINE void MInvalICache(void)
Invalidate all I-Cache lines in M-Mode.
__STATIC_INLINE void UInvalICacheCCache(void)
Invalidate all I-Cache and Cluster Cache in U-Mode.
__STATIC_INLINE void MInvalICacheCCacheLine(unsigned long addr)
Invalidate one I-Cache and Cluster Cache line specified by address in M-Mode.
__STATIC_INLINE unsigned long ULockICacheLines(unsigned long addr, unsigned long cnt)
Lock several I-Cache lines specified by address in U-Mode.
__STATIC_INLINE void SInvalICacheLine(unsigned long addr)
Invalidate one I-Cache line specified by address in S-Mode.
__STATIC_INLINE unsigned long MLockICacheLine(unsigned long addr)
Lock one I-Cache line specified by address in M-Mode.
__STATIC_FORCEINLINE void DisableICache(void)
Disable ICache.
__STATIC_INLINE void UInvalICacheCCacheLine(unsigned long addr)
Invalidate one I-Cache and Cluster Cache line specified by address in U-Mode.
__STATIC_INLINE unsigned long ULockICacheLine(unsigned long addr)
Lock one I-Cache line specified by address in U-Mode.
__STATIC_FORCEINLINE void EnableICache(void)
Enable ICache.
__STATIC_INLINE int32_t ICachePresent(void)
Check ICache Unit Present or Not.
__STATIC_INLINE void SInvalICacheLines(unsigned long addr, unsigned long cnt)
Invalidate several I-Cache lines specified by address in S-Mode.
__STATIC_INLINE void UInvalICache(void)
Invalidate all I-Cache lines in U-Mode.
__STATIC_INLINE void MUnlockICacheLine(unsigned long addr)
Unlock one I-Cache line specified by address in M-Mode.
__STATIC_INLINE void UInvalICacheLines(unsigned long addr, unsigned long cnt)
Invalidate several I-Cache lines specified by address in U-Mode.
__STATIC_FORCEINLINE void EnableICacheECC(void)
Enable ICache ECC.
__STATIC_INLINE int32_t GetICacheInfo(CacheInfo_Type *info)
Get I-Cache Information.
__STATIC_INLINE void UUnlockICacheLine(unsigned long addr)
Unlock one I-Cache line specified by address in U-Mode.
__STATIC_FORCEINLINE void DisableICacheECC(void)
Disable ICache ECC.
__STATIC_INLINE void SInvalICacheCCacheLine(unsigned long addr)
Invalidate one I-Cache and Cluster Cache line specified by address in S-Mode.
__STATIC_INLINE void SUnlockICacheLines(unsigned long addr, unsigned long cnt)
Unlock several I-Cache lines specified by address in S-Mode.
__STATIC_INLINE void UInvalICacheLine(unsigned long addr)
Invalidate one I-Cache line specified by address in U-Mode.
__STATIC_INLINE unsigned long SLockICacheLine(unsigned long addr)
Lock one I-Cache line specified by address in S-Mode.
__STATIC_INLINE void MUnlockICacheLines(unsigned long addr, unsigned long cnt)
Unlock several I-Cache lines specified by address in M-Mode.
__STATIC_INLINE void UInvalCCache(void)
Invalidate all Cluster Cache in U-Mode.
__STATIC_INLINE void SInvalICache(void)
Invalidate all I-Cache lines in S-Mode.
__STATIC_INLINE void SUnlockICacheLine(unsigned long addr)
Unlock one I-Cache line specified by address in S-Mode.
__STATIC_INLINE unsigned long SLockICacheLines(unsigned long addr, unsigned long cnt)
Lock several I-Cache lines specified by address in S-Mode.
__STATIC_INLINE void UInvalICacheCCacheLines(unsigned long addr, unsigned long cnt)
Invalidate several I-Cache and Cluster Cache lines specified by address in U-Mode.
__STATIC_INLINE void MInvalICacheLine(unsigned long addr)
Invalidate one I-Cache line specified by address in M-Mode.
__STATIC_INLINE void SInvalICacheCCacheLines(unsigned long addr, unsigned long cnt)
Invalidate several I-Cache and Cluster Cache lines specified by address in S-Mode.
#define _FLD2VAL(field, value)
Mask and shift a register value to extract a bit filed value.
#define _VAL2FLD(field, value)
Mask and shift a bit field value for use in a register bit range.
#define __IM
Defines 'read only' structure member permissions.
#define __IOM
Defines 'read/write' structure member permissions.
Cache Information Type.
uint32_t setperway
Cache set per way.
uint32_t ways
Cache ways.
uint32_t linesize
Cache Line size in bytes.
uint32_t size
Cache total size in bytes.
Cluster Cache Control and Command Registers.
__IOM uint32_t CC_CTRL
Offset: 0x10 (R/W) Cluster Cache Control Register.
__IOM uint32_t CC_uCMD
Offset: 0xC4 (R/W) Cluster Cache U-mode Command Register.
__IOM uint32_t CC_INVALID_ALL
Offset: 0xDC (R/W) Cluster Cache Invalid All Register.
__IOM uint32_t CC_mCMD
Offset: 0x14 (R/W) Cluster Cache M-mode Command Register.
__IOM uint32_t CC_sCMD
Offset: 0xC0 (R/W) Cluster Cache S-mode Command Register.
Union type to access MDCFG_INFO CSR register.
rv_csr_t set
bit: 0..3 D-Cache sets per way
struct CSR_MDCFGINFO_Type::@16 b
Structure used for bit access.
rv_csr_t d
Type used for csr data access.
rv_csr_t lsize
bit: 7..9 D-Cache line size
rv_csr_t way
bit: 4..6 D-Cache way
Union type to access MICFG_INFO CSR register.
rv_csr_t d
Type used for csr data access.
rv_csr_t set
bit: 0..3 I-Cache sets per way
rv_csr_t lsize
bit: 7..9 I-Cache line size
struct CSR_MICFGINFO_Type::@15 b
Structure used for bit access.
rv_csr_t way
bit: 4..6 I-Cache way