NMSIS-Core  Version 1.4.0
NMSIS-Core support for Nuclei processor-based devices
riscv_encoding.h
1 /*
2  * Copyright (c) 2019 Nuclei Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Licensed under the Apache License, Version 2.0 (the License); you may
7  * not use this file except in compliance with the License.
8  * You may obtain a copy of the License at
9  *
10  * www.apache.org/licenses/LICENSE-2.0
11  *
12  * Unless required by applicable law or agreed to in writing, software
13  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15  * See the License for the specific language governing permissions and
16  * limitations under the License.
17  */
18 #ifndef __RISCV_ENCODING_H__
19 #define __RISCV_ENCODING_H__
20 
21 #ifdef __cplusplus
22  extern "C" {
23 #endif
24 
25 #include "riscv_bits.h"
26 
36 /* === Standard CSR bit mask === */
37 #define MSTATUS_UIE 0x00000001
38 #define MSTATUS_SIE 0x00000002
39 #define MSTATUS_HIE 0x00000004
40 #define MSTATUS_MIE 0x00000008
41 #define MSTATUS_UPIE 0x00000010
42 #define MSTATUS_SPIE 0x00000020
43 #define MSTATUS_UBE 0x00000040
44 #define MSTATUS_MPIE 0x00000080
45 #define MSTATUS_SPP 0x00000100
46 #define MSTATUS_VS 0x00000600
47 #define MSTATUS_MPP 0x00001800
48 #define MSTATUS_FS 0x00006000
49 #define MSTATUS_XS 0x00018000
50 #define MSTATUS_MPRV 0x00020000
51 #define MSTATUS_SUM 0x00040000
52 #define MSTATUS_MXR 0x00080000
53 #define MSTATUS_TVM 0x00100000
54 #define MSTATUS_TW 0x00200000
55 #define MSTATUS_TSR 0x00400000
56 #define MSTATUS32_SD 0x80000000
57 #define MSTATUS_UXL 0x0000000300000000
58 #define MSTATUS_SXL 0x0000000C00000000
59 #define MSTATUS_SBE 0x0000001000000000
60 #define MSTATUS_MBE 0x0000002000000000
61 #define MSTATUS_GVA 0x0000004000000000
62 #define MSTATUS_MPV 0x0000008000000000
63 #define MSTATUS64_SD 0x8000000000000000
64 
65 #define MSTATUS_FS_INITIAL 0x00002000
66 #define MSTATUS_FS_CLEAN 0x00004000
67 #define MSTATUS_FS_DIRTY 0x00006000
68 
69 #define MSTATUS_VS_INITIAL 0x00000200
70 #define MSTATUS_VS_CLEAN 0x00000400
71 #define MSTATUS_VS_DIRTY 0x00000600
72 
73 #define MSTATUSH_SBE 0x00000010
74 #define MSTATUSH_MBE 0x00000020
75 #define MSTATUSH_GVA 0x00000040
76 #define MSTATUSH_MPV 0x00000080
77 
78 #define SSTATUS_UIE 0x00000001
79 #define SSTATUS_SIE 0x00000002
80 #define SSTATUS_UPIE 0x00000010
81 #define SSTATUS_SPIE 0x00000020
82 #define SSTATUS_UBE 0x00000040
83 #define SSTATUS_SPP 0x00000100
84 #define SSTATUS_VS 0x00000600
85 #define SSTATUS_FS 0x00006000
86 #define SSTATUS_XS 0x00018000
87 #define SSTATUS_SUM 0x00040000
88 #define SSTATUS_MXR 0x00080000
89 #define SSTATUS32_SD 0x80000000
90 #define SSTATUS_UXL 0x0000000300000000
91 #define SSTATUS64_SD 0x8000000000000000
92 
93 #define USTATUS_UIE 0x00000001
94 #define USTATUS_UPIE 0x00000010
95 
96 #define DCSR_XDEBUGVER (3U<<30)
97 #define DCSR_NDRESET (1<<29)
98 #define DCSR_FULLRESET (1<<28)
99 #define DCSR_EBREAKM (1<<15)
100 #define DCSR_EBREAKH (1<<14)
101 #define DCSR_EBREAKS (1<<13)
102 #define DCSR_EBREAKU (1<<12)
103 #define DCSR_STOPCYCLE (1<<10)
104 #define DCSR_STOPTIME (1<<9)
105 #define DCSR_CAUSE (7<<6)
106 #define DCSR_DEBUGINT (1<<5)
107 #define DCSR_HALT (1<<3)
108 #define DCSR_STEP (1<<2)
109 #define DCSR_PRV (3<<0)
110 
111 #define DCSR_CAUSE_NONE 0
112 #define DCSR_CAUSE_SWBP 1
113 #define DCSR_CAUSE_HWBP 2
114 #define DCSR_CAUSE_DEBUGINT 3
115 #define DCSR_CAUSE_STEP 4
116 #define DCSR_CAUSE_HALT 5
117 
118 #define MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))
119 #define MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))
120 #define MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))
121 
122 #define MCONTROL_SELECT (1<<19)
123 #define MCONTROL_TIMING (1<<18)
124 #define MCONTROL_ACTION (0x3f<<12)
125 #define MCONTROL_CHAIN (1<<11)
126 #define MCONTROL_MATCH (0xf<<7)
127 #define MCONTROL_M (1<<6)
128 #define MCONTROL_H (1<<5)
129 #define MCONTROL_S (1<<4)
130 #define MCONTROL_U (1<<3)
131 #define MCONTROL_EXECUTE (1<<2)
132 #define MCONTROL_STORE (1<<1)
133 #define MCONTROL_LOAD (1<<0)
134 
135 #define MCONTROL_TYPE_NONE 0
136 #define MCONTROL_TYPE_MATCH 2
137 
138 #define MCONTROL_ACTION_DEBUG_EXCEPTION 0
139 #define MCONTROL_ACTION_DEBUG_MODE 1
140 #define MCONTROL_ACTION_TRACE_START 2
141 #define MCONTROL_ACTION_TRACE_STOP 3
142 #define MCONTROL_ACTION_TRACE_EMIT 4
143 
144 #define MCONTROL_MATCH_EQUAL 0
145 #define MCONTROL_MATCH_NAPOT 1
146 #define MCONTROL_MATCH_GE 2
147 #define MCONTROL_MATCH_LT 3
148 #define MCONTROL_MATCH_MASK_LOW 4
149 #define MCONTROL_MATCH_MASK_HIGH 5
150 
151 #define MIP_SSIP (1 << IRQ_S_SOFT)
152 #define MIP_HSIP (1 << IRQ_H_SOFT)
153 #define MIP_MSIP (1 << IRQ_M_SOFT)
154 #define MIP_STIP (1 << IRQ_S_TIMER)
155 #define MIP_HTIP (1 << IRQ_H_TIMER)
156 #define MIP_MTIP (1 << IRQ_M_TIMER)
157 #define MIP_SEIP (1 << IRQ_S_EXT)
158 #define MIP_HEIP (1 << IRQ_H_EXT)
159 #define MIP_MEIP (1 << IRQ_M_EXT)
160 
161 #define MIE_SSIE MIP_SSIP
162 #define MIE_HSIE MIP_HSIP
163 #define MIE_MSIE MIP_MSIP
164 #define MIE_STIE MIP_STIP
165 #define MIE_HTIE MIP_HTIP
166 #define MIE_MTIE MIP_MTIP
167 #define MIE_SEIE MIP_SEIP
168 #define MIE_HEIE MIP_HEIP
169 #define MIE_MEIE MIP_MEIP
170 
171 #define SIP_SSIP MIP_SSIP
172 #define SIP_STIP MIP_STIP
173 #define SIP_SEIP MIP_SEIP
174 
175 #define SIE_SSIE MIP_SSIP
176 #define SIE_STIE MIP_STIP
177 #define SIE_SEIE MIP_SEIP
178 
179 #define MCAUSE_INTR (1ULL << (__riscv_xlen - 1))
180 #define MCAUSE_CAUSE 0x00000FFFUL
181 #define SCAUSE_INTR MCAUSE_INTR
182 #define SCAUSE_CAUSE 0x000003FFUL
183 
184 #define MENVCFG_CBIE_EN (0x11 << 4)
185 #define MENVCFG_CBIE_FLUSH (0x01 << 4)
186 #define MENVCFG_CBIE_INVAL (0x11 << 4)
187 #define SENVCFG_CBIE_EN (0x11 << 4)
188 #define SENVCFG_CBIE_FLUSH (0x01 << 4)
189 #define SENVCFG_CBIE_INVAL (0x11 << 4)
190 
191 #define MENVCFG_FIOM 0x00000001
192 #define MENVCFG_LPE 0x00000004
193 #define MENVCFG_SSE 0x00000008
194 #define MENVCFG_CBIE 0x00000030
195 #define MENVCFG_CBCFE 0x00000040
196 #define MENVCFG_CBZE 0x00000080
197 #define MENVCFG_PMM 0x0000000300000000
198 #define MENVCFG_DTE 0x0800000000000000
199 #define MENVCFG_ADUE 0x2000000000000000
200 #define MENVCFG_PBMTE 0x4000000000000000
201 #define MENVCFG_STCE 0x8000000000000000
202 
203 #define MENVCFGH_DTE 0x08000000
204 #define MENVCFGH_ADUE 0x20000000
205 #define MENVCFGH_PBMTE 0x40000000
206 #define MENVCFGH_STCE 0x80000000
207 
208 #define SENVCFG_FIOM 0x00000001
209 #define SENVCFG_LPE 0x00000004
210 #define SENVCFG_SSE 0x00000008
211 #define SENVCFG_CBIE 0x00000030
212 #define SENVCFG_CBCFE 0x00000040
213 #define SENVCFG_CBZE 0x00000080
214 #define SENVCFG_PMM 0x0000000300000000
215 
216 /* === P-ext CSR bit mask === */
217 
218 #define UCODE_OV (0x1)
219 
220 /* === Nuclei custom CSR bit mask === */
221 #define CSR_MCACHE_CTL_IE 0x00000001
222 #define CSR_MCACHE_CTL_DE 0x00010000
223 
224 #define WFE_WFE (0x1)
225 #define TXEVT_TXEVT (0x1)
226 #define SLEEPVALUE_SLEEPVALUE (0x1)
227 
228 #define MCOUNTEREN_CY_SHIFT 0
229 #define MCOUNTEREN_TIME_SHIFT 1
230 #define MCOUNTEREN_IR_SHIFT 2
231 
232 #define MCOUNTEREN_CY (1U << MCOUNTEREN_CY_SHIFT)
233 #define MCOUNTEREN_TIME (1U << MCOUNTEREN_TIME_SHIFT)
234 #define MCOUNTEREN_IR (1U << MCOUNTEREN_IR_SHIFT)
235 
236 #define MCOUNTINHIBIT_CY MCOUNTEREN_CY
237 #define MCOUNTINHIBIT_IR MCOUNTEREN_IR
238 
239 #define MILM_CTL_ILM_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10)
240 #define MILM_CTL_ILM_ECC_CHK_EN (1<<4)
241 #define MILM_CTL_ILM_RWECC (1<<3)
242 #define MILM_CTL_ILM_ECC_INJ_EN (1<<3)
243 #define MILM_CTL_ILM_ECC_EXCP_EN (1<<2)
244 #define MILM_CTL_ILM_ECC_EN (1<<1)
245 #define MILM_CTL_ILM_EN (1<<0)
246 
247 #define MDLM_CTL_DLM_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10)
248 #define MDLM_CTL_DLM_ECC_CHK_EN (1<<4)
249 #define MDLM_CTL_DLM_RWECC (1<<3)
250 #define MDLM_CTL_DLM_ECC_INJ_EN (1<<3)
251 #define MDLM_CTL_DLM_ECC_EXCP_EN (1<<2)
252 #define MDLM_CTL_DLM_ECC_EN (1<<1)
253 #define MDLM_CTL_DLM_EN (1<<0)
254 
255 #define MSUBM_PTYP (0x3<<8)
256 #define MSUBM_TYP (0x3<<6)
257 
258 #define MDCAUSE_MDCAUSE (0x7)
259 
260 #define MMISC_CTL_LDSPEC_ENABLE (1<<12)
261 #define MMISC_CTL_SIJUMP_ENABLE (1<<11)
262 #define MMISC_CTL_IMRETURN_ENABLE (1<<10)
263 #define MMISC_CTL_NMI_CAUSE_FFF (1<<9)
264 #define MMISC_CTL_CODE_BUS_ERR (1<<8)
265 #define MMISC_CTL_MISALIGN (1<<6)
266 #define MMISC_CTL_ZC (1<<7)
267 #define MMISC_CTL_BPU (1<<3)
268 
269 #define MCACHE_CTL_IC_EN (1<<0)
270 #define MCACHE_CTL_IC_SCPD_MOD (1<<1)
271 #define MCACHE_CTL_IC_ECC_EN (1<<2)
272 #define MCACHE_CTL_IC_ECC_EXCP_EN (1<<3)
273 #define MCACHE_CTL_IC_TRAM_ECC_INJ_EN (1<<4)
274 #define MCACHE_CTL_IC_RWTECC (1<<4)
275 #define MCACHE_CTL_IC_RWDECC (1<<5)
276 #define MCACHE_CTL_IC_DRAM_ECC_INJ_EN (1<<5)
277 #define MCACHE_CTL_IC_PF_EN (1<<6)
278 #define MCACHE_CTL_IC_CANCEL_EN (1<<7)
279 #define MCACHE_CTL_IC_ECC_CHK_EN (1<<8)
280 #define MCACHE_CTL_DC_EN (1<<16)
281 #define MCACHE_CTL_DC_ECC_EN (1<<17)
282 #define MCACHE_CTL_DC_ECC_EXCP_EN (1<<18)
283 #define MCACHE_CTL_DC_TRAM_ECC_INJ_EN (1<<19)
284 #define MCACHE_CTL_DC_RWTECC (1<<19)
285 #define MCACHE_CTL_DC_RWDECC (1<<20)
286 #define MCACHE_CTL_DC_DRAM_ECC_INJ_EN (1<<20)
287 #define MCACHE_CTL_DC_ECC_CHK_EN (1<<21)
288 
289 #define MTVT2_MTVT2EN (1<<0)
290 #define MTVT2_COMMON_CODE_ENTRY (((1ULL<<((__riscv_xlen)-2))-1)<<2)
291 
292 #define MCFG_INFO_TEE (1<<0)
293 #define MCFG_INFO_ECC (1<<1)
294 #define MCFG_INFO_CLIC (1<<2)
295 #define MCFG_INFO_PLIC (1<<3)
296 #define MCFG_INFO_FIO (1<<4)
297 #define MCFG_INFO_PPI (1<<5)
298 #define MCFG_INFO_NICE (1<<6)
299 #define MCFG_INFO_ILM (1<<7)
300 #define MCFG_INFO_DLM (1<<8)
301 #define MCFG_INFO_ICACHE (1<<9)
302 #define MCFG_INFO_DCACHE (1<<10)
303 #define MCFG_INFO_SMP (1<<11)
304 #define MCFG_INFO_DSP_N1 (1<<12)
305 #define MCFG_INFO_DSP_N2 (1<<13)
306 #define MCFG_INFO_DSP_N3 (1<<14)
307 #define MCFG_INFO_IREGION_EXIST (1<<16)
308 #define MCFG_INFO_VP (0x3<<17)
309 
310 #define MICFG_IC_SET (0xF<<0)
311 #define MICFG_IC_WAY (0x7<<4)
312 #define MICFG_IC_LSIZE (0x7<<7)
313 #define MICFG_IC_ECC (0x1<<10)
314 #define MICFG_ILM_SIZE (0x1F<<16)
315 #define MICFG_ILM_XONLY (0x1<<21)
316 #define MICFG_ILM_ECC (0x1<<22)
317 
318 #define MDCFG_DC_SET (0xF<<0)
319 #define MDCFG_DC_WAY (0x7<<4)
320 #define MDCFG_DC_LSIZE (0x7<<7)
321 #define MDCFG_DC_ECC (0x1<<10)
322 #define MDCFG_DLM_SIZE (0x1F<<16)
323 #define MDCFG_DLM_ECC (0x1<<21)
324 
325 #define MIRGB_INFO_IRG_BASE_ADDR_BOFS (10)
326 #define MIRGB_INFO_IREGION_SIZE_BOFS (1)
327 
328 #define MPPICFG_INFO_PPI_SIZE (0x1F<<1)
329 #define MPPICFG_INFO_PPI_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10)
330 
331 #define MFIOCFG_INFO_FIO_SIZE (0x1F<<1)
332 #define MFIOCFG_INFO_FIO_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10)
333 
334 #define MECC_LOCK_ECC_LOCK (0x1)
335 
336 #define MECC_CODE_CODE (0x1FF)
337 #define MECC_CODE_RAMID (0x1F<<16)
338 #define MECC_CODE_SRAMID (0x1F<<24)
339 
340 #define CCM_SUEN_SUEN (0x1<<0)
341 #define CCM_DATA_DATA (0x7<<0)
342 #define CCM_COMMAND_COMMAND (0x1F<<0)
343 
344 /* IREGION Offsets */
345 #define IREGION_IINFO_OFS (0x0)
346 #define IREGION_DEBUG_OFS (0x10000)
347 #define IREGION_ECLIC_OFS (0x20000)
348 #define IREGION_TIMER_OFS (0x30000)
349 #define IREGION_SMP_OFS (0x40000)
350 #define IREGION_IDU_OFS (0x50000)
351 #define IREGION_PL2_OFS (0x60000)
352 #define IREGION_DPREFETCH_OFS (0x70000)
353 #define IREGION_PLIC_OFS (0x4000000)
354 
355 /* === Stack protect === */
356 #define MSTACK_CTRL_MODE (0x1<<2)
357 #define MSTACK_CTRL_UDF_EN (0x1<<1)
358 #define MSTACK_CTRL_OVF_TRACK_EN (0x1)
359 
360 #define SIP_SSIP MIP_SSIP
361 #define SIP_STIP MIP_STIP
362 
363 #define PRV_U 0
364 #define PRV_S 1
365 #define PRV_H 2
366 #define PRV_M 3
367 
368 #define VM_MBARE 0
369 #define VM_MBB 1
370 #define VM_MBBID 2
371 #define VM_SV32 8
372 #define VM_SV39 9
373 #define VM_SV48 10
374 
375 #define SATP32_MODE 0x80000000
376 #define SATP32_ASID 0x7FC00000
377 #define SATP32_PPN 0x003FFFFF
378 #define SATP64_MODE 0xF000000000000000
379 #define SATP64_ASID 0x0FFFF00000000000
380 #define SATP64_PPN 0x00000FFFFFFFFFFF
381 
382 #define SATP_MODE_OFF 0
383 #define SATP_MODE_SV32 1
384 #define SATP_MODE_SV39 8
385 #define SATP_MODE_SV48 9
386 #define SATP_MODE_SV57 10
387 #define SATP_MODE_SV64 11
388 
389 #define IRQ_S_SOFT 1
390 #define IRQ_H_SOFT 2
391 #define IRQ_M_SOFT 3
392 #define IRQ_S_TIMER 5
393 #define IRQ_H_TIMER 6
394 #define IRQ_M_TIMER 7
395 #define IRQ_S_EXT 9
396 #define IRQ_H_EXT 10
397 #define IRQ_M_EXT 11
398 #define IRQ_COP 12
399 #define IRQ_HOST 13
400 
401 
402 /* === FPU FRM Rounding Mode === */
404 #define FRM_RNDMODE_RNE 0x0
406 #define FRM_RNDMODE_RTZ 0x1
408 #define FRM_RNDMODE_RDN 0x2
410 #define FRM_RNDMODE_RUP 0x3
412 #define FRM_RNDMODE_RMM 0x4
416 #define FRM_RNDMODE_DYN 0x7
417 
418 /* === FPU FFLAGS Accrued Exceptions === */
420 #define FFLAGS_AE_NX (1<<0)
422 #define FFLAGS_AE_UF (1<<1)
424 #define FFLAGS_AE_OF (1<<2)
426 #define FFLAGS_AE_DZ (1<<3)
428 #define FFLAGS_AE_NV (1<<4)
429 
431 #define FREG(idx) f##idx
432 
433 
434 /* === PMP CFG Bits === */
435 #define PMP_R 0x01
436 #define PMP_W 0x02
437 #define PMP_X 0x04
438 #define PMP_A 0x18
439 #define PMP_A_TOR 0x08
440 #define PMP_A_NA4 0x10
441 #define PMP_A_NAPOT 0x18
442 #define PMP_L 0x80
443 
444 #define PMP_SHIFT 2
445 #define PMP_COUNT 16
446 
447 /* === sPMP CFG Bits === */
448 #define SPMP_R PMP_R
449 #define SPMP_W PMP_W
450 #define SPMP_X PMP_X
451 #define SPMP_A PMP_A
452 #define SPMP_A_TOR PMP_A_TOR
453 #define SPMP_A_NA4 PMP_A_NA4
454 #define SPMP_A_NAPOT PMP_A_NAPOT
455 #define SPMP_U 0x40
456 #define SPMP_L PMP_L
457 
458 #define SPMP_SHIFT PMP_SHIFT
459 #define SPMP_COUNT 16
460 
461 /* === SMPU CFG Bits === */
462 #define SMPU_R SPMP_R
463 #define SMPU_W SPMP_W
464 #define SMPU_X SPMP_X
465 #define SMPU_A SPMP_A
466 #define SMPU_A_TOR SPMP_A_TOR
467 #define SMPU_A_NA4 SPMP_A_NA4
468 #define SMPU_A_NAPOT SPMP_A_NAPOT
469 #define SMPU_S 0x80
470 
471 #define SMPU_SHIFT PMP_SHIFT
472 
473 // page table entry (PTE) fields
474 #define PTE_V 0x001 // Valid
475 #define PTE_R 0x002 // Read
476 #define PTE_W 0x004 // Write
477 #define PTE_X 0x008 // Execute
478 #define PTE_U 0x010 // User
479 #define PTE_G 0x020 // Global
480 #define PTE_A 0x040 // Accessed
481 #define PTE_D 0x080 // Dirty
482 #define PTE_SOFT 0x300 // Reserved for Software
483 
484 #define PTE_PPN_SHIFT 10
485 
486 #define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)
487 
488 #ifdef __riscv
489 
490 #ifdef __riscv64
491 # define MSTATUS_SD MSTATUS64_SD
492 # define SSTATUS_SD SSTATUS64_SD
493 # define RISCV_PGLEVEL_BITS 9
494 #else
495 # define MSTATUS_SD MSTATUS32_SD
496 # define SSTATUS_SD SSTATUS32_SD
497 # define RISCV_PGLEVEL_BITS 10
498 #endif /* __riscv64 */
499 
500 #define RISCV_PGSHIFT 12
501 #define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
502 
503 #endif /* __riscv */
504 
514 /* === Standard RISC-V CSR Registers === */
515 #define CSR_USTATUS 0x0
516 #define CSR_FFLAGS 0x1
517 #define CSR_FRM 0x2
518 #define CSR_FCSR 0x3
519 #define CSR_VSTART 0x8
520 #define CSR_VXSAT 0x9
521 #define CSR_VXRM 0xa
522 #define CSR_VCSR 0xf
523 #define CSR_SEED 0x15
524 #define CSR_JVT 0x17
525 #define CSR_CYCLE 0xc00
526 #define CSR_TIME 0xc01
527 #define CSR_INSTRET 0xc02
528 #define CSR_HPMCOUNTER3 0xc03
529 #define CSR_HPMCOUNTER4 0xc04
530 #define CSR_HPMCOUNTER5 0xc05
531 #define CSR_HPMCOUNTER6 0xc06
532 #define CSR_HPMCOUNTER7 0xc07
533 #define CSR_HPMCOUNTER8 0xc08
534 #define CSR_HPMCOUNTER9 0xc09
535 #define CSR_HPMCOUNTER10 0xc0a
536 #define CSR_HPMCOUNTER11 0xc0b
537 #define CSR_HPMCOUNTER12 0xc0c
538 #define CSR_HPMCOUNTER13 0xc0d
539 #define CSR_HPMCOUNTER14 0xc0e
540 #define CSR_HPMCOUNTER15 0xc0f
541 #define CSR_HPMCOUNTER16 0xc10
542 #define CSR_HPMCOUNTER17 0xc11
543 #define CSR_HPMCOUNTER18 0xc12
544 #define CSR_HPMCOUNTER19 0xc13
545 #define CSR_HPMCOUNTER20 0xc14
546 #define CSR_HPMCOUNTER21 0xc15
547 #define CSR_HPMCOUNTER22 0xc16
548 #define CSR_HPMCOUNTER23 0xc17
549 #define CSR_HPMCOUNTER24 0xc18
550 #define CSR_HPMCOUNTER25 0xc19
551 #define CSR_HPMCOUNTER26 0xc1a
552 #define CSR_HPMCOUNTER27 0xc1b
553 #define CSR_HPMCOUNTER28 0xc1c
554 #define CSR_HPMCOUNTER29 0xc1d
555 #define CSR_HPMCOUNTER30 0xc1e
556 #define CSR_HPMCOUNTER31 0xc1f
557 #define CSR_VL 0xc20
558 #define CSR_VTYPE 0xc21
559 #define CSR_VLENB 0xc22
560 #define CSR_TIMEH 0xc81
561 #define CSR_SSTATUS 0x100
562 #define CSR_SEDELEG 0x102
563 #define CSR_SIDELEG 0x103
564 #define CSR_SIE 0x104
565 #define CSR_STVEC 0x105
566 #define CSR_STVT 0x107
567 #define CSR_SCOUNTEREN 0x106
568 #define CSR_SENVCFG 0x10a
569 #define CSR_SSTATEEN0 0x10c
570 #define CSR_SSTATEEN1 0x10d
571 #define CSR_SSTATEEN2 0x10e
572 #define CSR_SSTATEEN3 0x10f
573 #define CSR_SSCRATCH 0x140
574 #define CSR_SEPC 0x141
575 #define CSR_SCAUSE 0x142
576 #define CSR_STVAL 0x143
577 #define CSR_SIP 0x144
578 #define CSR_STIMECMP 0x14d
579 #define CSR_STIMECMPH 0x15d
580 #define CSR_SATP 0x180
581 #define CSR_SCONTEXT 0x5a8
582 #define CSR_VSSTATUS 0x200
583 #define CSR_VSIE 0x204
584 #define CSR_VSTVEC 0x205
585 #define CSR_VSSCRATCH 0x240
586 #define CSR_VSEPC 0x241
587 #define CSR_VSCAUSE 0x242
588 #define CSR_VSTVAL 0x243
589 #define CSR_VSIP 0x244
590 #define CSR_VSTIMECMP 0x24d
591 #define CSR_VSATP 0x280
592 #define CSR_HSTATUS 0x600
593 #define CSR_HEDELEG 0x602
594 #define CSR_HIDELEG 0x603
595 #define CSR_HIE 0x604
596 #define CSR_HTIMEDELTA 0x605
597 #define CSR_HCOUNTEREN 0x606
598 #define CSR_HGEIE 0x607
599 #define CSR_HENVCFG 0x60a
600 #define CSR_HSTATEEN0 0x60c
601 #define CSR_HSTATEEN1 0x60d
602 #define CSR_HSTATEEN2 0x60e
603 #define CSR_HSTATEEN3 0x60f
604 #define CSR_HTVAL 0x643
605 #define CSR_HIP 0x644
606 #define CSR_HVIP 0x645
607 #define CSR_HTINST 0x64a
608 #define CSR_HGATP 0x680
609 #define CSR_HCONTEXT 0x6a8
610 #define CSR_HGEIP 0xe12
611 #define CSR_SCOUNTOVF 0xda0
612 #define CSR_UTVT 0x7
613 #define CSR_UNXTI 0x45
614 #define CSR_UINTSTATUS 0x46
615 #define CSR_USCRATCHCSW 0x48
616 #define CSR_USCRATCHCSWL 0x49
617 #define CSR_STVT 0x107
618 #define CSR_SNXTI 0x145
619 #define CSR_SINTSTATUS 0x146
620 #define CSR_SSCRATCHCSW 0x148
621 #define CSR_SSCRATCHCSWL 0x149
622 #define CSR_MTVT 0x307
623 #define CSR_MNXTI 0x345
624 #define CSR_MINTSTATUS 0x346
625 #define CSR_MSCRATCHCSW 0x348
626 #define CSR_MSCRATCHCSWL 0x349
627 #define CSR_MSTATUS 0x300
628 #define CSR_MISA 0x301
629 #define CSR_MEDELEG 0x302
630 #define CSR_MIDELEG 0x303
631 #define CSR_MIE 0x304
632 #define CSR_MTVEC 0x305
633 #define CSR_MCOUNTEREN 0x306
634 #define CSR_MENVCFG 0x30a
635 #define CSR_MENVCFGH 0x31a
636 #define CSR_MSTATEEN0 0x30c
637 #define CSR_MSTATEEN1 0x30d
638 #define CSR_MSTATEEN2 0x30e
639 #define CSR_MSTATEEN3 0x30f
640 #define CSR_MCOUNTINHIBIT 0x320
641 #define CSR_MSCRATCH 0x340
642 #define CSR_MEPC 0x341
643 #define CSR_MCAUSE 0x342
644 #define CSR_MTVAL 0x343
645 #define CSR_MBADADDR 0x343
646 #define CSR_MIP 0x344
647 #define CSR_MTINST 0x34a
648 #define CSR_MTVAL2 0x34b
649 #define CSR_PMPCFG0 0x3a0
650 #define CSR_PMPCFG1 0x3a1
651 #define CSR_PMPCFG2 0x3a2
652 #define CSR_PMPCFG3 0x3a3
653 #define CSR_PMPCFG4 0x3a4
654 #define CSR_PMPCFG5 0x3a5
655 #define CSR_PMPCFG6 0x3a6
656 #define CSR_PMPCFG7 0x3a7
657 #define CSR_PMPCFG8 0x3a8
658 #define CSR_PMPCFG9 0x3a9
659 #define CSR_PMPCFG10 0x3aa
660 #define CSR_PMPCFG11 0x3ab
661 #define CSR_PMPCFG12 0x3ac
662 #define CSR_PMPCFG13 0x3ad
663 #define CSR_PMPCFG14 0x3ae
664 #define CSR_PMPCFG15 0x3af
665 #define CSR_PMPADDR0 0x3b0
666 #define CSR_PMPADDR1 0x3b1
667 #define CSR_PMPADDR2 0x3b2
668 #define CSR_PMPADDR3 0x3b3
669 #define CSR_PMPADDR4 0x3b4
670 #define CSR_PMPADDR5 0x3b5
671 #define CSR_PMPADDR6 0x3b6
672 #define CSR_PMPADDR7 0x3b7
673 #define CSR_PMPADDR8 0x3b8
674 #define CSR_PMPADDR9 0x3b9
675 #define CSR_PMPADDR10 0x3ba
676 #define CSR_PMPADDR11 0x3bb
677 #define CSR_PMPADDR12 0x3bc
678 #define CSR_PMPADDR13 0x3bd
679 #define CSR_PMPADDR14 0x3be
680 #define CSR_PMPADDR15 0x3bf
681 #define CSR_PMPADDR16 0x3c0
682 #define CSR_PMPADDR17 0x3c1
683 #define CSR_PMPADDR18 0x3c2
684 #define CSR_PMPADDR19 0x3c3
685 #define CSR_PMPADDR20 0x3c4
686 #define CSR_PMPADDR21 0x3c5
687 #define CSR_PMPADDR22 0x3c6
688 #define CSR_PMPADDR23 0x3c7
689 #define CSR_PMPADDR24 0x3c8
690 #define CSR_PMPADDR25 0x3c9
691 #define CSR_PMPADDR26 0x3ca
692 #define CSR_PMPADDR27 0x3cb
693 #define CSR_PMPADDR28 0x3cc
694 #define CSR_PMPADDR29 0x3cd
695 #define CSR_PMPADDR30 0x3ce
696 #define CSR_PMPADDR31 0x3cf
697 #define CSR_PMPADDR32 0x3d0
698 #define CSR_PMPADDR33 0x3d1
699 #define CSR_PMPADDR34 0x3d2
700 #define CSR_PMPADDR35 0x3d3
701 #define CSR_PMPADDR36 0x3d4
702 #define CSR_PMPADDR37 0x3d5
703 #define CSR_PMPADDR38 0x3d6
704 #define CSR_PMPADDR39 0x3d7
705 #define CSR_PMPADDR40 0x3d8
706 #define CSR_PMPADDR41 0x3d9
707 #define CSR_PMPADDR42 0x3da
708 #define CSR_PMPADDR43 0x3db
709 #define CSR_PMPADDR44 0x3dc
710 #define CSR_PMPADDR45 0x3dd
711 #define CSR_PMPADDR46 0x3de
712 #define CSR_PMPADDR47 0x3df
713 #define CSR_PMPADDR48 0x3e0
714 #define CSR_PMPADDR49 0x3e1
715 #define CSR_PMPADDR50 0x3e2
716 #define CSR_PMPADDR51 0x3e3
717 #define CSR_PMPADDR52 0x3e4
718 #define CSR_PMPADDR53 0x3e5
719 #define CSR_PMPADDR54 0x3e6
720 #define CSR_PMPADDR55 0x3e7
721 #define CSR_PMPADDR56 0x3e8
722 #define CSR_PMPADDR57 0x3e9
723 #define CSR_PMPADDR58 0x3ea
724 #define CSR_PMPADDR59 0x3eb
725 #define CSR_PMPADDR60 0x3ec
726 #define CSR_PMPADDR61 0x3ed
727 #define CSR_PMPADDR62 0x3ee
728 #define CSR_PMPADDR63 0x3ef
729 #define CSR_MSECCFG 0x747
730 #define CSR_TSELECT 0x7a0
731 #define CSR_TDATA1 0x7a1
732 #define CSR_TDATA2 0x7a2
733 #define CSR_TDATA3 0x7a3
734 #define CSR_TINFO 0x7a4
735 #define CSR_TCONTROL 0x7a5
736 #define CSR_MCONTEXT 0x7a8
737 #define CSR_MSCONTEXT 0x7aa
738 #define CSR_DCSR 0x7b0
739 #define CSR_DPC 0x7b1
740 #define CSR_DSCRATCH0 0x7b2
741 #define CSR_DSCRATCH1 0x7b3
742 #define CSR_MCYCLE 0xb00
743 #define CSR_MINSTRET 0xb02
744 #define CSR_MHPMCOUNTER3 0xb03
745 #define CSR_MHPMCOUNTER4 0xb04
746 #define CSR_MHPMCOUNTER5 0xb05
747 #define CSR_MHPMCOUNTER6 0xb06
748 #define CSR_MHPMCOUNTER7 0xb07
749 #define CSR_MHPMCOUNTER8 0xb08
750 #define CSR_MHPMCOUNTER9 0xb09
751 #define CSR_MHPMCOUNTER10 0xb0a
752 #define CSR_MHPMCOUNTER11 0xb0b
753 #define CSR_MHPMCOUNTER12 0xb0c
754 #define CSR_MHPMCOUNTER13 0xb0d
755 #define CSR_MHPMCOUNTER14 0xb0e
756 #define CSR_MHPMCOUNTER15 0xb0f
757 #define CSR_MHPMCOUNTER16 0xb10
758 #define CSR_MHPMCOUNTER17 0xb11
759 #define CSR_MHPMCOUNTER18 0xb12
760 #define CSR_MHPMCOUNTER19 0xb13
761 #define CSR_MHPMCOUNTER20 0xb14
762 #define CSR_MHPMCOUNTER21 0xb15
763 #define CSR_MHPMCOUNTER22 0xb16
764 #define CSR_MHPMCOUNTER23 0xb17
765 #define CSR_MHPMCOUNTER24 0xb18
766 #define CSR_MHPMCOUNTER25 0xb19
767 #define CSR_MHPMCOUNTER26 0xb1a
768 #define CSR_MHPMCOUNTER27 0xb1b
769 #define CSR_MHPMCOUNTER28 0xb1c
770 #define CSR_MHPMCOUNTER29 0xb1d
771 #define CSR_MHPMCOUNTER30 0xb1e
772 #define CSR_MHPMCOUNTER31 0xb1f
773 #define CSR_MHPMEVENT3 0x323
774 #define CSR_MHPMEVENT4 0x324
775 #define CSR_MHPMEVENT5 0x325
776 #define CSR_MHPMEVENT6 0x326
777 #define CSR_MHPMEVENT7 0x327
778 #define CSR_MHPMEVENT8 0x328
779 #define CSR_MHPMEVENT9 0x329
780 #define CSR_MHPMEVENT10 0x32a
781 #define CSR_MHPMEVENT11 0x32b
782 #define CSR_MHPMEVENT12 0x32c
783 #define CSR_MHPMEVENT13 0x32d
784 #define CSR_MHPMEVENT14 0x32e
785 #define CSR_MHPMEVENT15 0x32f
786 #define CSR_MHPMEVENT16 0x330
787 #define CSR_MHPMEVENT17 0x331
788 #define CSR_MHPMEVENT18 0x332
789 #define CSR_MHPMEVENT19 0x333
790 #define CSR_MHPMEVENT20 0x334
791 #define CSR_MHPMEVENT21 0x335
792 #define CSR_MHPMEVENT22 0x336
793 #define CSR_MHPMEVENT23 0x337
794 #define CSR_MHPMEVENT24 0x338
795 #define CSR_MHPMEVENT25 0x339
796 #define CSR_MHPMEVENT26 0x33a
797 #define CSR_MHPMEVENT27 0x33b
798 #define CSR_MHPMEVENT28 0x33c
799 #define CSR_MHPMEVENT29 0x33d
800 #define CSR_MHPMEVENT30 0x33e
801 #define CSR_MHPMEVENT31 0x33f
802 #define CSR_MVENDORID 0xf11
803 #define CSR_MARCHID 0xf12
804 #define CSR_MIMPID 0xf13
805 #define CSR_MHARTID 0xf14
806 #define CSR_MCONFIGPTR 0xf15
807 #define CSR_STIMECMPH 0x15d
808 #define CSR_VSTIMECMPH 0x25d
809 #define CSR_HTIMEDELTAH 0x615
810 #define CSR_HENVCFGH 0x61a
811 #define CSR_HSTATEEN0H 0x61c
812 #define CSR_HSTATEEN1H 0x61d
813 #define CSR_HSTATEEN2H 0x61e
814 #define CSR_HSTATEEN3H 0x61f
815 #define CSR_CYCLEH 0xc80
816 #define CSR_TIMEH 0xc81
817 #define CSR_INSTRETH 0xc82
818 #define CSR_HPMCOUNTER3H 0xc83
819 #define CSR_HPMCOUNTER4H 0xc84
820 #define CSR_HPMCOUNTER5H 0xc85
821 #define CSR_HPMCOUNTER6H 0xc86
822 #define CSR_HPMCOUNTER7H 0xc87
823 #define CSR_HPMCOUNTER8H 0xc88
824 #define CSR_HPMCOUNTER9H 0xc89
825 #define CSR_HPMCOUNTER10H 0xc8a
826 #define CSR_HPMCOUNTER11H 0xc8b
827 #define CSR_HPMCOUNTER12H 0xc8c
828 #define CSR_HPMCOUNTER13H 0xc8d
829 #define CSR_HPMCOUNTER14H 0xc8e
830 #define CSR_HPMCOUNTER15H 0xc8f
831 #define CSR_HPMCOUNTER16H 0xc90
832 #define CSR_HPMCOUNTER17H 0xc91
833 #define CSR_HPMCOUNTER18H 0xc92
834 #define CSR_HPMCOUNTER19H 0xc93
835 #define CSR_HPMCOUNTER20H 0xc94
836 #define CSR_HPMCOUNTER21H 0xc95
837 #define CSR_HPMCOUNTER22H 0xc96
838 #define CSR_HPMCOUNTER23H 0xc97
839 #define CSR_HPMCOUNTER24H 0xc98
840 #define CSR_HPMCOUNTER25H 0xc99
841 #define CSR_HPMCOUNTER26H 0xc9a
842 #define CSR_HPMCOUNTER27H 0xc9b
843 #define CSR_HPMCOUNTER28H 0xc9c
844 #define CSR_HPMCOUNTER29H 0xc9d
845 #define CSR_HPMCOUNTER30H 0xc9e
846 #define CSR_HPMCOUNTER31H 0xc9f
847 #define CSR_MSTATUSH 0x310
848 #define CSR_MENVCFGH 0x31a
849 #define CSR_MSTATEEN0H 0x31c
850 #define CSR_MSTATEEN1H 0x31d
851 #define CSR_MSTATEEN2H 0x31e
852 #define CSR_MSTATEEN3H 0x31f
853 #define CSR_MHPMEVENT3H 0x723
854 #define CSR_MHPMEVENT4H 0x724
855 #define CSR_MHPMEVENT5H 0x725
856 #define CSR_MHPMEVENT6H 0x726
857 #define CSR_MHPMEVENT7H 0x727
858 #define CSR_MHPMEVENT8H 0x728
859 #define CSR_MHPMEVENT9H 0x729
860 #define CSR_MHPMEVENT10H 0x72a
861 #define CSR_MHPMEVENT11H 0x72b
862 #define CSR_MHPMEVENT12H 0x72c
863 #define CSR_MHPMEVENT13H 0x72d
864 #define CSR_MHPMEVENT14H 0x72e
865 #define CSR_MHPMEVENT15H 0x72f
866 #define CSR_MHPMEVENT16H 0x730
867 #define CSR_MHPMEVENT17H 0x731
868 #define CSR_MHPMEVENT18H 0x732
869 #define CSR_MHPMEVENT19H 0x733
870 #define CSR_MHPMEVENT20H 0x734
871 #define CSR_MHPMEVENT21H 0x735
872 #define CSR_MHPMEVENT22H 0x736
873 #define CSR_MHPMEVENT23H 0x737
874 #define CSR_MHPMEVENT24H 0x738
875 #define CSR_MHPMEVENT25H 0x739
876 #define CSR_MHPMEVENT26H 0x73a
877 #define CSR_MHPMEVENT27H 0x73b
878 #define CSR_MHPMEVENT28H 0x73c
879 #define CSR_MHPMEVENT29H 0x73d
880 #define CSR_MHPMEVENT30H 0x73e
881 #define CSR_MHPMEVENT31H 0x73f
882 #define CSR_MSECCFGH 0x757
883 #define CSR_MCYCLEH 0xb80
884 #define CSR_MINSTRETH 0xb82
885 #define CSR_MHPMCOUNTER3H 0xb83
886 #define CSR_MHPMCOUNTER4H 0xb84
887 #define CSR_MHPMCOUNTER5H 0xb85
888 #define CSR_MHPMCOUNTER6H 0xb86
889 #define CSR_MHPMCOUNTER7H 0xb87
890 #define CSR_MHPMCOUNTER8H 0xb88
891 #define CSR_MHPMCOUNTER9H 0xb89
892 #define CSR_MHPMCOUNTER10H 0xb8a
893 #define CSR_MHPMCOUNTER11H 0xb8b
894 #define CSR_MHPMCOUNTER12H 0xb8c
895 #define CSR_MHPMCOUNTER13H 0xb8d
896 #define CSR_MHPMCOUNTER14H 0xb8e
897 #define CSR_MHPMCOUNTER15H 0xb8f
898 #define CSR_MHPMCOUNTER16H 0xb90
899 #define CSR_MHPMCOUNTER17H 0xb91
900 #define CSR_MHPMCOUNTER18H 0xb92
901 #define CSR_MHPMCOUNTER19H 0xb93
902 #define CSR_MHPMCOUNTER20H 0xb94
903 #define CSR_MHPMCOUNTER21H 0xb95
904 #define CSR_MHPMCOUNTER22H 0xb96
905 #define CSR_MHPMCOUNTER23H 0xb97
906 #define CSR_MHPMCOUNTER24H 0xb98
907 #define CSR_MHPMCOUNTER25H 0xb99
908 #define CSR_MHPMCOUNTER26H 0xb9a
909 #define CSR_MHPMCOUNTER27H 0xb9b
910 #define CSR_MHPMCOUNTER28H 0xb9c
911 #define CSR_MHPMCOUNTER29H 0xb9d
912 #define CSR_MHPMCOUNTER30H 0xb9e
913 #define CSR_MHPMCOUNTER31H 0xb9f
914 
915 /* === TEE CSR Registers === */
916 #define CSR_SPMPCFG0 0x1A0
917 #define CSR_SPMPCFG1 0x1A1
918 #define CSR_SPMPCFG2 0x1A2
919 #define CSR_SPMPCFG3 0x1A3
920 #define CSR_SPMPADDR0 0x1B0
921 #define CSR_SPMPADDR1 0x1B1
922 #define CSR_SPMPADDR2 0x1B2
923 #define CSR_SPMPADDR3 0x1B3
924 #define CSR_SPMPADDR4 0x1B4
925 #define CSR_SPMPADDR5 0x1B5
926 #define CSR_SPMPADDR6 0x1B6
927 #define CSR_SPMPADDR7 0x1B7
928 #define CSR_SPMPADDR8 0x1B8
929 #define CSR_SPMPADDR9 0x1B9
930 #define CSR_SPMPADDR10 0x1BA
931 #define CSR_SPMPADDR11 0x1BB
932 #define CSR_SPMPADDR12 0x1BC
933 #define CSR_SPMPADDR13 0x1BD
934 #define CSR_SPMPADDR14 0x1BE
935 #define CSR_SPMPADDR15 0x1BF
936 
937 #define CSR_SMPUCFG0 0x1A0
938 #define CSR_SMPUCFG1 0x1A1
939 #define CSR_SMPUCFG2 0x1A2
940 #define CSR_SMPUCFG3 0x1A3
941 #define CSR_SMPUADDR0 0x1B0
942 #define CSR_SMPUADDR1 0x1B1
943 #define CSR_SMPUADDR2 0x1B2
944 #define CSR_SMPUADDR3 0x1B3
945 #define CSR_SMPUADDR4 0x1B4
946 #define CSR_SMPUADDR5 0x1B5
947 #define CSR_SMPUADDR6 0x1B6
948 #define CSR_SMPUADDR7 0x1B7
949 #define CSR_SMPUADDR8 0x1B8
950 #define CSR_SMPUADDR9 0x1B9
951 #define CSR_SMPUADDR10 0x1BA
952 #define CSR_SMPUADDR11 0x1BB
953 #define CSR_SMPUADDR12 0x1BC
954 #define CSR_SMPUADDR13 0x1BD
955 #define CSR_SMPUADDR14 0x1BE
956 #define CSR_SMPUADDR15 0x1BF
957 
958 #define CSR_SMPUSWITCH0 0x170
959 #define CSR_SMPUSWITCH1 0x171
960 
961 /* === CLIC CSR Registers === */
962 #define CSR_MTVT 0x307
963 #define CSR_MNXTI 0x345
964 #define CSR_MINTSTATUS 0x346
965 #define CSR_MSCRATCHCSW 0x348
966 #define CSR_MSCRATCHCSWL 0x349
967 #define CSR_MCLICBASE 0x350
968 
969 /* === P-Extension Registers === */
970 #define CSR_UCODE 0x801
971 
972 /* === Nuclei custom CSR Registers === */
973 //#define CSR_MCOUNTINHIBIT 0x320
974 #define CSR_MILM_CTL 0x7C0
975 #define CSR_MDLM_CTL 0x7C1
976 #define CSR_MECC_CODE 0x7C2
977 #define CSR_MNVEC 0x7C3
978 #define CSR_MSUBM 0x7C4
979 #define CSR_MDCAUSE 0x7C9
980 #define CSR_MCACHE_CTL 0x7CA
981 #define CSR_MMISC_CTL 0x7D0
982 #define CSR_MSAVESTATUS 0x7D6
983 #define CSR_MSAVEEPC1 0x7D7
984 #define CSR_MSAVECAUSE1 0x7D8
985 #define CSR_MSAVEEPC2 0x7D9
986 #define CSR_MSAVECAUSE2 0x7DA
987 #define CSR_MSAVEDCAUSE1 0x7DB
988 #define CSR_MSAVEDCAUSE2 0x7DC
989 #define CSR_MTLB_CTL 0x7DD
990 #define CSR_MECC_LOCK 0x7DE
991 #define CSR_MFP16MODE 0x7E2
992 /* mfp16mode is renamed to mmisc_ctl1 */
993 #define CSR_MMISC_CTL1 0x7E2
994 #define CSR_LSTEPFORC 0x7E9
995 #define CSR_PUSHMSUBM 0x7EB
996 #define CSR_MTVT2 0x7EC
997 #define CSR_JALMNXTI 0x7ED
998 #define CSR_PUSHMCAUSE 0x7EE
999 #define CSR_PUSHMEPC 0x7EF
1000 #define CSR_MPPICFG_INFO 0x7F0
1001 #define CSR_MFIOCFG_INFO 0x7F1
1002 
1003 /* === NCDEV === */
1004 #define CSR_MDEVB 0x7F3
1005 #define CSR_MDEVM 0x7F4
1006 #define CSR_MNOCB 0x7F5
1007 #define CSR_MNOCM 0x7F6
1008 #define CSR_MMACRO_DEV_EN 0xBC8
1009 #define CSR_MMACRO_NOC_EN 0xBC9
1010 #define CSR_MMACRO_CA_EN 0xBCA
1011 #define CSR_MATTRI0_BASE 0x7F3
1012 #define CSR_MATTRI0_MASK 0x7F4
1013 #define CSR_MATTRI1_BASE 0x7F5
1014 #define CSR_MATTRI1_MASK 0x7F6
1015 #define CSR_MATTRI2_BASE 0x7F9
1016 #define CSR_MATTRI2_MASK 0x7FA
1017 #define CSR_MATTRI3_BASE 0x7FB
1018 #define CSR_MATTRI3_MASK 0x7FC
1019 #define CSR_MATTRI4_BASE 0x7FD
1020 #define CSR_MATTRI4_MASK 0x7FE
1021 #define CSR_MATTRI5_BASE 0xBE0
1022 #define CSR_MATTRI5_MASK 0xBE1
1023 #define CSR_MATTRI6_BASE 0xBE2
1024 #define CSR_MATTRI6_MASK 0xBE3
1025 #define CSR_MATTRI7_BASE 0xBE4
1026 #define CSR_MATTRI7_MASK 0xBE5
1027 #define CSR_SATTRI0_BASE 0x5F0
1028 #define CSR_SATTRI0_MASK 0x5F1
1029 #define CSR_SATTRI1_BASE 0x5F2
1030 #define CSR_SATTRI1_MASK 0x5F3
1031 #define CSR_SATTRI2_BASE 0x5F4
1032 #define CSR_SATTRI2_MASK 0x5F5
1033 #define CSR_SATTRI3_BASE 0x5F6
1034 #define CSR_SATTRI3_MASK 0x5F7
1035 #define CSR_SATTRI4_BASE 0x5F8
1036 #define CSR_SATTRI4_MASK 0x5F9
1037 #define CSR_SATTRI5_BASE 0x5FA
1038 #define CSR_SATTRI5_MASK 0x5FB
1039 #define CSR_SATTRI6_BASE 0x5FC
1040 #define CSR_SATTRI6_MASK 0x5FD
1041 #define CSR_SATTRI7_BASE 0x5FE
1042 #define CSR_SATTRI7_MASK 0x5FF
1043 
1044 /* === IREGION === */
1045 #define CSR_MSMPCFG_INFO 0x7F7
1046 #define CSR_MIRGB_INFO 0x7F7
1047 
1048 #define CSR_SLEEPVALUE 0x811
1049 #define CSR_TXEVT 0x812
1050 #define CSR_WFE 0x810
1051 #define CSR_JALSNXTI 0x947
1052 #define CSR_STVT2 0x948
1053 #define CSR_PUSHSCAUSE 0x949
1054 #define CSR_PUSHSEPC 0x94A
1055 #define CSR_SDCAUSE 0x9C0
1056 #define CSR_MICFG_INFO 0xFC0
1057 #define CSR_MDCFG_INFO 0xFC1
1058 #define CSR_MCFG_INFO 0xFC2
1059 #define CSR_MTLBCFG_INFO 0xFC3
1060 
1061 /* === ECC === */
1062 #define CSR_MECC_CTL 0xBC0
1063 #define CSR_MECC_STATUS 0xBC4
1064 
1065 /* === STL === */
1066 #define CSR_SAFETY_CRC_CTL 0x813
1067 #define CSR_SAFETY_STL_STATUS 0x814
1068 
1069 /* === Stack protect === */
1070 #define CSR_MSTACK_CTRL 0x7C6
1071 #define CSR_MSTACK_CTL 0x7C6
1072 #define CSR_MSTACK_BOUND 0x7C7
1073 #define CSR_MSTACK_BASE 0x7C8
1074 
1075 /* === Nuclei CCM Registers === */
1076 #define CSR_CCM_MBEGINADDR 0x7CB
1077 #define CSR_CCM_MCOMMAND 0x7CC
1078 #define CSR_CCM_MDATA 0x7CD
1079 #define CSR_CCM_SUEN 0x7CE
1080 #define CSR_CCM_SBEGINADDR 0x5CB
1081 #define CSR_CCM_SCOMMAND 0x5CC
1082 #define CSR_CCM_SDATA 0x5CD
1083 #define CSR_CCM_UBEGINADDR 0x4CB
1084 #define CSR_CCM_UCOMMAND 0x4CC
1085 #define CSR_CCM_UDATA 0x4CD
1086 #define CSR_CCM_FPIPE 0x4CF
1087 
1088 #define CSR_SHARTID 0xDC0
1089 /* === Worldguard CSRs === */
1090 #define CSR_MLWID 0x390
1091 #define CSR_MWIDDELEG 0x738
1092 #define CSR_SLWID 0x190
1093 
1096 /* Exception Code in MCAUSE CSR */
1097 #define CAUSE_MISALIGNED_FETCH 0x0
1098 #define CAUSE_FAULT_FETCH 0x1
1099 #define CAUSE_ILLEGAL_INSTRUCTION 0x2
1100 #define CAUSE_BREAKPOINT 0x3
1101 #define CAUSE_MISALIGNED_LOAD 0x4
1102 #define CAUSE_FAULT_LOAD 0x5
1103 #define CAUSE_MISALIGNED_STORE 0x6
1104 #define CAUSE_FAULT_STORE 0x7
1105 #define CAUSE_USER_ECALL 0x8
1106 #define CAUSE_SUPERVISOR_ECALL 0x9
1107 #define CAUSE_HYPERVISOR_ECALL 0xa
1108 #define CAUSE_MACHINE_ECALL 0xb
1109 #define CAUSE_FETCH_PAGE_FAULT 0xc
1110 #define CAUSE_LOAD_PAGE_FAULT 0xd
1111 #define CAUSE_STORE_PAGE_FAULT 0xf
1112 
1113 /* Delegatable Exception Code Mask in MCAUSE CSR*/
1114 #define MISALIGNED_FETCH (1 << CAUSE_MISALIGNED_FETCH)
1115 #define FAULT_FETCH (1 << CAUSE_FAULT_FETCH)
1116 #define ILLEGAL_INSTRUCTION (1 << CAUSE_ILLEGAL_INSTRUCTION)
1117 #define BREAKPOINT (1 << CAUSE_BREAKPOINT)
1118 #define MISALIGNED_LOAD (1 << CAUSE_MISALIGNED_LOAD)
1119 #define FAULT_LOAD (1 << CAUSE_FAULT_LOAD)
1120 #define MISALIGNED_STORE (1 << CAUSE_MISALIGNED_STORE)
1121 #define FAULT_STORE (1 << CAUSE_FAULT_STORE)
1122 #define USER_ECALL (1 << CAUSE_USER_ECALL)
1123 #define FETCH_PAGE_FAULT (1 << CAUSE_FETCH_PAGE_FAULT)
1124 #define LOAD_PAGE_FAULT (1 << CAUSE_LOAD_PAGE_FAULT)
1125 #define STORE_PAGE_FAULT (1 << CAUSE_STORE_PAGE_FAULT)
1126 
1127 /* Exception Subcode in MDCAUSE CSR */
1128 #define DCAUSE_FAULT_FETCH_PMP 0x1
1129 #define DCAUSE_FAULT_FETCH_INST 0x2
1130 
1131 #define DCAUSE_FAULT_LOAD_PMP 0x1
1132 #define DCAUSE_FAULT_LOAD_INST 0x2
1133 #define DCAUSE_FAULT_LOAD_NICE 0x3
1134 
1135 #define DCAUSE_FAULT_STORE_PMP 0x1
1136 #define DCAUSE_FAULT_STORE_INST 0x2
1137 
1138 #ifdef SMODE_RTOS
1139 #define CSR_XSTATUS CSR_SSTATUS
1140 #define CSR_XTVEC CSR_STVEC
1141 #define CSR_XCOUNTEREN CSR_SCOUNTEREN
1142 #define CSR_XIE CSR_SIE
1143 #define CSR_XIP CSR_SIP
1144 #define CSR_XSCRATCH CSR_SSCRATCH
1145 #define CSR_XEPC CSR_SEPC
1146 #define CSR_XCAUSE CSR_SCAUSE
1147 #define CSR_XTVAL CSR_STVAL
1148 #define CSR_XENVCFG CSR_SENVCFG
1149 #define CSR_XTVT CSR_STVT
1150 #define CSR_XTVT2 CSR_STVT2
1151 #define CSR_XSCRATCHCSWL CSR_SSCRATCHCSWL
1152 #define CSR_XSCRATCHCSW CSR_SSCRATCHCSW
1153 #define CSR_XDCAUSE CSR_SDCAUSE
1154 #define CSR_JALXNXTI CSR_JALSNXTI
1155 #define CSR_XINTSTATUS CSR_SINTSTATUS
1156 #define CSR_XNXTI CSR_SNXTI
1157 #define CSR_PUSHXEPC CSR_PUSHSEPC
1158 #define CSR_PUSHXCAUSE CSR_PUSHSCAUSE
1159 #define XRET sret
1160 #define eclic_xsip_handler eclic_ssip_handler
1161 #define eclic_xtip_handler eclic_stip_handler
1162 #define XSTATUS_XIE SSTATUS_SIE
1163 #define x_exc_entry exc_entry_s
1164 #define x_irq_entry irq_entry_s
1165 #else
1166 #define CSR_XSTATUS CSR_MSTATUS
1167 #define CSR_XTVEC CSR_MTVEC
1168 #define CSR_XCOUNTEREN CSR_MCOUNTEREN
1169 #define CSR_XIE CSR_MIE
1170 #define CSR_XIP CSR_MIP
1171 #define CSR_XSCRATCH CSR_MSCRATCH
1172 #define CSR_XEPC CSR_MEPC
1173 #define CSR_XCAUSE CSR_MCAUSE
1174 #define CSR_XSUBM CSR_MSUBM
1175 #define CSR_XTVAL CSR_MTVAL
1176 #define CSR_XENVCFG CSR_MENVCFG
1177 #define CSR_XTVT CSR_MTVT
1178 #define CSR_XTVT2 CSR_MTVT2
1179 #define CSR_XSCRATCHCSWL CSR_MSCRATCHCSWL
1180 #define CSR_XSCRATCHCSW CSR_MSCRATCHCSW
1181 #define CSR_XDCAUSE CSR_MDCAUSE
1182 #define CSR_JALXNXTI CSR_JALMNXTI
1183 #define CSR_XINTSTATUS CSR_MINTSTATUS
1184 #define CSR_XNXTI CSR_MNXTI
1185 #define CSR_PUSHXEPC CSR_PUSHMEPC
1186 #define CSR_PUSHXCAUSE CSR_PUSHMCAUSE
1187 #define XRET mret
1188 #define eclic_xsip_handler eclic_msip_handler
1189 #define eclic_xtip_handler eclic_mtip_handler
1190 #define XSTATUS_XIE MSTATUS_MIE
1191 #define x_exc_entry exc_entry
1192 #define x_irq_entry irq_entry
1193 #endif
1194 
1197 #ifdef __cplusplus
1198 }
1199 #endif
1200 #endif /* __RISCV_ENCODING_H__ */