NMSIS-Core  Version 1.2.0
NMSIS-Core support for Nuclei processor-based devices
Intrinsic Functions for CPU Intructions

Functions that generate RISC-V CPU instructions. More...

Macros

#define __FENCE(p, s)   __ASM volatile ("fence " #p "," #s : : : "memory")
 Execute fence instruction, p -> pred, s -> succ. More...
 
#define __RWMB()   __FENCE(iorw,iorw)
 Read & Write Memory barrier. More...
 
#define __RMB()   __FENCE(ir,ir)
 Read Memory barrier. More...
 
#define __WMB()   __FENCE(ow,ow)
 Write Memory barrier. More...
 
#define __SMP_RWMB()   __FENCE(rw,rw)
 SMP Read & Write Memory barrier. More...
 
#define __SMP_RMB()   __FENCE(r,r)
 SMP Read Memory barrier. More...
 
#define __SMP_WMB()   __FENCE(w,w)
 SMP Write Memory barrier. More...
 
#define __CPU_RELAX()   __ASM volatile ("" : : : "memory")
 CPU relax for busy loop. More...
 

Enumerations

enum  WFI_SleepMode {
  WFI_SHALLOW_SLEEP = 0,
  WFI_DEEP_SLEEP = 1
}
 WFI Sleep Mode enumeration. More...
 

Functions

__STATIC_FORCEINLINE void __NOP (void)
 NOP Instruction. More...
 
__STATIC_FORCEINLINE void __WFI (void)
 Wait For Interrupt. More...
 
__STATIC_FORCEINLINE void __WFE (void)
 Wait For Event. More...
 
__STATIC_FORCEINLINE void __EBREAK (void)
 Breakpoint Instruction. More...
 
__STATIC_FORCEINLINE void __ECALL (void)
 Environment Call Instruction. More...
 
__STATIC_FORCEINLINE void __set_wfi_sleepmode (WFI_SleepMode_Type mode)
 Set Sleep mode of WFI. More...
 
__STATIC_FORCEINLINE void __TXEVT (void)
 Send TX Event. More...
 
__STATIC_FORCEINLINE void __enable_mcycle_counter (void)
 Enable MCYCLE counter. More...
 
__STATIC_FORCEINLINE void __disable_mcycle_counter (void)
 Disable MCYCLE counter. More...
 
__STATIC_FORCEINLINE void __enable_minstret_counter (void)
 Enable MINSTRET counter. More...
 
__STATIC_FORCEINLINE void __disable_minstret_counter (void)
 Disable MINSTRET counter. More...
 
__STATIC_FORCEINLINE void __enable_mhpm_counter (unsigned long idx)
 Enable selected hardware performance monitor counter. More...
 
__STATIC_FORCEINLINE void __disable_mhpm_counter (unsigned long idx)
 Disable selected hardware performance monitor counter. More...
 
__STATIC_FORCEINLINE void __enable_mhpm_counters (unsigned long mask)
 Enable hardware performance counters with mask. More...
 
__STATIC_FORCEINLINE void __disable_mhpm_counters (unsigned long mask)
 Disable hardware performance counters with mask. More...
 
__STATIC_FORCEINLINE void __enable_all_counter (void)
 Enable all MCYCLE & MINSTRET & MHPMCOUNTER counter. More...
 
__STATIC_FORCEINLINE void __disable_all_counter (void)
 Disable all MCYCLE & MINSTRET & MHPMCOUNTER counter. More...
 
__STATIC_FORCEINLINE void __set_hpm_event (unsigned long idx, unsigned long event)
 Set event for selected high performance monitor event. More...
 
__STATIC_FORCEINLINE unsigned long __get_hpm_event (unsigned long idx)
 Get event for selected high performance monitor event. More...
 
__STATIC_FORCEINLINE void __set_hpm_counter (unsigned long idx, uint64_t value)
 Set value for selected high performance monitor counter. More...
 
__STATIC_FORCEINLINE unsigned long __get_hpm_counter (unsigned long idx)
 Get value of selected high performance monitor couner. More...
 
__STATIC_FORCEINLINE void __set_medeleg (unsigned long mask)
 Set exceptions delegation to S mode. More...
 
__STATIC_FORCEINLINE void __FENCE_I (void)
 Fence.i Instruction. More...
 
__STATIC_FORCEINLINE uint8_t __LB (volatile void *addr)
 Load 8bit value from address (8 bit) More...
 
__STATIC_FORCEINLINE uint16_t __LH (volatile void *addr)
 Load 16bit value from address (16 bit) More...
 
__STATIC_FORCEINLINE uint32_t __LW (volatile void *addr)
 Load 32bit value from address (32 bit) More...
 
__STATIC_FORCEINLINE void __SB (volatile void *addr, uint8_t val)
 Write 8bit value to address (8 bit) More...
 
__STATIC_FORCEINLINE void __SH (volatile void *addr, uint16_t val)
 Write 16bit value to address (16 bit) More...
 
__STATIC_FORCEINLINE void __SW (volatile void *addr, uint32_t val)
 Write 32bit value to address (32 bit) More...
 
__STATIC_FORCEINLINE uint32_t __CAS_W (volatile uint32_t *addr, uint32_t oldval, uint32_t newval)
 Compare and Swap 32bit value using LR and SC. More...
 
__STATIC_FORCEINLINE uint32_t __AMOSWAP_W (volatile uint32_t *addr, uint32_t newval)
 Atomic Swap 32bit value into memory. More...
 
__STATIC_FORCEINLINE int32_t __AMOADD_W (volatile int32_t *addr, int32_t value)
 Atomic Add with 32bit value. More...
 
__STATIC_FORCEINLINE int32_t __AMOAND_W (volatile int32_t *addr, int32_t value)
 Atomic And with 32bit value. More...
 
__STATIC_FORCEINLINE int32_t __AMOOR_W (volatile int32_t *addr, int32_t value)
 Atomic OR with 32bit value. More...
 
__STATIC_FORCEINLINE int32_t __AMOXOR_W (volatile int32_t *addr, int32_t value)
 Atomic XOR with 32bit value. More...
 
__STATIC_FORCEINLINE uint32_t __AMOMAXU_W (volatile uint32_t *addr, uint32_t value)
 Atomic unsigned MAX with 32bit value. More...
 
__STATIC_FORCEINLINE int32_t __AMOMAX_W (volatile int32_t *addr, int32_t value)
 Atomic signed MAX with 32bit value. More...
 
__STATIC_FORCEINLINE uint32_t __AMOMINU_W (volatile uint32_t *addr, uint32_t value)
 Atomic unsigned MIN with 32bit value. More...
 
__STATIC_FORCEINLINE int32_t __AMOMIN_W (volatile int32_t *addr, int32_t value)
 Atomic signed MIN with 32bit value. More...
 

Detailed Description

Functions that generate RISC-V CPU instructions.

The following functions generate specified RISC-V instructions that cannot be directly accessed by compiler.

Macro Definition Documentation

◆ __CPU_RELAX

#define __CPU_RELAX ( )    __ASM volatile ("" : : : "memory")

CPU relax for busy loop.

Definition at line 1499 of file core_feature_base.h.

◆ __FENCE

#define __FENCE (   p,
 
)    __ASM volatile ("fence " #p "," #s : : : "memory")

Execute fence instruction, p -> pred, s -> succ.

the FENCE instruction ensures that all memory accesses from instructions preceding the fence in program order (the predecessor set) appear earlier in the global memory order than memory accesses from instructions appearing after the fence in program order (the successor set). For details, please refer to The RISC-V Instruction Set Manual

Parameters
ppredecessor set, such as iorw, rw, r, w
ssuccessor set, such as iorw, rw, r, w

Definition at line 1467 of file core_feature_base.h.

◆ __RMB

#define __RMB ( )    __FENCE(ir,ir)

Read Memory barrier.

Definition at line 1484 of file core_feature_base.h.

◆ __RWMB

#define __RWMB ( )    __FENCE(iorw,iorw)

Read & Write Memory barrier.

Definition at line 1481 of file core_feature_base.h.

◆ __SMP_RMB

#define __SMP_RMB ( )    __FENCE(r,r)

SMP Read Memory barrier.

Definition at line 1493 of file core_feature_base.h.

◆ __SMP_RWMB

#define __SMP_RWMB ( )    __FENCE(rw,rw)

SMP Read & Write Memory barrier.

Definition at line 1490 of file core_feature_base.h.

◆ __SMP_WMB

#define __SMP_WMB ( )    __FENCE(w,w)

SMP Write Memory barrier.

Definition at line 1496 of file core_feature_base.h.

◆ __WMB

#define __WMB ( )    __FENCE(ow,ow)

Write Memory barrier.

Definition at line 1487 of file core_feature_base.h.

Enumeration Type Documentation

◆ WFI_SleepMode

WFI Sleep Mode enumeration.

Enumerator
WFI_SHALLOW_SLEEP 

Shallow sleep mode, the core_clk will poweroff.

WFI_DEEP_SLEEP 

Deep sleep mode, the core_clk and core_ano_clk will poweroff.

Definition at line 882 of file core_feature_base.h.

882  {
883  WFI_SHALLOW_SLEEP = 0,
884  WFI_DEEP_SLEEP = 1
885 } WFI_SleepMode_Type;

Function Documentation

◆ __AMOADD_W()

__STATIC_FORCEINLINE int32_t __AMOADD_W ( volatile int32_t *  addr,
int32_t  value 
)

Atomic Add with 32bit value.

Atomically ADD 32bit value with value in memory using amoadd.d.

Parameters
[in]addrAddress pointer to data, address need to be 4byte aligned
[in]valuevalue to be ADDed
Returns
return memory value + add value

Definition at line 1658 of file core_feature_base.h.

1659 {
1660  int32_t result;
1661 
1662  __ASM volatile ("amoadd.w %0, %2, %1" : \
1663  "=r"(result), "+A"(*addr) : "r"(value) : "memory");
1664  return *addr;
1665 }

References __ASM.

◆ __AMOAND_W()

__STATIC_FORCEINLINE int32_t __AMOAND_W ( volatile int32_t *  addr,
int32_t  value 
)

Atomic And with 32bit value.

Atomically AND 32bit value with value in memory using amoand.d.

Parameters
[in]addrAddress pointer to data, address need to be 4byte aligned
[in]valuevalue to be ANDed
Returns
return memory value & and value

Definition at line 1674 of file core_feature_base.h.

1675 {
1676  int32_t result;
1677 
1678  __ASM volatile ("amoand.w %0, %2, %1" : \
1679  "=r"(result), "+A"(*addr) : "r"(value) : "memory");
1680  return *addr;
1681 }

References __ASM.

◆ __AMOMAX_W()

__STATIC_FORCEINLINE int32_t __AMOMAX_W ( volatile int32_t *  addr,
int32_t  value 
)

Atomic signed MAX with 32bit value.

Atomically signed max compare 32bit value with value in memory using amomax.d.

Parameters
[in]addrAddress pointer to data, address need to be 4byte aligned
[in]valuevalue to be compared
Returns
the bigger value

Definition at line 1738 of file core_feature_base.h.

1739 {
1740  int32_t result;
1741 
1742  __ASM volatile ("amomax.w %0, %2, %1" : \
1743  "=r"(result), "+A"(*addr) : "r"(value) : "memory");
1744  return *addr;
1745 }

References __ASM.

◆ __AMOMAXU_W()

__STATIC_FORCEINLINE uint32_t __AMOMAXU_W ( volatile uint32_t *  addr,
uint32_t  value 
)

Atomic unsigned MAX with 32bit value.

Atomically unsigned max compare 32bit value with value in memory using amomaxu.d.

Parameters
[in]addrAddress pointer to data, address need to be 4byte aligned
[in]valuevalue to be compared
Returns
return the bigger value

Definition at line 1722 of file core_feature_base.h.

1723 {
1724  uint32_t result;
1725 
1726  __ASM volatile ("amomaxu.w %0, %2, %1" : \
1727  "=r"(result), "+A"(*addr) : "r"(value) : "memory");
1728  return *addr;
1729 }

References __ASM.

◆ __AMOMIN_W()

__STATIC_FORCEINLINE int32_t __AMOMIN_W ( volatile int32_t *  addr,
int32_t  value 
)

Atomic signed MIN with 32bit value.

Atomically signed min compare 32bit value with value in memory using amomin.d.

Parameters
[in]addrAddress pointer to data, address need to be 4byte aligned
[in]valuevalue to be compared
Returns
the smaller value

Definition at line 1770 of file core_feature_base.h.

1771 {
1772  int32_t result;
1773 
1774  __ASM volatile ("amomin.w %0, %2, %1" : \
1775  "=r"(result), "+A"(*addr) : "r"(value) : "memory");
1776  return *addr;
1777 }

References __ASM.

◆ __AMOMINU_W()

__STATIC_FORCEINLINE uint32_t __AMOMINU_W ( volatile uint32_t *  addr,
uint32_t  value 
)

Atomic unsigned MIN with 32bit value.

Atomically unsigned min compare 32bit value with value in memory using amominu.d.

Parameters
[in]addrAddress pointer to data, address need to be 4byte aligned
[in]valuevalue to be compared
Returns
the smaller value

Definition at line 1754 of file core_feature_base.h.

1755 {
1756  uint32_t result;
1757 
1758  __ASM volatile ("amominu.w %0, %2, %1" : \
1759  "=r"(result), "+A"(*addr) : "r"(value) : "memory");
1760  return *addr;
1761 }

References __ASM.

◆ __AMOOR_W()

__STATIC_FORCEINLINE int32_t __AMOOR_W ( volatile int32_t *  addr,
int32_t  value 
)

Atomic OR with 32bit value.

Atomically OR 32bit value with value in memory using amoor.d.

Parameters
[in]addrAddress pointer to data, address need to be 4byte aligned
[in]valuevalue to be ORed
Returns
return memory value | and value

Definition at line 1690 of file core_feature_base.h.

1691 {
1692  int32_t result;
1693 
1694  __ASM volatile ("amoor.w %0, %2, %1" : \
1695  "=r"(result), "+A"(*addr) : "r"(value) : "memory");
1696  return *addr;
1697 }

References __ASM.

◆ __AMOSWAP_W()

__STATIC_FORCEINLINE uint32_t __AMOSWAP_W ( volatile uint32_t *  addr,
uint32_t  newval 
)

Atomic Swap 32bit value into memory.

Atomically swap new 32bit value into memory using amoswap.d.

Parameters
[in]addrAddress pointer to data, address need to be 4byte aligned
[in]newvalNew value to be stored into the address
Returns
return the original value in memory

Definition at line 1642 of file core_feature_base.h.

1643 {
1644  uint32_t result;
1645 
1646  __ASM volatile ("amoswap.w %0, %2, %1" : \
1647  "=r"(result), "+A"(*addr) : "r"(newval) : "memory");
1648  return result;
1649 }

References __ASM.

◆ __AMOXOR_W()

__STATIC_FORCEINLINE int32_t __AMOXOR_W ( volatile int32_t *  addr,
int32_t  value 
)

Atomic XOR with 32bit value.

Atomically XOR 32bit value with value in memory using amoxor.d.

Parameters
[in]addrAddress pointer to data, address need to be 4byte aligned
[in]valuevalue to be XORed
Returns
return memory value ^ and value

Definition at line 1706 of file core_feature_base.h.

1707 {
1708  int32_t result;
1709 
1710  __ASM volatile ("amoxor.w %0, %2, %1" : \
1711  "=r"(result), "+A"(*addr) : "r"(value) : "memory");
1712  return *addr;
1713 }

References __ASM.

◆ __CAS_W()

__STATIC_FORCEINLINE uint32_t __CAS_W ( volatile uint32_t *  addr,
uint32_t  oldval,
uint32_t  newval 
)

Compare and Swap 32bit value using LR and SC.

Compare old value with memory, if identical, store new value in memory. Return the initial value in memory. Success is indicated by comparing return value with OLD. memory address, return 0 if successful, otherwise return !0

Parameters
[in]addrAddress pointer to data, address need to be 4byte aligned
[in]oldvalOld value of the data in address
[in]newvalNew value to be stored into the address
Returns
return the initial value in memory

Definition at line 1618 of file core_feature_base.h.

1619 {
1620  uint32_t result;
1621  uint32_t rc;
1622 
1623  __ASM volatile ( \
1624  "0: lr.w %0, %2 \n" \
1625  " bne %0, %z3, 1f \n" \
1626  " sc.w %1, %z4, %2 \n" \
1627  " bnez %1, 0b \n" \
1628  "1:\n" \
1629  : "=&r"(result), "=&r"(rc), "+A"(*addr) \
1630  : "r"(oldval), "r"(newval) \
1631  : "memory");
1632  return result;
1633 }

References __ASM.

◆ __disable_all_counter()

__STATIC_FORCEINLINE void __disable_all_counter ( void  )

Disable all MCYCLE & MINSTRET & MHPMCOUNTER counter.

Set all to one to disable all counters, such as cycle, instret, high performance monitor counters

Definition at line 1013 of file core_feature_base.h.

1014 {
1015  __RV_CSR_SET(CSR_MCOUNTINHIBIT, 0xFFFFFFFF);
1016 }

References __RV_CSR_SET, and CSR_MCOUNTINHIBIT.

◆ __disable_mcycle_counter()

__STATIC_FORCEINLINE void __disable_mcycle_counter ( void  )

Disable MCYCLE counter.

Set the CY bit of MCOUNTINHIBIT to 1 to disable MCYCLE Counter

Definition at line 925 of file core_feature_base.h.

References __RV_CSR_SET, CSR_MCOUNTINHIBIT, and MCOUNTINHIBIT_CY.

◆ __disable_mhpm_counter()

__STATIC_FORCEINLINE void __disable_mhpm_counter ( unsigned long  idx)

Disable selected hardware performance monitor counter.

Parameters
[in]idxthe index of the hardware performance monitor counter

Disable selected hardware performance monitor counter mhpmcounterx.

Definition at line 967 of file core_feature_base.h.

968 {
969  __RV_CSR_SET(CSR_MCOUNTINHIBIT, (1 << idx));
970 }

References __RV_CSR_SET, and CSR_MCOUNTINHIBIT.

◆ __disable_mhpm_counters()

__STATIC_FORCEINLINE void __disable_mhpm_counters ( unsigned long  mask)

Disable hardware performance counters with mask.

Parameters
[in]maskmask of selected hardware performance monitor counters

Disable mhpmcounterx with mask, only the masked ones will be disabled. mhpmcounter3-mhpmcount31 are for high performance monitor counters.

Definition at line 991 of file core_feature_base.h.

992 {
994 }

References __RV_CSR_SET, and CSR_MCOUNTINHIBIT.

◆ __disable_minstret_counter()

__STATIC_FORCEINLINE void __disable_minstret_counter ( void  )

Disable MINSTRET counter.

Set the IR bit of MCOUNTINHIBIT to 1 to disable MINSTRET Counter

Definition at line 945 of file core_feature_base.h.

References __RV_CSR_SET, CSR_MCOUNTINHIBIT, and MCOUNTINHIBIT_IR.

◆ __EBREAK()

__STATIC_FORCEINLINE void __EBREAK ( void  )

Breakpoint Instruction.

Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.

Definition at line 863 of file core_feature_base.h.

864 {
865  __ASM volatile("ebreak");
866 }

References __ASM.

◆ __ECALL()

__STATIC_FORCEINLINE void __ECALL ( void  )

Environment Call Instruction.

The ECALL instruction is used to make a service request to the execution environment.

Definition at line 874 of file core_feature_base.h.

875 {
876  __ASM volatile("ecall");
877 }

References __ASM.

◆ __enable_all_counter()

__STATIC_FORCEINLINE void __enable_all_counter ( void  )

Enable all MCYCLE & MINSTRET & MHPMCOUNTER counter.

Clear all to zero to enable all counters, such as cycle, instret, high performance monitor counters

Definition at line 1002 of file core_feature_base.h.

1003 {
1004  __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, 0xFFFFFFFF);
1005 }

References __RV_CSR_CLEAR, and CSR_MCOUNTINHIBIT.

◆ __enable_mcycle_counter()

__STATIC_FORCEINLINE void __enable_mcycle_counter ( void  )

Enable MCYCLE counter.

Clear the CY bit of MCOUNTINHIBIT to 0 to enable MCYCLE Counter

Definition at line 915 of file core_feature_base.h.

References __RV_CSR_CLEAR, CSR_MCOUNTINHIBIT, and MCOUNTINHIBIT_CY.

◆ __enable_mhpm_counter()

__STATIC_FORCEINLINE void __enable_mhpm_counter ( unsigned long  idx)

Enable selected hardware performance monitor counter.

Parameters
[in]idxthe index of the hardware performance monitor counter

enable selected hardware performance monitor counter mhpmcounterx.

Definition at line 956 of file core_feature_base.h.

957 {
958  __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, (1 << idx));
959 }

References __RV_CSR_CLEAR, and CSR_MCOUNTINHIBIT.

◆ __enable_mhpm_counters()

__STATIC_FORCEINLINE void __enable_mhpm_counters ( unsigned long  mask)

Enable hardware performance counters with mask.

Parameters
[in]maskmask of selected hardware performance monitor counters

enable mhpmcounterx with mask, only the masked ones will be enabled. mhpmcounter3-mhpmcount31 are for high performance monitor counters.

Definition at line 979 of file core_feature_base.h.

980 {
982 }

References __RV_CSR_CLEAR, and CSR_MCOUNTINHIBIT.

◆ __enable_minstret_counter()

__STATIC_FORCEINLINE void __enable_minstret_counter ( void  )

Enable MINSTRET counter.

Clear the IR bit of MCOUNTINHIBIT to 0 to enable MINSTRET Counter

Definition at line 935 of file core_feature_base.h.

References __RV_CSR_CLEAR, CSR_MCOUNTINHIBIT, and MCOUNTINHIBIT_IR.

◆ __FENCE_I()

__STATIC_FORCEINLINE void __FENCE_I ( void  )

Fence.i Instruction.

The FENCE.I instruction is used to synchronize the instruction and data streams.

Definition at line 1475 of file core_feature_base.h.

1476 {
1477  __ASM volatile("fence.i");
1478 }

References __ASM.

Referenced by __ECLIC_SetVector(), and __ECLIC_SetVector_S().

◆ __get_hpm_counter()

__STATIC_FORCEINLINE unsigned long __get_hpm_counter ( unsigned long  idx)

Get value of selected high performance monitor couner.

Parameters
[in]idxHPMCOUNTERx CSR index(3-31)
[in]eventHPMCOUNTERx Register value to set

Get high performance monitor counter register value

Returns
HPMCOUNTERx Register value

Definition at line 1249 of file core_feature_base.h.

1250 {
1251 #if __RISCV_XLEN == 32
1252  volatile uint32_t high0, low, high;
1253  uint64_t full;
1254 
1255  switch (idx) {
1256  case 0: return __get_rv_cycle();
1257  case 2: return __get_rv_instret();
1258  case 3: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER3H);
1261  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER3); }
1262  full = (((uint64_t)high) << 32) | low; return full;
1263  case 4: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER4H);
1266  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER4); }
1267  full = (((uint64_t)high) << 32) | low; return full;
1268  case 5: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER5H);
1271  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER5); }
1272  full = (((uint64_t)high) << 32) | low; return full;
1273  case 6: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER6H);
1276  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER6); }
1277  full = (((uint64_t)high) << 32) | low; return full;
1278  case 7: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER7H);
1281  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER7); }
1282  full = (((uint64_t)high) << 32) | low; return full;
1283  case 8: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER8H);
1286  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER8); }
1287  full = (((uint64_t)high) << 32) | low; return full;
1288  case 9: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER9H);
1291  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER9); }
1292  full = (((uint64_t)high) << 32) | low; return full;
1293  case 10: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER10H);
1296  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER10); }
1297  full = (((uint64_t)high) << 32) | low; return full;
1298  case 11: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER11H);
1301  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER11); }
1302  full = (((uint64_t)high) << 32) | low; return full;
1303  case 12: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER12H);
1306  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER12); }
1307  full = (((uint64_t)high) << 32) | low; return full;
1308  case 13: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER13H);
1311  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER13); }
1312  full = (((uint64_t)high) << 32) | low; return full;
1313  case 14: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER14H);
1316  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER14); }
1317  full = (((uint64_t)high) << 32) | low; return full;
1318  case 15: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER15H);
1321  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER15); }
1322  full = (((uint64_t)high) << 32) | low; return full;
1323  case 16: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER16H);
1326  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER16); }
1327  full = (((uint64_t)high) << 32) | low; return full;
1328  case 17: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER17H);
1331  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER17); }
1332  full = (((uint64_t)high) << 32) | low; return full;
1333  case 18: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER18H);
1336  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER18); }
1337  full = (((uint64_t)high) << 32) | low; return full;
1338  case 19: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER19H);
1341  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER19); }
1342  full = (((uint64_t)high) << 32) | low; return full;
1343  case 20: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER20H);
1346  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER20); }
1347  full = (((uint64_t)high) << 32) | low; return full;
1348  case 21: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER21H);
1351  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER21); }
1352  full = (((uint64_t)high) << 32) | low; return full;
1353  case 22: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER22H);
1356  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER22); }
1357  full = (((uint64_t)high) << 32) | low; return full;
1358  case 23: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER23H);
1361  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER23); }
1362  full = (((uint64_t)high) << 32) | low; return full;
1363  case 24: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER24H);
1366  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER24); }
1367  full = (((uint64_t)high) << 32) | low; return full;
1368  case 25: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER25H);
1371  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER25); }
1372  full = (((uint64_t)high) << 32) | low; return full;
1373  case 26: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER26H);
1376  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER26); }
1377  full = (((uint64_t)high) << 32) | low; return full;
1378  case 27: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER27H);
1381  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER27); }
1382  full = (((uint64_t)high) << 32) | low; return full;
1383  case 28: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER28H);
1386  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER28); }
1387  full = (((uint64_t)high) << 32) | low; return full;
1388  case 29: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER29H);
1391  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER29); }
1392  full = (((uint64_t)high) << 32) | low; return full;
1393  case 30: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER30H);
1396  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER30); }
1397  full = (((uint64_t)high) << 32) | low; return full;
1398  case 31: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER31H);
1401  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER31); }
1402  full = (((uint64_t)high) << 32) | low; return full;
1403 
1404 #elif __RISCV_XLEN == 64
1405  switch (idx) {
1406  case 0: return __get_rv_cycle();
1407  case 2: return __get_rv_instret();
1408  case 3: return __RV_CSR_READ(CSR_MHPMCOUNTER3);
1409  case 4: return __RV_CSR_READ(CSR_MHPMCOUNTER4);
1410  case 5: return __RV_CSR_READ(CSR_MHPMCOUNTER5);
1411  case 6: return __RV_CSR_READ(CSR_MHPMCOUNTER6);
1412  case 7: return __RV_CSR_READ(CSR_MHPMCOUNTER7);
1413  case 8: return __RV_CSR_READ(CSR_MHPMCOUNTER8);
1414  case 9: return __RV_CSR_READ(CSR_MHPMCOUNTER9);
1415  case 10: return __RV_CSR_READ(CSR_MHPMCOUNTER10);
1416  case 11: return __RV_CSR_READ(CSR_MHPMCOUNTER11);
1417  case 12: return __RV_CSR_READ(CSR_MHPMCOUNTER12);
1418  case 13: return __RV_CSR_READ(CSR_MHPMCOUNTER13);
1419  case 14: return __RV_CSR_READ(CSR_MHPMCOUNTER14);
1420  case 15: return __RV_CSR_READ(CSR_MHPMCOUNTER15);
1421  case 16: return __RV_CSR_READ(CSR_MHPMCOUNTER16);
1422  case 17: return __RV_CSR_READ(CSR_MHPMCOUNTER17);
1423  case 18: return __RV_CSR_READ(CSR_MHPMCOUNTER18);
1424  case 19: return __RV_CSR_READ(CSR_MHPMCOUNTER19);
1425  case 20: return __RV_CSR_READ(CSR_MHPMCOUNTER20);
1426  case 21: return __RV_CSR_READ(CSR_MHPMCOUNTER21);
1427  case 22: return __RV_CSR_READ(CSR_MHPMCOUNTER22);
1428  case 23: return __RV_CSR_READ(CSR_MHPMCOUNTER23);
1429  case 24: return __RV_CSR_READ(CSR_MHPMCOUNTER24);
1430  case 25: return __RV_CSR_READ(CSR_MHPMCOUNTER25);
1431  case 26: return __RV_CSR_READ(CSR_MHPMCOUNTER26);
1432  case 27: return __RV_CSR_READ(CSR_MHPMCOUNTER27);
1433  case 28: return __RV_CSR_READ(CSR_MHPMCOUNTER28);
1434  case 29: return __RV_CSR_READ(CSR_MHPMCOUNTER29);
1435  case 30: return __RV_CSR_READ(CSR_MHPMCOUNTER30);
1436  case 31: return __RV_CSR_READ(CSR_MHPMCOUNTER31);
1437 
1438 #else
1439  switch (idx) {
1440 #endif
1441  default: return 0;
1442  }
1443 }

References __get_rv_cycle(), __get_rv_instret(), __RV_CSR_READ, CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11, CSR_MHPMCOUNTER11H, CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15, CSR_MHPMCOUNTER15H, CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19, CSR_MHPMCOUNTER19H, CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23, CSR_MHPMCOUNTER23H, CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27, CSR_MHPMCOUNTER27H, CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER3, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31, CSR_MHPMCOUNTER31H, CSR_MHPMCOUNTER3H, CSR_MHPMCOUNTER4, CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7, CSR_MHPMCOUNTER7H, CSR_MHPMCOUNTER8, CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9, and CSR_MHPMCOUNTER9H.

◆ __get_hpm_event()

__STATIC_FORCEINLINE unsigned long __get_hpm_event ( unsigned long  idx)

Get event for selected high performance monitor event.

Parameters
[in]idxHPMEVENTx CSR index(3-31)
[in]eventHPMEVENTx Register value to set

Get high performance monitor event register value

Returns
HPMEVENTx Register value

Definition at line 1069 of file core_feature_base.h.

1070 {
1071  switch (idx) {
1072  case 3: return __RV_CSR_READ(CSR_MHPMEVENT3);
1073  case 4: return __RV_CSR_READ(CSR_MHPMEVENT4);
1074  case 5: return __RV_CSR_READ(CSR_MHPMEVENT5);
1075  case 6: return __RV_CSR_READ(CSR_MHPMEVENT6);
1076  case 7: return __RV_CSR_READ(CSR_MHPMEVENT7);
1077  case 8: return __RV_CSR_READ(CSR_MHPMEVENT8);
1078  case 9: return __RV_CSR_READ(CSR_MHPMEVENT9);
1079  case 10: return __RV_CSR_READ(CSR_MHPMEVENT10);
1080  case 11: return __RV_CSR_READ(CSR_MHPMEVENT11);
1081  case 12: return __RV_CSR_READ(CSR_MHPMEVENT12);
1082  case 13: return __RV_CSR_READ(CSR_MHPMEVENT13);
1083  case 14: return __RV_CSR_READ(CSR_MHPMEVENT14);
1084  case 15: return __RV_CSR_READ(CSR_MHPMEVENT15);
1085  case 16: return __RV_CSR_READ(CSR_MHPMEVENT16);
1086  case 17: return __RV_CSR_READ(CSR_MHPMEVENT17);
1087  case 18: return __RV_CSR_READ(CSR_MHPMEVENT18);
1088  case 19: return __RV_CSR_READ(CSR_MHPMEVENT19);
1089  case 20: return __RV_CSR_READ(CSR_MHPMEVENT20);
1090  case 21: return __RV_CSR_READ(CSR_MHPMEVENT21);
1091  case 22: return __RV_CSR_READ(CSR_MHPMEVENT22);
1092  case 23: return __RV_CSR_READ(CSR_MHPMEVENT23);
1093  case 24: return __RV_CSR_READ(CSR_MHPMEVENT24);
1094  case 25: return __RV_CSR_READ(CSR_MHPMEVENT25);
1095  case 26: return __RV_CSR_READ(CSR_MHPMEVENT26);
1096  case 27: return __RV_CSR_READ(CSR_MHPMEVENT27);
1097  case 28: return __RV_CSR_READ(CSR_MHPMEVENT28);
1098  case 29: return __RV_CSR_READ(CSR_MHPMEVENT29);
1099  case 30: return __RV_CSR_READ(CSR_MHPMEVENT30);
1100  case 31: return __RV_CSR_READ(CSR_MHPMEVENT31);
1101  default: return 0;
1102  }
1103 }

References __RV_CSR_READ, CSR_MHPMEVENT10, CSR_MHPMEVENT11, CSR_MHPMEVENT12, CSR_MHPMEVENT13, CSR_MHPMEVENT14, CSR_MHPMEVENT15, CSR_MHPMEVENT16, CSR_MHPMEVENT17, CSR_MHPMEVENT18, CSR_MHPMEVENT19, CSR_MHPMEVENT20, CSR_MHPMEVENT21, CSR_MHPMEVENT22, CSR_MHPMEVENT23, CSR_MHPMEVENT24, CSR_MHPMEVENT25, CSR_MHPMEVENT26, CSR_MHPMEVENT27, CSR_MHPMEVENT28, CSR_MHPMEVENT29, CSR_MHPMEVENT3, CSR_MHPMEVENT30, CSR_MHPMEVENT31, CSR_MHPMEVENT4, CSR_MHPMEVENT5, CSR_MHPMEVENT6, CSR_MHPMEVENT7, CSR_MHPMEVENT8, and CSR_MHPMEVENT9.

◆ __LB()

__STATIC_FORCEINLINE uint8_t __LB ( volatile void *  addr)

Load 8bit value from address (8 bit)

Load 8 bit value.

Parameters
[in]addrAddress pointer to data
Returns
value of type uint8_t at (*addr)

Definition at line 1509 of file core_feature_base.h.

1510 {
1511  uint8_t result;
1512 
1513  __ASM volatile ("lb %0, 0(%1)" : "=r" (result) : "r" (addr));
1514  return result;
1515 }

References __ASM.

◆ __LH()

__STATIC_FORCEINLINE uint16_t __LH ( volatile void *  addr)

Load 16bit value from address (16 bit)

Load 16 bit value.

Parameters
[in]addrAddress pointer to data
Returns
value of type uint16_t at (*addr)

Definition at line 1523 of file core_feature_base.h.

1524 {
1525  uint16_t result;
1526 
1527  __ASM volatile ("lh %0, 0(%1)" : "=r" (result) : "r" (addr));
1528  return result;
1529 }

References __ASM.

◆ __LW()

__STATIC_FORCEINLINE uint32_t __LW ( volatile void *  addr)

Load 32bit value from address (32 bit)

Load 32 bit value.

Parameters
[in]addrAddress pointer to data
Returns
value of type uint32_t at (*addr)

Definition at line 1537 of file core_feature_base.h.

1538 {
1539  uint32_t result;
1540 
1541  __ASM volatile ("lw %0, 0(%1)" : "=r" (result) : "r" (addr));
1542  return result;
1543 }

References __ASM.

Referenced by SysTimer_GetHartCompareValue(), SysTimer_GetHartMsipValue(), and SysTimer_GetLoadValue().

◆ __NOP()

__STATIC_FORCEINLINE void __NOP ( void  )

NOP Instruction.

No Operation does nothing. This instruction can be used for code alignment purposes.

Definition at line 822 of file core_feature_base.h.

823 {
824  __ASM volatile("nop");
825 }

References __ASM.

◆ __SB()

__STATIC_FORCEINLINE void __SB ( volatile void *  addr,
uint8_t  val 
)

Write 8bit value to address (8 bit)

Write 8 bit value.

Parameters
[in]addrAddress pointer to data
[in]valValue to set

Definition at line 1567 of file core_feature_base.h.

1568 {
1569  __ASM volatile ("sb %0, 0(%1)" : : "r" (val), "r" (addr));
1570 }

References __ASM.

◆ __set_hpm_counter()

__STATIC_FORCEINLINE void __set_hpm_counter ( unsigned long  idx,
uint64_t  value 
)

Set value for selected high performance monitor counter.

Parameters
[in]idxHPMCOUNTERx CSR index(3-31)
[in]valueHPMCOUNTERx Register value to set

Set value for high performance monitor couner register

Definition at line 1112 of file core_feature_base.h.

1113 {
1114  switch (idx) {
1115 #if __RISCV_XLEN == 32
1116  case 3: __RV_CSR_WRITE(CSR_MHPMCOUNTER3, 0); // prevent carry
1117  __RV_CSR_WRITE(CSR_MHPMCOUNTER3H, (uint32_t)(value >> 32));
1118  __RV_CSR_WRITE(CSR_MHPMCOUNTER3, (uint32_t)(value)); break;
1119  case 4: __RV_CSR_WRITE(CSR_MHPMCOUNTER4, 0); // prevent carry
1120  __RV_CSR_WRITE(CSR_MHPMCOUNTER4H, (uint32_t)(value >> 32));
1121  __RV_CSR_WRITE(CSR_MHPMCOUNTER4, (uint32_t)(value)); break;
1122  case 5: __RV_CSR_WRITE(CSR_MHPMCOUNTER5, 0); // prevent carry
1123  __RV_CSR_WRITE(CSR_MHPMCOUNTER5H, (uint32_t)(value >> 32));
1124  __RV_CSR_WRITE(CSR_MHPMCOUNTER5, (uint32_t)(value)); break;
1125  case 6: __RV_CSR_WRITE(CSR_MHPMCOUNTER6, 0); // prevent carry
1126  __RV_CSR_WRITE(CSR_MHPMCOUNTER6H, (uint32_t)(value >> 32));
1127  __RV_CSR_WRITE(CSR_MHPMCOUNTER6, (uint32_t)(value)); break;
1128  case 7: __RV_CSR_WRITE(CSR_MHPMCOUNTER7, 0); // prevent carry
1129  __RV_CSR_WRITE(CSR_MHPMCOUNTER7H, (uint32_t)(value >> 32));
1130  __RV_CSR_WRITE(CSR_MHPMCOUNTER7, (uint32_t)(value)); break;
1131  case 8: __RV_CSR_WRITE(CSR_MHPMCOUNTER8, 0); // prevent carry
1132  __RV_CSR_WRITE(CSR_MHPMCOUNTER8H, (uint32_t)(value >> 32));
1133  __RV_CSR_WRITE(CSR_MHPMCOUNTER8, (uint32_t)(value)); break;
1134  case 9: __RV_CSR_WRITE(CSR_MHPMCOUNTER9, 0); // prevent carry
1135  __RV_CSR_WRITE(CSR_MHPMCOUNTER9H, (uint32_t)(value >> 32));
1136  __RV_CSR_WRITE(CSR_MHPMCOUNTER9, (uint32_t)(value)); break;
1137  case 10: __RV_CSR_WRITE(CSR_MHPMCOUNTER10, 0); // prevent carry
1138  __RV_CSR_WRITE(CSR_MHPMCOUNTER10H, (uint32_t)(value >> 32));
1139  __RV_CSR_WRITE(CSR_MHPMCOUNTER10, (uint32_t)(value)); break;
1140  case 11: __RV_CSR_WRITE(CSR_MHPMCOUNTER11, 0); // prevent carry
1141  __RV_CSR_WRITE(CSR_MHPMCOUNTER11H, (uint32_t)(value >> 32));
1142  __RV_CSR_WRITE(CSR_MHPMCOUNTER11, (uint32_t)(value)); break;
1143  case 12: __RV_CSR_WRITE(CSR_MHPMCOUNTER12, 0); // prevent carry
1144  __RV_CSR_WRITE(CSR_MHPMCOUNTER12H, (uint32_t)(value >> 32));
1145  __RV_CSR_WRITE(CSR_MHPMCOUNTER12, (uint32_t)(value)); break;
1146  case 13: __RV_CSR_WRITE(CSR_MHPMCOUNTER13, 0); // prevent carry
1147  __RV_CSR_WRITE(CSR_MHPMCOUNTER13H, (uint32_t)(value >> 32));
1148  __RV_CSR_WRITE(CSR_MHPMCOUNTER13, (uint32_t)(value)); break;
1149  case 14: __RV_CSR_WRITE(CSR_MHPMCOUNTER14, 0); // prevent carry
1150  __RV_CSR_WRITE(CSR_MHPMCOUNTER14H, (uint32_t)(value >> 32));
1151  __RV_CSR_WRITE(CSR_MHPMCOUNTER14, (uint32_t)(value)); break;
1152  case 15: __RV_CSR_WRITE(CSR_MHPMCOUNTER15, 0); // prevent carry
1153  __RV_CSR_WRITE(CSR_MHPMCOUNTER15H, (uint32_t)(value >> 32));
1154  __RV_CSR_WRITE(CSR_MHPMCOUNTER15, (uint32_t)(value)); break;
1155  case 16: __RV_CSR_WRITE(CSR_MHPMCOUNTER16, 0); // prevent carry
1156  __RV_CSR_WRITE(CSR_MHPMCOUNTER16H, (uint32_t)(value >> 32));
1157  __RV_CSR_WRITE(CSR_MHPMCOUNTER16, (uint32_t)(value)); break;
1158  case 17: __RV_CSR_WRITE(CSR_MHPMCOUNTER17, 0); // prevent carry
1159  __RV_CSR_WRITE(CSR_MHPMCOUNTER17H, (uint32_t)(value >> 32));
1160  __RV_CSR_WRITE(CSR_MHPMCOUNTER17, (uint32_t)(value)); break;
1161  case 18: __RV_CSR_WRITE(CSR_MHPMCOUNTER18, 0); // prevent carry
1162  __RV_CSR_WRITE(CSR_MHPMCOUNTER18H, (uint32_t)(value >> 32));
1163  __RV_CSR_WRITE(CSR_MHPMCOUNTER18, (uint32_t)(value)); break;
1164  case 19: __RV_CSR_WRITE(CSR_MHPMCOUNTER19, 0); // prevent carry
1165  __RV_CSR_WRITE(CSR_MHPMCOUNTER19H, (uint32_t)(value >> 32));
1166  __RV_CSR_WRITE(CSR_MHPMCOUNTER19, (uint32_t)(value)); break;
1167  case 20: __RV_CSR_WRITE(CSR_MHPMCOUNTER20, 0); // prevent carry
1168  __RV_CSR_WRITE(CSR_MHPMCOUNTER20H, (uint32_t)(value >> 32));
1169  __RV_CSR_WRITE(CSR_MHPMCOUNTER20, (uint32_t)(value)); break;
1170  case 21: __RV_CSR_WRITE(CSR_MHPMCOUNTER21, 0); // prevent carry
1171  __RV_CSR_WRITE(CSR_MHPMCOUNTER21H, (uint32_t)(value >> 32));
1172  __RV_CSR_WRITE(CSR_MHPMCOUNTER21, (uint32_t)(value)); break;
1173  case 22: __RV_CSR_WRITE(CSR_MHPMCOUNTER22, 0); // prevent carry
1174  __RV_CSR_WRITE(CSR_MHPMCOUNTER22H, (uint32_t)(value >> 32));
1175  __RV_CSR_WRITE(CSR_MHPMCOUNTER22, (uint32_t)(value)); break;
1176  case 23: __RV_CSR_WRITE(CSR_MHPMCOUNTER23, 0); // prevent carry
1177  __RV_CSR_WRITE(CSR_MHPMCOUNTER23H, (uint32_t)(value >> 32));
1178  __RV_CSR_WRITE(CSR_MHPMCOUNTER23, (uint32_t)(value)); break;
1179  case 24: __RV_CSR_WRITE(CSR_MHPMCOUNTER24, 0); // prevent carry
1180  __RV_CSR_WRITE(CSR_MHPMCOUNTER24H, (uint32_t)(value >> 32));
1181  __RV_CSR_WRITE(CSR_MHPMCOUNTER24, (uint32_t)(value)); break;
1182  case 25: __RV_CSR_WRITE(CSR_MHPMCOUNTER25, 0); // prevent carry
1183  __RV_CSR_WRITE(CSR_MHPMCOUNTER25H, (uint32_t)(value >> 32));
1184  __RV_CSR_WRITE(CSR_MHPMCOUNTER25, (uint32_t)(value)); break;
1185  case 26: __RV_CSR_WRITE(CSR_MHPMCOUNTER26, 0); // prevent carry
1186  __RV_CSR_WRITE(CSR_MHPMCOUNTER26H, (uint32_t)(value >> 32));
1187  __RV_CSR_WRITE(CSR_MHPMCOUNTER26, (uint32_t)(value)); break;
1188  case 27: __RV_CSR_WRITE(CSR_MHPMCOUNTER27, 0); // prevent carry
1189  __RV_CSR_WRITE(CSR_MHPMCOUNTER27H, (uint32_t)(value >> 32));
1190  __RV_CSR_WRITE(CSR_MHPMCOUNTER27, (uint32_t)(value)); break;
1191  case 28: __RV_CSR_WRITE(CSR_MHPMCOUNTER28, 0); // prevent carry
1192  __RV_CSR_WRITE(CSR_MHPMCOUNTER28H, (uint32_t)(value >> 32));
1193  __RV_CSR_WRITE(CSR_MHPMCOUNTER28, (uint32_t)(value)); break;
1194  case 29: __RV_CSR_WRITE(CSR_MHPMCOUNTER29, 0); // prevent carry
1195  __RV_CSR_WRITE(CSR_MHPMCOUNTER29H, (uint32_t)(value >> 32));
1196  __RV_CSR_WRITE(CSR_MHPMCOUNTER29, (uint32_t)(value)); break;
1197  case 30: __RV_CSR_WRITE(CSR_MHPMCOUNTER30, 0); // prevent carry
1198  __RV_CSR_WRITE(CSR_MHPMCOUNTER30H, (uint32_t)(value >> 32));
1199  __RV_CSR_WRITE(CSR_MHPMCOUNTER30, (uint32_t)(value)); break;
1200  case 31: __RV_CSR_WRITE(CSR_MHPMCOUNTER31, 0); // prevent carry
1201  __RV_CSR_WRITE(CSR_MHPMCOUNTER31H, (uint32_t)(value >> 32));
1202  __RV_CSR_WRITE(CSR_MHPMCOUNTER31, (uint32_t)(value)); break;
1203 
1204 #elif __RISCV_XLEN == 64
1205  case 3: __RV_CSR_WRITE(CSR_MHPMCOUNTER3, (value)); break;
1206  case 4: __RV_CSR_WRITE(CSR_MHPMCOUNTER4, (value)); break;
1207  case 5: __RV_CSR_WRITE(CSR_MHPMCOUNTER5, (value)); break;
1208  case 6: __RV_CSR_WRITE(CSR_MHPMCOUNTER6, (value)); break;
1209  case 7: __RV_CSR_WRITE(CSR_MHPMCOUNTER7, (value)); break;
1210  case 8: __RV_CSR_WRITE(CSR_MHPMCOUNTER8, (value)); break;
1211  case 9: __RV_CSR_WRITE(CSR_MHPMCOUNTER9, (value)); break;
1212  case 10: __RV_CSR_WRITE(CSR_MHPMCOUNTER10, (value)); break;
1213  case 11: __RV_CSR_WRITE(CSR_MHPMCOUNTER11, (value)); break;
1214  case 12: __RV_CSR_WRITE(CSR_MHPMCOUNTER12, (value)); break;
1215  case 13: __RV_CSR_WRITE(CSR_MHPMCOUNTER13, (value)); break;
1216  case 14: __RV_CSR_WRITE(CSR_MHPMCOUNTER14, (value)); break;
1217  case 15: __RV_CSR_WRITE(CSR_MHPMCOUNTER15, (value)); break;
1218  case 16: __RV_CSR_WRITE(CSR_MHPMCOUNTER16, (value)); break;
1219  case 17: __RV_CSR_WRITE(CSR_MHPMCOUNTER17, (value)); break;
1220  case 18: __RV_CSR_WRITE(CSR_MHPMCOUNTER18, (value)); break;
1221  case 19: __RV_CSR_WRITE(CSR_MHPMCOUNTER19, (value)); break;
1222  case 20: __RV_CSR_WRITE(CSR_MHPMCOUNTER20, (value)); break;
1223  case 21: __RV_CSR_WRITE(CSR_MHPMCOUNTER21, (value)); break;
1224  case 22: __RV_CSR_WRITE(CSR_MHPMCOUNTER22, (value)); break;
1225  case 23: __RV_CSR_WRITE(CSR_MHPMCOUNTER23, (value)); break;
1226  case 24: __RV_CSR_WRITE(CSR_MHPMCOUNTER24, (value)); break;
1227  case 25: __RV_CSR_WRITE(CSR_MHPMCOUNTER25, (value)); break;
1228  case 26: __RV_CSR_WRITE(CSR_MHPMCOUNTER26, (value)); break;
1229  case 27: __RV_CSR_WRITE(CSR_MHPMCOUNTER27, (value)); break;
1230  case 28: __RV_CSR_WRITE(CSR_MHPMCOUNTER28, (value)); break;
1231  case 29: __RV_CSR_WRITE(CSR_MHPMCOUNTER29, (value)); break;
1232  case 30: __RV_CSR_WRITE(CSR_MHPMCOUNTER30, (value)); break;
1233  case 31: __RV_CSR_WRITE(CSR_MHPMCOUNTER31, (value)); break;
1234 
1235 #else
1236 #endif
1237  default: break;
1238  }
1239 }

References __RV_CSR_WRITE, CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11, CSR_MHPMCOUNTER11H, CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15, CSR_MHPMCOUNTER15H, CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19, CSR_MHPMCOUNTER19H, CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23, CSR_MHPMCOUNTER23H, CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27, CSR_MHPMCOUNTER27H, CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER3, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31, CSR_MHPMCOUNTER31H, CSR_MHPMCOUNTER3H, CSR_MHPMCOUNTER4, CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7, CSR_MHPMCOUNTER7H, CSR_MHPMCOUNTER8, CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9, and CSR_MHPMCOUNTER9H.

◆ __set_hpm_event()

__STATIC_FORCEINLINE void __set_hpm_event ( unsigned long  idx,
unsigned long  event 
)

Set event for selected high performance monitor event.

Parameters
[in]idxHPMEVENTx CSR index(3-31)
[in]eventHPMEVENTx Register value to set

Set event for high performance monitor event register

Definition at line 1025 of file core_feature_base.h.

1026 {
1027  switch (idx) {
1028  case 3: __RV_CSR_WRITE(CSR_MHPMEVENT3, event); break;
1029  case 4: __RV_CSR_WRITE(CSR_MHPMEVENT4, event); break;
1030  case 5: __RV_CSR_WRITE(CSR_MHPMEVENT5, event); break;
1031  case 6: __RV_CSR_WRITE(CSR_MHPMEVENT6, event); break;
1032  case 7: __RV_CSR_WRITE(CSR_MHPMEVENT7, event); break;
1033  case 8: __RV_CSR_WRITE(CSR_MHPMEVENT8, event); break;
1034  case 9: __RV_CSR_WRITE(CSR_MHPMEVENT9, event); break;
1035  case 10: __RV_CSR_WRITE(CSR_MHPMEVENT10, event); break;
1036  case 11: __RV_CSR_WRITE(CSR_MHPMEVENT11, event); break;
1037  case 12: __RV_CSR_WRITE(CSR_MHPMEVENT12, event); break;
1038  case 13: __RV_CSR_WRITE(CSR_MHPMEVENT13, event); break;
1039  case 14: __RV_CSR_WRITE(CSR_MHPMEVENT14, event); break;
1040  case 15: __RV_CSR_WRITE(CSR_MHPMEVENT15, event); break;
1041  case 16: __RV_CSR_WRITE(CSR_MHPMEVENT16, event); break;
1042  case 17: __RV_CSR_WRITE(CSR_MHPMEVENT17, event); break;
1043  case 18: __RV_CSR_WRITE(CSR_MHPMEVENT18, event); break;
1044  case 19: __RV_CSR_WRITE(CSR_MHPMEVENT19, event); break;
1045  case 20: __RV_CSR_WRITE(CSR_MHPMEVENT20, event); break;
1046  case 21: __RV_CSR_WRITE(CSR_MHPMEVENT21, event); break;
1047  case 22: __RV_CSR_WRITE(CSR_MHPMEVENT22, event); break;
1048  case 23: __RV_CSR_WRITE(CSR_MHPMEVENT23, event); break;
1049  case 24: __RV_CSR_WRITE(CSR_MHPMEVENT24, event); break;
1050  case 25: __RV_CSR_WRITE(CSR_MHPMEVENT25, event); break;
1051  case 26: __RV_CSR_WRITE(CSR_MHPMEVENT26, event); break;
1052  case 27: __RV_CSR_WRITE(CSR_MHPMEVENT27, event); break;
1053  case 28: __RV_CSR_WRITE(CSR_MHPMEVENT28, event); break;
1054  case 29: __RV_CSR_WRITE(CSR_MHPMEVENT29, event); break;
1055  case 30: __RV_CSR_WRITE(CSR_MHPMEVENT30, event); break;
1056  case 31: __RV_CSR_WRITE(CSR_MHPMEVENT31, event); break;
1057  default: break;
1058  }
1059 }

References __RV_CSR_WRITE, CSR_MHPMEVENT10, CSR_MHPMEVENT11, CSR_MHPMEVENT12, CSR_MHPMEVENT13, CSR_MHPMEVENT14, CSR_MHPMEVENT15, CSR_MHPMEVENT16, CSR_MHPMEVENT17, CSR_MHPMEVENT18, CSR_MHPMEVENT19, CSR_MHPMEVENT20, CSR_MHPMEVENT21, CSR_MHPMEVENT22, CSR_MHPMEVENT23, CSR_MHPMEVENT24, CSR_MHPMEVENT25, CSR_MHPMEVENT26, CSR_MHPMEVENT27, CSR_MHPMEVENT28, CSR_MHPMEVENT29, CSR_MHPMEVENT3, CSR_MHPMEVENT30, CSR_MHPMEVENT31, CSR_MHPMEVENT4, CSR_MHPMEVENT5, CSR_MHPMEVENT6, CSR_MHPMEVENT7, CSR_MHPMEVENT8, and CSR_MHPMEVENT9.

◆ __set_medeleg()

__STATIC_FORCEINLINE void __set_medeleg ( unsigned long  mask)

Set exceptions delegation to S mode.

Set certain exceptions of supervisor mode or user mode delegated from machined mode to supervisor mode.

Remarks
Exception should trigger in supervisor mode or user mode.

Definition at line 1452 of file core_feature_base.h.

1453 {
1454  __RV_CSR_WRITE(CSR_MEDELEG, mask);
1455 }

References __RV_CSR_WRITE, and CSR_MEDELEG.

◆ __set_wfi_sleepmode()

__STATIC_FORCEINLINE void __set_wfi_sleepmode ( WFI_SleepMode_Type  mode)

Set Sleep mode of WFI.

Set the SLEEPVALUE CSR register to control the WFI Sleep mode.

Parameters
[in]modeThe sleep mode to be set

Definition at line 894 of file core_feature_base.h.

895 {
897 }

References __RV_CSR_WRITE, and CSR_SLEEPVALUE.

◆ __SH()

__STATIC_FORCEINLINE void __SH ( volatile void *  addr,
uint16_t  val 
)

Write 16bit value to address (16 bit)

Write 16 bit value.

Parameters
[in]addrAddress pointer to data
[in]valValue to set

Definition at line 1578 of file core_feature_base.h.

1579 {
1580  __ASM volatile ("sh %0, 0(%1)" : : "r" (val), "r" (addr));
1581 }

References __ASM.

◆ __SW()

__STATIC_FORCEINLINE void __SW ( volatile void *  addr,
uint32_t  val 
)

Write 32bit value to address (32 bit)

Write 32 bit value.

Parameters
[in]addrAddress pointer to data
[in]valValue to set

Definition at line 1589 of file core_feature_base.h.

1590 {
1591  __ASM volatile ("sw %0, 0(%1)" : : "r" (val), "r" (addr));
1592 }

References __ASM.

Referenced by SysTimer_ClearHartSWIRQ(), SysTimer_ClearIPI(), SysTimer_SendIPI(), SysTimer_SetHartCompareValue(), SysTimer_SetHartMsipValue(), SysTimer_SetHartSWIRQ(), and SysTimer_SetLoadValue().

◆ __TXEVT()

__STATIC_FORCEINLINE void __TXEVT ( void  )

Send TX Event.

Set the CSR TXEVT to control send a TX Event. The Core will output signal tx_evt as output event signal.

Definition at line 905 of file core_feature_base.h.

906 {
907  __RV_CSR_SET(CSR_TXEVT, 0x1);
908 }

References __RV_CSR_SET, and CSR_TXEVT.

◆ __WFE()

__STATIC_FORCEINLINE void __WFE ( void  )

Wait For Event.

Wait For Event is executed using CSR_WFE.WFE=1 and WFI instruction. It will suspends execution until event, NMI or Debug happened. When Core is waked up, Core will resume previous execution

Definition at line 849 of file core_feature_base.h.

850 {
852  __ASM volatile("wfi");
854 }

References __ASM, __RV_CSR_CLEAR, __RV_CSR_SET, CSR_WFE, and WFE_WFE.

◆ __WFI()

__STATIC_FORCEINLINE void __WFI ( void  )

Wait For Interrupt.

Wait For Interrupt is is executed using CSR_WFE.WFE=0 and WFI instruction. It will suspends execution until interrupt, NMI or Debug happened. When Core is waked up by interrupt, if

  1. mstatus.MIE == 1(interrupt enabled), Core will enter ISR code
  2. mstatus.MIE == 0(interrupt disabled), Core will resume previous execution

Definition at line 836 of file core_feature_base.h.

837 {
839  __ASM volatile("wfi");
840 }

References __ASM, __RV_CSR_CLEAR, CSR_WFE, and WFE_WFE.

CSR_MHPMCOUNTER9
#define CSR_MHPMCOUNTER9
Definition: riscv_encoding.h:688
MCOUNTINHIBIT_CY
#define MCOUNTINHIBIT_CY
Definition: riscv_encoding.h:200
CSR_MHPMCOUNTER15H
#define CSR_MHPMCOUNTER15H
Definition: riscv_encoding.h:835
CSR_MHPMCOUNTER7
#define CSR_MHPMCOUNTER7
Definition: riscv_encoding.h:686
CSR_TXEVT
#define CSR_TXEVT
Definition: riscv_encoding.h:960
CSR_MHPMCOUNTER16
#define CSR_MHPMCOUNTER16
Definition: riscv_encoding.h:695
CSR_MHPMEVENT26
#define CSR_MHPMEVENT26
Definition: riscv_encoding.h:734
CSR_MHPMCOUNTER22H
#define CSR_MHPMCOUNTER22H
Definition: riscv_encoding.h:842
CSR_MHPMCOUNTER20H
#define CSR_MHPMCOUNTER20H
Definition: riscv_encoding.h:840
CSR_MHPMCOUNTER23H
#define CSR_MHPMCOUNTER23H
Definition: riscv_encoding.h:843
CSR_MHPMEVENT19
#define CSR_MHPMEVENT19
Definition: riscv_encoding.h:727
CSR_MHPMCOUNTER14
#define CSR_MHPMCOUNTER14
Definition: riscv_encoding.h:693
CSR_MHPMCOUNTER17H
#define CSR_MHPMCOUNTER17H
Definition: riscv_encoding.h:837
CSR_MHPMCOUNTER21
#define CSR_MHPMCOUNTER21
Definition: riscv_encoding.h:700
__RV_CSR_CLEAR
#define __RV_CSR_CLEAR(csr, val)
CSR operation Macro for csrc instruction.
Definition: core_feature_base.h:573
CSR_MHPMEVENT11
#define CSR_MHPMEVENT11
Definition: riscv_encoding.h:719
CSR_MEDELEG
#define CSR_MEDELEG
Definition: riscv_encoding.h:568
CSR_MHPMEVENT6
#define CSR_MHPMEVENT6
Definition: riscv_encoding.h:714
CSR_MHPMCOUNTER22
#define CSR_MHPMCOUNTER22
Definition: riscv_encoding.h:701
CSR_MHPMCOUNTER31
#define CSR_MHPMCOUNTER31
Definition: riscv_encoding.h:710
CSR_MHPMEVENT17
#define CSR_MHPMEVENT17
Definition: riscv_encoding.h:725
CSR_MHPMCOUNTER27H
#define CSR_MHPMCOUNTER27H
Definition: riscv_encoding.h:847
CSR_MHPMCOUNTER13
#define CSR_MHPMCOUNTER13
Definition: riscv_encoding.h:692
CSR_MHPMEVENT9
#define CSR_MHPMEVENT9
Definition: riscv_encoding.h:717
CSR_MHPMCOUNTER10H
#define CSR_MHPMCOUNTER10H
Definition: riscv_encoding.h:830
CSR_MHPMCOUNTER14H
#define CSR_MHPMCOUNTER14H
Definition: riscv_encoding.h:834
CSR_MHPMCOUNTER13H
#define CSR_MHPMCOUNTER13H
Definition: riscv_encoding.h:833
CSR_MHPMCOUNTER20
#define CSR_MHPMCOUNTER20
Definition: riscv_encoding.h:699
CSR_MHPMCOUNTER4
#define CSR_MHPMCOUNTER4
Definition: riscv_encoding.h:683
CSR_MHPMCOUNTER8H
#define CSR_MHPMCOUNTER8H
Definition: riscv_encoding.h:828
CSR_MHPMCOUNTER8
#define CSR_MHPMCOUNTER8
Definition: riscv_encoding.h:687
__RV_CSR_WRITE
#define __RV_CSR_WRITE(csr, val)
CSR operation Macro for csrw instruction.
Definition: core_feature_base.h:499
CSR_MHPMEVENT31
#define CSR_MHPMEVENT31
Definition: riscv_encoding.h:739
CSR_MHPMEVENT14
#define CSR_MHPMEVENT14
Definition: riscv_encoding.h:722
CSR_MHPMEVENT3
#define CSR_MHPMEVENT3
Definition: riscv_encoding.h:711
CSR_MHPMCOUNTER17
#define CSR_MHPMCOUNTER17
Definition: riscv_encoding.h:696
CSR_MHPMEVENT12
#define CSR_MHPMEVENT12
Definition: riscv_encoding.h:720
CSR_MHPMCOUNTER19H
#define CSR_MHPMCOUNTER19H
Definition: riscv_encoding.h:839
CSR_MHPMCOUNTER18H
#define CSR_MHPMCOUNTER18H
Definition: riscv_encoding.h:838
CSR_MHPMEVENT29
#define CSR_MHPMEVENT29
Definition: riscv_encoding.h:737
CSR_MHPMCOUNTER24
#define CSR_MHPMCOUNTER24
Definition: riscv_encoding.h:703
CSR_MHPMEVENT15
#define CSR_MHPMEVENT15
Definition: riscv_encoding.h:723
CSR_MHPMEVENT13
#define CSR_MHPMEVENT13
Definition: riscv_encoding.h:721
CSR_MHPMEVENT27
#define CSR_MHPMEVENT27
Definition: riscv_encoding.h:735
WFE_WFE
#define WFE_WFE
Definition: riscv_encoding.h:195
CSR_MHPMEVENT25
#define CSR_MHPMEVENT25
Definition: riscv_encoding.h:733
CSR_MHPMCOUNTER30H
#define CSR_MHPMCOUNTER30H
Definition: riscv_encoding.h:850
CSR_MHPMEVENT22
#define CSR_MHPMEVENT22
Definition: riscv_encoding.h:730
WFI_SHALLOW_SLEEP
@ WFI_SHALLOW_SLEEP
Shallow sleep mode, the core_clk will poweroff.
Definition: core_feature_base.h:883
CSR_MHPMEVENT7
#define CSR_MHPMEVENT7
Definition: riscv_encoding.h:715
CSR_MHPMEVENT20
#define CSR_MHPMEVENT20
Definition: riscv_encoding.h:728
CSR_MHPMEVENT5
#define CSR_MHPMEVENT5
Definition: riscv_encoding.h:713
__get_rv_cycle
__STATIC_FORCEINLINE uint64_t __get_rv_cycle(void)
Read whole 64 bits value of mcycle counter.
Definition: core_feature_base.h:677
CSR_MHPMCOUNTER16H
#define CSR_MHPMCOUNTER16H
Definition: riscv_encoding.h:836
CSR_MHPMEVENT16
#define CSR_MHPMEVENT16
Definition: riscv_encoding.h:724
CSR_MHPMCOUNTER4H
#define CSR_MHPMCOUNTER4H
Definition: riscv_encoding.h:824
CSR_MHPMCOUNTER12
#define CSR_MHPMCOUNTER12
Definition: riscv_encoding.h:691
CSR_MHPMCOUNTER28H
#define CSR_MHPMCOUNTER28H
Definition: riscv_encoding.h:848
CSR_MHPMCOUNTER25
#define CSR_MHPMCOUNTER25
Definition: riscv_encoding.h:704
CSR_MHPMEVENT10
#define CSR_MHPMEVENT10
Definition: riscv_encoding.h:718
CSR_MHPMEVENT30
#define CSR_MHPMEVENT30
Definition: riscv_encoding.h:738
CSR_MHPMCOUNTER9H
#define CSR_MHPMCOUNTER9H
Definition: riscv_encoding.h:829
CSR_MHPMCOUNTER11
#define CSR_MHPMCOUNTER11
Definition: riscv_encoding.h:690
MCOUNTINHIBIT_IR
#define MCOUNTINHIBIT_IR
Definition: riscv_encoding.h:199
CSR_MHPMCOUNTER7H
#define CSR_MHPMCOUNTER7H
Definition: riscv_encoding.h:827
CSR_MHPMCOUNTER27
#define CSR_MHPMCOUNTER27
Definition: riscv_encoding.h:706
CSR_MCOUNTINHIBIT
#define CSR_MCOUNTINHIBIT
Definition: riscv_encoding.h:578
CSR_MHPMCOUNTER5H
#define CSR_MHPMCOUNTER5H
Definition: riscv_encoding.h:825
CSR_MHPMCOUNTER29H
#define CSR_MHPMCOUNTER29H
Definition: riscv_encoding.h:849
CSR_MHPMCOUNTER3
#define CSR_MHPMCOUNTER3
Definition: riscv_encoding.h:682
CSR_MHPMCOUNTER12H
#define CSR_MHPMCOUNTER12H
Definition: riscv_encoding.h:832
CSR_MHPMEVENT8
#define CSR_MHPMEVENT8
Definition: riscv_encoding.h:716
CSR_SLEEPVALUE
#define CSR_SLEEPVALUE
Definition: riscv_encoding.h:959
__RV_CSR_READ
#define __RV_CSR_READ(csr)
CSR operation Macro for csrr instruction.
Definition: core_feature_base.h:481
CSR_MHPMCOUNTER24H
#define CSR_MHPMCOUNTER24H
Definition: riscv_encoding.h:844
CSR_MHPMCOUNTER5
#define CSR_MHPMCOUNTER5
Definition: riscv_encoding.h:684
CSR_MHPMCOUNTER3H
#define CSR_MHPMCOUNTER3H
Definition: riscv_encoding.h:823
CSR_MHPMCOUNTER15
#define CSR_MHPMCOUNTER15
Definition: riscv_encoding.h:694
CSR_MHPMCOUNTER6
#define CSR_MHPMCOUNTER6
Definition: riscv_encoding.h:685
CSR_MHPMCOUNTER19
#define CSR_MHPMCOUNTER19
Definition: riscv_encoding.h:698
CSR_MHPMEVENT24
#define CSR_MHPMEVENT24
Definition: riscv_encoding.h:732
CSR_MHPMCOUNTER11H
#define CSR_MHPMCOUNTER11H
Definition: riscv_encoding.h:831
CSR_MHPMCOUNTER23
#define CSR_MHPMCOUNTER23
Definition: riscv_encoding.h:702
CSR_MHPMCOUNTER26H
#define CSR_MHPMCOUNTER26H
Definition: riscv_encoding.h:846
__RV_CSR_SET
#define __RV_CSR_SET(csr, val)
CSR operation Macro for csrs instruction.
Definition: core_feature_base.h:536
CSR_MHPMCOUNTER31H
#define CSR_MHPMCOUNTER31H
Definition: riscv_encoding.h:851
CSR_MHPMCOUNTER21H
#define CSR_MHPMCOUNTER21H
Definition: riscv_encoding.h:841
CSR_MHPMEVENT18
#define CSR_MHPMEVENT18
Definition: riscv_encoding.h:726
CSR_MHPMCOUNTER28
#define CSR_MHPMCOUNTER28
Definition: riscv_encoding.h:707
CSR_MHPMCOUNTER29
#define CSR_MHPMCOUNTER29
Definition: riscv_encoding.h:708
CSR_MHPMEVENT28
#define CSR_MHPMEVENT28
Definition: riscv_encoding.h:736
CSR_MHPMCOUNTER30
#define CSR_MHPMCOUNTER30
Definition: riscv_encoding.h:709
CSR_MHPMEVENT4
#define CSR_MHPMEVENT4
Definition: riscv_encoding.h:712
CSR_MHPMCOUNTER25H
#define CSR_MHPMCOUNTER25H
Definition: riscv_encoding.h:845
__ASM
#define __ASM
Pass information from the compiler to the assembler.
Definition: nmsis_gcc.h:55
__get_rv_instret
__STATIC_FORCEINLINE uint64_t __get_rv_instret(void)
Read whole 64 bits value of machine instruction-retired counter.
Definition: core_feature_base.h:704
WFI_DEEP_SLEEP
@ WFI_DEEP_SLEEP
Deep sleep mode, the core_clk and core_ano_clk will poweroff.
Definition: core_feature_base.h:884
CSR_MHPMCOUNTER10
#define CSR_MHPMCOUNTER10
Definition: riscv_encoding.h:689
CSR_MHPMEVENT23
#define CSR_MHPMEVENT23
Definition: riscv_encoding.h:731
CSR_MHPMCOUNTER18
#define CSR_MHPMCOUNTER18
Definition: riscv_encoding.h:697
CSR_WFE
#define CSR_WFE
Definition: riscv_encoding.h:961
CSR_MHPMCOUNTER6H
#define CSR_MHPMCOUNTER6H
Definition: riscv_encoding.h:826
CSR_MHPMCOUNTER26
#define CSR_MHPMCOUNTER26
Definition: riscv_encoding.h:705
CSR_MHPMEVENT21
#define CSR_MHPMEVENT21
Definition: riscv_encoding.h:729