NMSIS-Core  Version 1.4.0
NMSIS-Core support for Nuclei processor-based devices
Intrinsic Functions for CPU Intructions

Functions that generate RISC-V CPU instructions. More...

Macros

#define __FENCE(p, s)   __ASM volatile ("fence " #p "," #s : : : "memory")
 Execute fence instruction, p -> pred, s -> succ. More...
 
#define __RWMB()   __FENCE(iorw,iorw)
 Read & Write Memory barrier. More...
 
#define __RMB()   __FENCE(ir,ir)
 Read Memory barrier. More...
 
#define __WMB()   __FENCE(ow,ow)
 Write Memory barrier. More...
 
#define __SMP_RWMB()   __FENCE(rw,rw)
 SMP Read & Write Memory barrier. More...
 
#define __SMP_RMB()   __FENCE(r,r)
 SMP Read Memory barrier. More...
 
#define __SMP_WMB()   __FENCE(w,w)
 SMP Write Memory barrier. More...
 
#define __CPU_RELAX()   __ASM volatile ("" : : : "memory")
 CPU relax for busy loop. More...
 

Enumerations

enum  WFI_SleepMode_Type {
  WFI_SHALLOW_SLEEP = 0 ,
  WFI_DEEP_SLEEP = 1
}
 WFI Sleep Mode enumeration. More...
 

Functions

__STATIC_FORCEINLINE void __NOP (void)
 NOP Instruction. More...
 
__STATIC_FORCEINLINE void __WFI (void)
 Wait For Interrupt. More...
 
__STATIC_FORCEINLINE void __WFE (void)
 Wait For Event. More...
 
__STATIC_FORCEINLINE void __EBREAK (void)
 Breakpoint Instruction. More...
 
__STATIC_FORCEINLINE void __ECALL (void)
 Environment Call Instruction. More...
 
__STATIC_FORCEINLINE void __set_wfi_sleepmode (WFI_SleepMode_Type mode)
 Set Sleep mode of WFI. More...
 
__STATIC_FORCEINLINE void __TXEVT (void)
 Send TX Event. More...
 
__STATIC_FORCEINLINE void __enable_mcycle_counter (void)
 Enable MCYCLE counter. More...
 
__STATIC_FORCEINLINE void __disable_mcycle_counter (void)
 Disable MCYCLE counter. More...
 
__STATIC_FORCEINLINE void __enable_minstret_counter (void)
 Enable MINSTRET counter. More...
 
__STATIC_FORCEINLINE void __disable_minstret_counter (void)
 Disable MINSTRET counter. More...
 
__STATIC_FORCEINLINE void __enable_mhpm_counter (unsigned long idx)
 Enable selected hardware performance monitor counter. More...
 
__STATIC_FORCEINLINE void __disable_mhpm_counter (unsigned long idx)
 Disable selected hardware performance monitor counter. More...
 
__STATIC_FORCEINLINE void __enable_mhpm_counters (unsigned long mask)
 Enable hardware performance counters with mask. More...
 
__STATIC_FORCEINLINE void __disable_mhpm_counters (unsigned long mask)
 Disable hardware performance counters with mask. More...
 
__STATIC_FORCEINLINE void __enable_all_counter (void)
 Enable all MCYCLE & MINSTRET & MHPMCOUNTER counter. More...
 
__STATIC_FORCEINLINE void __disable_all_counter (void)
 Disable all MCYCLE & MINSTRET & MHPMCOUNTER counter. More...
 
__STATIC_FORCEINLINE void __set_hpm_event (unsigned long idx, unsigned long event)
 Set event for selected high performance monitor event. More...
 
__STATIC_FORCEINLINE unsigned long __get_hpm_event (unsigned long idx)
 Get event for selected high performance monitor event. More...
 
__STATIC_FORCEINLINE void __set_hpm_counter (unsigned long idx, uint64_t value)
 Set value for selected high performance monitor counter. More...
 
__STATIC_FORCEINLINE uint64_t __get_hpm_counter (unsigned long idx)
 Get value of selected high performance monitor counter. More...
 
__STATIC_FORCEINLINE unsigned long __read_hpm_counter (unsigned long idx)
 Get value of selected high performance monitor counter. More...
 
__STATIC_FORCEINLINE void __set_medeleg (unsigned long mask)
 Set exceptions delegation to S mode. More...
 
__STATIC_FORCEINLINE void __set_mideleg (unsigned long mask)
 Set interrupt delegation to S mode. More...
 
__STATIC_FORCEINLINE void __FENCE_I (void)
 Fence.i Instruction. More...
 
__STATIC_FORCEINLINE uint8_t __LB (volatile void *addr)
 Load 8bit value from address (8 bit) More...
 
__STATIC_FORCEINLINE uint16_t __LH (volatile void *addr)
 Load 16bit value from address (16 bit) More...
 
__STATIC_FORCEINLINE uint32_t __LW (volatile void *addr)
 Load 32bit value from address (32 bit) More...
 
__STATIC_FORCEINLINE void __SB (volatile void *addr, uint8_t val)
 Write 8bit value to address (8 bit) More...
 
__STATIC_FORCEINLINE void __SH (volatile void *addr, uint16_t val)
 Write 16bit value to address (16 bit) More...
 
__STATIC_FORCEINLINE void __SW (volatile void *addr, uint32_t val)
 Write 32bit value to address (32 bit) More...
 
__STATIC_FORCEINLINE uint32_t __CAS_W (volatile uint32_t *addr, uint32_t oldval, uint32_t newval)
 Compare and Swap 32bit value using LR and SC. More...
 
__STATIC_FORCEINLINE uint32_t __AMOSWAP_W (volatile uint32_t *addr, uint32_t newval)
 Atomic Swap 32bit value into memory. More...
 
__STATIC_FORCEINLINE int32_t __AMOADD_W (volatile int32_t *addr, int32_t value)
 Atomic Add with 32bit value. More...
 
__STATIC_FORCEINLINE int32_t __AMOAND_W (volatile int32_t *addr, int32_t value)
 Atomic And with 32bit value. More...
 
__STATIC_FORCEINLINE int32_t __AMOOR_W (volatile int32_t *addr, int32_t value)
 Atomic OR with 32bit value. More...
 
__STATIC_FORCEINLINE int32_t __AMOXOR_W (volatile int32_t *addr, int32_t value)
 Atomic XOR with 32bit value. More...
 
__STATIC_FORCEINLINE uint32_t __AMOMAXU_W (volatile uint32_t *addr, uint32_t value)
 Atomic unsigned MAX with 32bit value. More...
 
__STATIC_FORCEINLINE int32_t __AMOMAX_W (volatile int32_t *addr, int32_t value)
 Atomic signed MAX with 32bit value. More...
 
__STATIC_FORCEINLINE uint32_t __AMOMINU_W (volatile uint32_t *addr, uint32_t value)
 Atomic unsigned MIN with 32bit value. More...
 
__STATIC_FORCEINLINE int32_t __AMOMIN_W (volatile int32_t *addr, int32_t value)
 Atomic signed MIN with 32bit value. More...
 

Detailed Description

Functions that generate RISC-V CPU instructions.

The following functions generate specified RISC-V instructions that cannot be directly accessed by compiler.

Macro Definition Documentation

◆ __CPU_RELAX

#define __CPU_RELAX ( )    __ASM volatile ("" : : : "memory")

CPU relax for busy loop.

Definition at line 2064 of file core_feature_base.h.

◆ __FENCE

#define __FENCE (   p,
 
)    __ASM volatile ("fence " #p "," #s : : : "memory")

Execute fence instruction, p -> pred, s -> succ.

the FENCE instruction ensures that all memory accesses from instructions preceding the fence in program order (the predecessor set) appear earlier in the global memory order than memory accesses from instructions appearing after the fence in program order (the successor set). For details, please refer to The RISC-V Instruction Set Manual

Parameters
ppredecessor set, such as iorw, rw, r, w
ssuccessor set, such as iorw, rw, r, w

Definition at line 2032 of file core_feature_base.h.

◆ __RMB

#define __RMB ( )    __FENCE(ir,ir)

Read Memory barrier.

Definition at line 2049 of file core_feature_base.h.

◆ __RWMB

#define __RWMB ( )    __FENCE(iorw,iorw)

Read & Write Memory barrier.

Definition at line 2046 of file core_feature_base.h.

◆ __SMP_RMB

#define __SMP_RMB ( )    __FENCE(r,r)

SMP Read Memory barrier.

Definition at line 2058 of file core_feature_base.h.

◆ __SMP_RWMB

#define __SMP_RWMB ( )    __FENCE(rw,rw)

SMP Read & Write Memory barrier.

Definition at line 2055 of file core_feature_base.h.

◆ __SMP_WMB

#define __SMP_WMB ( )    __FENCE(w,w)

SMP Write Memory barrier.

Definition at line 2061 of file core_feature_base.h.

◆ __WMB

#define __WMB ( )    __FENCE(ow,ow)

Write Memory barrier.

Definition at line 2052 of file core_feature_base.h.

Enumeration Type Documentation

◆ WFI_SleepMode_Type

WFI Sleep Mode enumeration.

Enumerator
WFI_SHALLOW_SLEEP 

Shallow sleep mode, the core_clk will poweroff.

WFI_DEEP_SLEEP 

Deep sleep mode, the core_clk and core_ano_clk will poweroff.

Definition at line 1390 of file core_feature_base.h.

1390  {
1391  WFI_SHALLOW_SLEEP = 0,
1392  WFI_DEEP_SLEEP = 1
WFI_SleepMode_Type
WFI Sleep Mode enumeration.
@ WFI_DEEP_SLEEP
Deep sleep mode, the core_clk and core_ano_clk will poweroff.
@ WFI_SHALLOW_SLEEP
Shallow sleep mode, the core_clk will poweroff.

Function Documentation

◆ __AMOADD_W()

__STATIC_FORCEINLINE int32_t __AMOADD_W ( volatile int32_t *  addr,
int32_t  value 
)

Atomic Add with 32bit value.

Atomically ADD 32bit value with value in memory using amoadd.d.

Parameters
[in]addrAddress pointer to data, address need to be 4byte aligned
[in]valuevalue to be ADDed
Returns
return memory value + add value

Definition at line 2223 of file core_feature_base.h.

2224 {
2225  int32_t result;
2226 
2227  __ASM volatile ("amoadd.w %0, %2, %1" : \
2228  "=r"(result), "+A"(*addr) : "r"(value) : "memory");
2229  return *addr;
2230 }
#define __ASM
Pass information from the compiler to the assembler.
Definition: nmsis_gcc.h:55

References __ASM.

◆ __AMOAND_W()

__STATIC_FORCEINLINE int32_t __AMOAND_W ( volatile int32_t *  addr,
int32_t  value 
)

Atomic And with 32bit value.

Atomically AND 32bit value with value in memory using amoand.d.

Parameters
[in]addrAddress pointer to data, address need to be 4byte aligned
[in]valuevalue to be ANDed
Returns
return memory value & and value

Definition at line 2239 of file core_feature_base.h.

2240 {
2241  int32_t result;
2242 
2243  __ASM volatile ("amoand.w %0, %2, %1" : \
2244  "=r"(result), "+A"(*addr) : "r"(value) : "memory");
2245  return *addr;
2246 }

References __ASM.

◆ __AMOMAX_W()

__STATIC_FORCEINLINE int32_t __AMOMAX_W ( volatile int32_t *  addr,
int32_t  value 
)

Atomic signed MAX with 32bit value.

Atomically signed max compare 32bit value with value in memory using amomax.d.

Parameters
[in]addrAddress pointer to data, address need to be 4byte aligned
[in]valuevalue to be compared
Returns
the bigger value

Definition at line 2303 of file core_feature_base.h.

2304 {
2305  int32_t result;
2306 
2307  __ASM volatile ("amomax.w %0, %2, %1" : \
2308  "=r"(result), "+A"(*addr) : "r"(value) : "memory");
2309  return *addr;
2310 }

References __ASM.

◆ __AMOMAXU_W()

__STATIC_FORCEINLINE uint32_t __AMOMAXU_W ( volatile uint32_t *  addr,
uint32_t  value 
)

Atomic unsigned MAX with 32bit value.

Atomically unsigned max compare 32bit value with value in memory using amomaxu.d.

Parameters
[in]addrAddress pointer to data, address need to be 4byte aligned
[in]valuevalue to be compared
Returns
return the bigger value

Definition at line 2287 of file core_feature_base.h.

2288 {
2289  uint32_t result;
2290 
2291  __ASM volatile ("amomaxu.w %0, %2, %1" : \
2292  "=r"(result), "+A"(*addr) : "r"(value) : "memory");
2293  return *addr;
2294 }

References __ASM.

◆ __AMOMIN_W()

__STATIC_FORCEINLINE int32_t __AMOMIN_W ( volatile int32_t *  addr,
int32_t  value 
)

Atomic signed MIN with 32bit value.

Atomically signed min compare 32bit value with value in memory using amomin.d.

Parameters
[in]addrAddress pointer to data, address need to be 4byte aligned
[in]valuevalue to be compared
Returns
the smaller value

Definition at line 2335 of file core_feature_base.h.

2336 {
2337  int32_t result;
2338 
2339  __ASM volatile ("amomin.w %0, %2, %1" : \
2340  "=r"(result), "+A"(*addr) : "r"(value) : "memory");
2341  return *addr;
2342 }

References __ASM.

◆ __AMOMINU_W()

__STATIC_FORCEINLINE uint32_t __AMOMINU_W ( volatile uint32_t *  addr,
uint32_t  value 
)

Atomic unsigned MIN with 32bit value.

Atomically unsigned min compare 32bit value with value in memory using amominu.d.

Parameters
[in]addrAddress pointer to data, address need to be 4byte aligned
[in]valuevalue to be compared
Returns
the smaller value

Definition at line 2319 of file core_feature_base.h.

2320 {
2321  uint32_t result;
2322 
2323  __ASM volatile ("amominu.w %0, %2, %1" : \
2324  "=r"(result), "+A"(*addr) : "r"(value) : "memory");
2325  return *addr;
2326 }

References __ASM.

◆ __AMOOR_W()

__STATIC_FORCEINLINE int32_t __AMOOR_W ( volatile int32_t *  addr,
int32_t  value 
)

Atomic OR with 32bit value.

Atomically OR 32bit value with value in memory using amoor.d.

Parameters
[in]addrAddress pointer to data, address need to be 4byte aligned
[in]valuevalue to be ORed
Returns
return memory value | and value

Definition at line 2255 of file core_feature_base.h.

2256 {
2257  int32_t result;
2258 
2259  __ASM volatile ("amoor.w %0, %2, %1" : \
2260  "=r"(result), "+A"(*addr) : "r"(value) : "memory");
2261  return *addr;
2262 }

References __ASM.

◆ __AMOSWAP_W()

__STATIC_FORCEINLINE uint32_t __AMOSWAP_W ( volatile uint32_t *  addr,
uint32_t  newval 
)

Atomic Swap 32bit value into memory.

Atomically swap new 32bit value into memory using amoswap.d.

Parameters
[in]addrAddress pointer to data, address need to be 4byte aligned
[in]newvalNew value to be stored into the address
Returns
return the original value in memory

Definition at line 2207 of file core_feature_base.h.

2208 {
2209  uint32_t result;
2210 
2211  __ASM volatile ("amoswap.w %0, %2, %1" : \
2212  "=r"(result), "+A"(*addr) : "r"(newval) : "memory");
2213  return result;
2214 }

References __ASM.

◆ __AMOXOR_W()

__STATIC_FORCEINLINE int32_t __AMOXOR_W ( volatile int32_t *  addr,
int32_t  value 
)

Atomic XOR with 32bit value.

Atomically XOR 32bit value with value in memory using amoxor.d.

Parameters
[in]addrAddress pointer to data, address need to be 4byte aligned
[in]valuevalue to be XORed
Returns
return memory value ^ and value

Definition at line 2271 of file core_feature_base.h.

2272 {
2273  int32_t result;
2274 
2275  __ASM volatile ("amoxor.w %0, %2, %1" : \
2276  "=r"(result), "+A"(*addr) : "r"(value) : "memory");
2277  return *addr;
2278 }

References __ASM.

◆ __CAS_W()

__STATIC_FORCEINLINE uint32_t __CAS_W ( volatile uint32_t *  addr,
uint32_t  oldval,
uint32_t  newval 
)

Compare and Swap 32bit value using LR and SC.

Compare old value with memory, if identical, store new value in memory. Return the initial value in memory. Success is indicated by comparing return value with OLD. memory address, return 0 if successful, otherwise return !0

Parameters
[in]addrAddress pointer to data, address need to be 4byte aligned
[in]oldvalOld value of the data in address
[in]newvalNew value to be stored into the address
Returns
return the initial value in memory

Definition at line 2183 of file core_feature_base.h.

2184 {
2185  uint32_t result;
2186  uint32_t rc;
2187 
2188  __ASM volatile ( \
2189  "0: lr.w %0, %2 \n" \
2190  " bne %0, %z3, 1f \n" \
2191  " sc.w %1, %z4, %2 \n" \
2192  " bnez %1, 0b \n" \
2193  "1:\n" \
2194  : "=&r"(result), "=&r"(rc), "+A"(*addr) \
2195  : "r"(oldval), "r"(newval) \
2196  : "memory");
2197  return result;
2198 }

References __ASM.

◆ __disable_all_counter()

__STATIC_FORCEINLINE void __disable_all_counter ( void  )

Disable all MCYCLE & MINSTRET & MHPMCOUNTER counter.

Set all to one to disable all counters, such as cycle, instret, high performance monitor counters

Definition at line 1521 of file core_feature_base.h.

1522 {
1523  __RV_CSR_SET(CSR_MCOUNTINHIBIT, 0xFFFFFFFF);
1524 }
#define __RV_CSR_SET(csr, val)
CSR operation Macro for csrs instruction.
#define CSR_MCOUNTINHIBIT

References __RV_CSR_SET, and CSR_MCOUNTINHIBIT.

◆ __disable_mcycle_counter()

__STATIC_FORCEINLINE void __disable_mcycle_counter ( void  )

Disable MCYCLE counter.

Set the CY bit of MCOUNTINHIBIT to 1 to disable MCYCLE Counter

Definition at line 1433 of file core_feature_base.h.

1434 {
1436 }
#define MCOUNTINHIBIT_CY

References __RV_CSR_SET, CSR_MCOUNTINHIBIT, and MCOUNTINHIBIT_CY.

◆ __disable_mhpm_counter()

__STATIC_FORCEINLINE void __disable_mhpm_counter ( unsigned long  idx)

Disable selected hardware performance monitor counter.

Parameters
[in]idxthe index of the hardware performance monitor counter

Disable selected hardware performance monitor counter mhpmcounterx.

Definition at line 1475 of file core_feature_base.h.

1476 {
1477  __RV_CSR_SET(CSR_MCOUNTINHIBIT, (1UL << idx));
1478 }

References __RV_CSR_SET, and CSR_MCOUNTINHIBIT.

◆ __disable_mhpm_counters()

__STATIC_FORCEINLINE void __disable_mhpm_counters ( unsigned long  mask)

Disable hardware performance counters with mask.

Parameters
[in]maskmask of selected hardware performance monitor counters

Disable mhpmcounterx with mask, only the masked ones will be disabled. mhpmcounter3-mhpmcount31 are for high performance monitor counters.

Definition at line 1499 of file core_feature_base.h.

1500 {
1502 }

References __RV_CSR_SET, and CSR_MCOUNTINHIBIT.

◆ __disable_minstret_counter()

__STATIC_FORCEINLINE void __disable_minstret_counter ( void  )

Disable MINSTRET counter.

Set the IR bit of MCOUNTINHIBIT to 1 to disable MINSTRET Counter

Definition at line 1453 of file core_feature_base.h.

1454 {
1456 }
#define MCOUNTINHIBIT_IR

References __RV_CSR_SET, CSR_MCOUNTINHIBIT, and MCOUNTINHIBIT_IR.

◆ __EBREAK()

__STATIC_FORCEINLINE void __EBREAK ( void  )

Breakpoint Instruction.

Causes the processor to enter Debug state. Debug tools can use this to investigate system state when the instruction at a particular address is reached.

Definition at line 1371 of file core_feature_base.h.

1372 {
1373  __ASM volatile("ebreak");
1374 }

References __ASM.

◆ __ECALL()

__STATIC_FORCEINLINE void __ECALL ( void  )

Environment Call Instruction.

The ECALL instruction is used to make a service request to the execution environment.

Definition at line 1382 of file core_feature_base.h.

1383 {
1384  __ASM volatile("ecall");
1385 }

References __ASM.

◆ __enable_all_counter()

__STATIC_FORCEINLINE void __enable_all_counter ( void  )

Enable all MCYCLE & MINSTRET & MHPMCOUNTER counter.

Clear all to zero to enable all counters, such as cycle, instret, high performance monitor counters

Definition at line 1510 of file core_feature_base.h.

1511 {
1512  __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, 0xFFFFFFFF);
1513 }
#define __RV_CSR_CLEAR(csr, val)
CSR operation Macro for csrc instruction.

References __RV_CSR_CLEAR, and CSR_MCOUNTINHIBIT.

Referenced by __prepare_bench_env().

◆ __enable_mcycle_counter()

__STATIC_FORCEINLINE void __enable_mcycle_counter ( void  )

Enable MCYCLE counter.

Clear the CY bit of MCOUNTINHIBIT to 0 to enable MCYCLE Counter

Definition at line 1423 of file core_feature_base.h.

References __RV_CSR_CLEAR, CSR_MCOUNTINHIBIT, and MCOUNTINHIBIT_CY.

◆ __enable_mhpm_counter()

__STATIC_FORCEINLINE void __enable_mhpm_counter ( unsigned long  idx)

Enable selected hardware performance monitor counter.

Parameters
[in]idxthe index of the hardware performance monitor counter

enable selected hardware performance monitor counter mhpmcounterx.

Definition at line 1464 of file core_feature_base.h.

1465 {
1466  __RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, (1UL << idx));
1467 }

References __RV_CSR_CLEAR, and CSR_MCOUNTINHIBIT.

◆ __enable_mhpm_counters()

__STATIC_FORCEINLINE void __enable_mhpm_counters ( unsigned long  mask)

Enable hardware performance counters with mask.

Parameters
[in]maskmask of selected hardware performance monitor counters

enable mhpmcounterx with mask, only the masked ones will be enabled. mhpmcounter3-mhpmcount31 are for high performance monitor counters.

Definition at line 1487 of file core_feature_base.h.

1488 {
1490 }

References __RV_CSR_CLEAR, and CSR_MCOUNTINHIBIT.

◆ __enable_minstret_counter()

__STATIC_FORCEINLINE void __enable_minstret_counter ( void  )

Enable MINSTRET counter.

Clear the IR bit of MCOUNTINHIBIT to 0 to enable MINSTRET Counter

Definition at line 1443 of file core_feature_base.h.

References __RV_CSR_CLEAR, CSR_MCOUNTINHIBIT, and MCOUNTINHIBIT_IR.

◆ __FENCE_I()

__STATIC_FORCEINLINE void __FENCE_I ( void  )

Fence.i Instruction.

The FENCE.I instruction is used to synchronize the instruction and data streams.

Definition at line 2040 of file core_feature_base.h.

2041 {
2042  __ASM volatile("fence.i");
2043 }

References __ASM.

Referenced by __ECLIC_SetVector(), __ECLIC_SetVector_S(), and _premain_init().

◆ __get_hpm_counter()

__STATIC_FORCEINLINE uint64_t __get_hpm_counter ( unsigned long  idx)

Get value of selected high performance monitor counter.

Parameters
[in]idxHPMCOUNTERx CSR index(3-31)

Get high performance monitor counter register value

Returns
HPMCOUNTERx Register value

Definition at line 1756 of file core_feature_base.h.

1757 {
1758 #if __RISCV_XLEN == 32
1759  volatile uint32_t high0, low, high;
1760  uint64_t full;
1761 
1762  switch (idx) {
1763  case 0: return __get_rv_cycle();
1764  case 2: return __get_rv_instret();
1765  case 3: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER3H);
1768  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER3); }
1769  full = (((uint64_t)high) << 32) | low; return full;
1770  case 4: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER4H);
1773  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER4); }
1774  full = (((uint64_t)high) << 32) | low; return full;
1775  case 5: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER5H);
1778  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER5); }
1779  full = (((uint64_t)high) << 32) | low; return full;
1780  case 6: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER6H);
1783  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER6); }
1784  full = (((uint64_t)high) << 32) | low; return full;
1785  case 7: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER7H);
1788  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER7); }
1789  full = (((uint64_t)high) << 32) | low; return full;
1790  case 8: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER8H);
1793  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER8); }
1794  full = (((uint64_t)high) << 32) | low; return full;
1795  case 9: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER9H);
1798  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER9); }
1799  full = (((uint64_t)high) << 32) | low; return full;
1800  case 10: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER10H);
1803  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER10); }
1804  full = (((uint64_t)high) << 32) | low; return full;
1805  case 11: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER11H);
1808  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER11); }
1809  full = (((uint64_t)high) << 32) | low; return full;
1810  case 12: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER12H);
1813  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER12); }
1814  full = (((uint64_t)high) << 32) | low; return full;
1815  case 13: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER13H);
1818  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER13); }
1819  full = (((uint64_t)high) << 32) | low; return full;
1820  case 14: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER14H);
1823  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER14); }
1824  full = (((uint64_t)high) << 32) | low; return full;
1825  case 15: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER15H);
1828  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER15); }
1829  full = (((uint64_t)high) << 32) | low; return full;
1830  case 16: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER16H);
1833  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER16); }
1834  full = (((uint64_t)high) << 32) | low; return full;
1835  case 17: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER17H);
1838  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER17); }
1839  full = (((uint64_t)high) << 32) | low; return full;
1840  case 18: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER18H);
1843  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER18); }
1844  full = (((uint64_t)high) << 32) | low; return full;
1845  case 19: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER19H);
1848  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER19); }
1849  full = (((uint64_t)high) << 32) | low; return full;
1850  case 20: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER20H);
1853  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER20); }
1854  full = (((uint64_t)high) << 32) | low; return full;
1855  case 21: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER21H);
1858  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER21); }
1859  full = (((uint64_t)high) << 32) | low; return full;
1860  case 22: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER22H);
1863  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER22); }
1864  full = (((uint64_t)high) << 32) | low; return full;
1865  case 23: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER23H);
1868  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER23); }
1869  full = (((uint64_t)high) << 32) | low; return full;
1870  case 24: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER24H);
1873  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER24); }
1874  full = (((uint64_t)high) << 32) | low; return full;
1875  case 25: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER25H);
1878  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER25); }
1879  full = (((uint64_t)high) << 32) | low; return full;
1880  case 26: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER26H);
1883  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER26); }
1884  full = (((uint64_t)high) << 32) | low; return full;
1885  case 27: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER27H);
1888  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER27); }
1889  full = (((uint64_t)high) << 32) | low; return full;
1890  case 28: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER28H);
1893  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER28); }
1894  full = (((uint64_t)high) << 32) | low; return full;
1895  case 29: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER29H);
1898  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER29); }
1899  full = (((uint64_t)high) << 32) | low; return full;
1900  case 30: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER30H);
1903  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER30); }
1904  full = (((uint64_t)high) << 32) | low; return full;
1905  case 31: high0 = __RV_CSR_READ(CSR_MHPMCOUNTER31H);
1908  if (high0 != high) { low = __RV_CSR_READ(CSR_MHPMCOUNTER31); }
1909  full = (((uint64_t)high) << 32) | low; return full;
1910 
1911 #elif __RISCV_XLEN == 64
1912  switch (idx) {
1913  case 0: return __get_rv_cycle();
1914  case 2: return __get_rv_instret();
1915  case 3: return __RV_CSR_READ(CSR_MHPMCOUNTER3);
1916  case 4: return __RV_CSR_READ(CSR_MHPMCOUNTER4);
1917  case 5: return __RV_CSR_READ(CSR_MHPMCOUNTER5);
1918  case 6: return __RV_CSR_READ(CSR_MHPMCOUNTER6);
1919  case 7: return __RV_CSR_READ(CSR_MHPMCOUNTER7);
1920  case 8: return __RV_CSR_READ(CSR_MHPMCOUNTER8);
1921  case 9: return __RV_CSR_READ(CSR_MHPMCOUNTER9);
1922  case 10: return __RV_CSR_READ(CSR_MHPMCOUNTER10);
1923  case 11: return __RV_CSR_READ(CSR_MHPMCOUNTER11);
1924  case 12: return __RV_CSR_READ(CSR_MHPMCOUNTER12);
1925  case 13: return __RV_CSR_READ(CSR_MHPMCOUNTER13);
1926  case 14: return __RV_CSR_READ(CSR_MHPMCOUNTER14);
1927  case 15: return __RV_CSR_READ(CSR_MHPMCOUNTER15);
1928  case 16: return __RV_CSR_READ(CSR_MHPMCOUNTER16);
1929  case 17: return __RV_CSR_READ(CSR_MHPMCOUNTER17);
1930  case 18: return __RV_CSR_READ(CSR_MHPMCOUNTER18);
1931  case 19: return __RV_CSR_READ(CSR_MHPMCOUNTER19);
1932  case 20: return __RV_CSR_READ(CSR_MHPMCOUNTER20);
1933  case 21: return __RV_CSR_READ(CSR_MHPMCOUNTER21);
1934  case 22: return __RV_CSR_READ(CSR_MHPMCOUNTER22);
1935  case 23: return __RV_CSR_READ(CSR_MHPMCOUNTER23);
1936  case 24: return __RV_CSR_READ(CSR_MHPMCOUNTER24);
1937  case 25: return __RV_CSR_READ(CSR_MHPMCOUNTER25);
1938  case 26: return __RV_CSR_READ(CSR_MHPMCOUNTER26);
1939  case 27: return __RV_CSR_READ(CSR_MHPMCOUNTER27);
1940  case 28: return __RV_CSR_READ(CSR_MHPMCOUNTER28);
1941  case 29: return __RV_CSR_READ(CSR_MHPMCOUNTER29);
1942  case 30: return __RV_CSR_READ(CSR_MHPMCOUNTER30);
1943  case 31: return __RV_CSR_READ(CSR_MHPMCOUNTER31);
1944 
1945 #else
1946  switch (idx) {
1947 #endif
1948  default: return 0;
1949  }
1950 }
__STATIC_FORCEINLINE uint64_t __get_rv_instret(void)
Read whole 64 bits value of machine instruction-retired counter.
__STATIC_FORCEINLINE uint64_t __get_rv_cycle(void)
Read whole 64 bits value of mcycle counter.
#define __RV_CSR_READ(csr)
CSR operation Macro for csrr instruction.
#define CSR_MHPMCOUNTER17H
#define CSR_MHPMCOUNTER16
#define CSR_MHPMCOUNTER7H
#define CSR_MHPMCOUNTER27H
#define CSR_MHPMCOUNTER25
#define CSR_MHPMCOUNTER20
#define CSR_MHPMCOUNTER28
#define CSR_MHPMCOUNTER31
#define CSR_MHPMCOUNTER18H
#define CSR_MHPMCOUNTER21H
#define CSR_MHPMCOUNTER28H
#define CSR_MHPMCOUNTER21
#define CSR_MHPMCOUNTER9H
#define CSR_MHPMCOUNTER7
#define CSR_MHPMCOUNTER29H
#define CSR_MHPMCOUNTER26
#define CSR_MHPMCOUNTER14
#define CSR_MHPMCOUNTER10H
#define CSR_MHPMCOUNTER6
#define CSR_MHPMCOUNTER5
#define CSR_MHPMCOUNTER11H
#define CSR_MHPMCOUNTER12H
#define CSR_MHPMCOUNTER25H
#define CSR_MHPMCOUNTER26H
#define CSR_MHPMCOUNTER5H
#define CSR_MHPMCOUNTER24H
#define CSR_MHPMCOUNTER8H
#define CSR_MHPMCOUNTER3H
#define CSR_MHPMCOUNTER12
#define CSR_MHPMCOUNTER20H
#define CSR_MHPMCOUNTER31H
#define CSR_MHPMCOUNTER8
#define CSR_MHPMCOUNTER9
#define CSR_MHPMCOUNTER6H
#define CSR_MHPMCOUNTER23H
#define CSR_MHPMCOUNTER17
#define CSR_MHPMCOUNTER11
#define CSR_MHPMCOUNTER15H
#define CSR_MHPMCOUNTER3
#define CSR_MHPMCOUNTER10
#define CSR_MHPMCOUNTER14H
#define CSR_MHPMCOUNTER29
#define CSR_MHPMCOUNTER4
#define CSR_MHPMCOUNTER27
#define CSR_MHPMCOUNTER18
#define CSR_MHPMCOUNTER13H
#define CSR_MHPMCOUNTER4H
#define CSR_MHPMCOUNTER23
#define CSR_MHPMCOUNTER24
#define CSR_MHPMCOUNTER15
#define CSR_MHPMCOUNTER22
#define CSR_MHPMCOUNTER13
#define CSR_MHPMCOUNTER30
#define CSR_MHPMCOUNTER22H
#define CSR_MHPMCOUNTER19H
#define CSR_MHPMCOUNTER16H
#define CSR_MHPMCOUNTER30H
#define CSR_MHPMCOUNTER19

References __get_rv_cycle(), __get_rv_instret(), __RV_CSR_READ, CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11, CSR_MHPMCOUNTER11H, CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15, CSR_MHPMCOUNTER15H, CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19, CSR_MHPMCOUNTER19H, CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23, CSR_MHPMCOUNTER23H, CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27, CSR_MHPMCOUNTER27H, CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER3, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31, CSR_MHPMCOUNTER31H, CSR_MHPMCOUNTER3H, CSR_MHPMCOUNTER4, CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7, CSR_MHPMCOUNTER7H, CSR_MHPMCOUNTER8, CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9, and CSR_MHPMCOUNTER9H.

◆ __get_hpm_event()

__STATIC_FORCEINLINE unsigned long __get_hpm_event ( unsigned long  idx)

Get event for selected high performance monitor event.

Parameters
[in]idxHPMEVENTx CSR index(3-31)
[in]eventHPMEVENTx Register value to set

Get high performance monitor event register value

Returns
HPMEVENTx Register value

Definition at line 1577 of file core_feature_base.h.

1578 {
1579  switch (idx) {
1580  case 3: return __RV_CSR_READ(CSR_MHPMEVENT3);
1581  case 4: return __RV_CSR_READ(CSR_MHPMEVENT4);
1582  case 5: return __RV_CSR_READ(CSR_MHPMEVENT5);
1583  case 6: return __RV_CSR_READ(CSR_MHPMEVENT6);
1584  case 7: return __RV_CSR_READ(CSR_MHPMEVENT7);
1585  case 8: return __RV_CSR_READ(CSR_MHPMEVENT8);
1586  case 9: return __RV_CSR_READ(CSR_MHPMEVENT9);
1587  case 10: return __RV_CSR_READ(CSR_MHPMEVENT10);
1588  case 11: return __RV_CSR_READ(CSR_MHPMEVENT11);
1589  case 12: return __RV_CSR_READ(CSR_MHPMEVENT12);
1590  case 13: return __RV_CSR_READ(CSR_MHPMEVENT13);
1591  case 14: return __RV_CSR_READ(CSR_MHPMEVENT14);
1592  case 15: return __RV_CSR_READ(CSR_MHPMEVENT15);
1593  case 16: return __RV_CSR_READ(CSR_MHPMEVENT16);
1594  case 17: return __RV_CSR_READ(CSR_MHPMEVENT17);
1595  case 18: return __RV_CSR_READ(CSR_MHPMEVENT18);
1596  case 19: return __RV_CSR_READ(CSR_MHPMEVENT19);
1597  case 20: return __RV_CSR_READ(CSR_MHPMEVENT20);
1598  case 21: return __RV_CSR_READ(CSR_MHPMEVENT21);
1599  case 22: return __RV_CSR_READ(CSR_MHPMEVENT22);
1600  case 23: return __RV_CSR_READ(CSR_MHPMEVENT23);
1601  case 24: return __RV_CSR_READ(CSR_MHPMEVENT24);
1602  case 25: return __RV_CSR_READ(CSR_MHPMEVENT25);
1603  case 26: return __RV_CSR_READ(CSR_MHPMEVENT26);
1604  case 27: return __RV_CSR_READ(CSR_MHPMEVENT27);
1605  case 28: return __RV_CSR_READ(CSR_MHPMEVENT28);
1606  case 29: return __RV_CSR_READ(CSR_MHPMEVENT29);
1607  case 30: return __RV_CSR_READ(CSR_MHPMEVENT30);
1608  case 31: return __RV_CSR_READ(CSR_MHPMEVENT31);
1609  default: return 0;
1610  }
1611 }
#define CSR_MHPMEVENT6
#define CSR_MHPMEVENT29
#define CSR_MHPMEVENT18
#define CSR_MHPMEVENT31
#define CSR_MHPMEVENT17
#define CSR_MHPMEVENT20
#define CSR_MHPMEVENT5
#define CSR_MHPMEVENT9
#define CSR_MHPMEVENT13
#define CSR_MHPMEVENT16
#define CSR_MHPMEVENT24
#define CSR_MHPMEVENT26
#define CSR_MHPMEVENT21
#define CSR_MHPMEVENT3
#define CSR_MHPMEVENT14
#define CSR_MHPMEVENT27
#define CSR_MHPMEVENT19
#define CSR_MHPMEVENT15
#define CSR_MHPMEVENT11
#define CSR_MHPMEVENT4
#define CSR_MHPMEVENT8
#define CSR_MHPMEVENT7
#define CSR_MHPMEVENT12
#define CSR_MHPMEVENT25
#define CSR_MHPMEVENT22
#define CSR_MHPMEVENT30
#define CSR_MHPMEVENT10
#define CSR_MHPMEVENT23
#define CSR_MHPMEVENT28

References __RV_CSR_READ, CSR_MHPMEVENT10, CSR_MHPMEVENT11, CSR_MHPMEVENT12, CSR_MHPMEVENT13, CSR_MHPMEVENT14, CSR_MHPMEVENT15, CSR_MHPMEVENT16, CSR_MHPMEVENT17, CSR_MHPMEVENT18, CSR_MHPMEVENT19, CSR_MHPMEVENT20, CSR_MHPMEVENT21, CSR_MHPMEVENT22, CSR_MHPMEVENT23, CSR_MHPMEVENT24, CSR_MHPMEVENT25, CSR_MHPMEVENT26, CSR_MHPMEVENT27, CSR_MHPMEVENT28, CSR_MHPMEVENT29, CSR_MHPMEVENT3, CSR_MHPMEVENT30, CSR_MHPMEVENT31, CSR_MHPMEVENT4, CSR_MHPMEVENT5, CSR_MHPMEVENT6, CSR_MHPMEVENT7, CSR_MHPMEVENT8, and CSR_MHPMEVENT9.

◆ __LB()

__STATIC_FORCEINLINE uint8_t __LB ( volatile void *  addr)

Load 8bit value from address (8 bit)

Load 8 bit value.

Parameters
[in]addrAddress pointer to data
Returns
value of type uint8_t at (*addr)

Definition at line 2074 of file core_feature_base.h.

2075 {
2076  uint8_t result;
2077 
2078  __ASM volatile ("lb %0, 0(%1)" : "=r" (result) : "r" (addr));
2079  return result;
2080 }

References __ASM.

◆ __LH()

__STATIC_FORCEINLINE uint16_t __LH ( volatile void *  addr)

Load 16bit value from address (16 bit)

Load 16 bit value.

Parameters
[in]addrAddress pointer to data
Returns
value of type uint16_t at (*addr)

Definition at line 2088 of file core_feature_base.h.

2089 {
2090  uint16_t result;
2091 
2092  __ASM volatile ("lh %0, 0(%1)" : "=r" (result) : "r" (addr));
2093  return result;
2094 }

References __ASM.

◆ __LW()

__STATIC_FORCEINLINE uint32_t __LW ( volatile void *  addr)

Load 32bit value from address (32 bit)

Load 32 bit value.

Parameters
[in]addrAddress pointer to data
Returns
value of type uint32_t at (*addr)

Definition at line 2102 of file core_feature_base.h.

2103 {
2104  uint32_t result;
2105 
2106  __ASM volatile ("lw %0, 0(%1)" : "=r" (result) : "r" (addr));
2107  return result;
2108 }

References __ASM.

Referenced by CIDU_GetBroadcastModeStatus(), CIDU_GetClaimStatus(), CIDU_GetCoreNum(), CIDU_GetIntNum(), CIDU_GetSemaphoreStatus(), CIDU_QueryCoreIntSenderMask(), CIDU_SetFirstClaimMode(), SysTimer_GetHartCompareValue(), SysTimer_GetHartMsipValue(), SysTimer_GetHartSsipValue(), and SysTimer_GetLoadValue().

◆ __NOP()

__STATIC_FORCEINLINE void __NOP ( void  )

NOP Instruction.

No Operation does nothing. This instruction can be used for code alignment purposes.

Definition at line 1330 of file core_feature_base.h.

1331 {
1332  __ASM volatile("nop");
1333 }

References __ASM.

◆ __read_hpm_counter()

__STATIC_FORCEINLINE unsigned long __read_hpm_counter ( unsigned long  idx)

Get value of selected high performance monitor counter.

Parameters
[in]idxHPMCOUNTERx CSR index(3-31)

Get high performance monitor counter register value without high 32 bits when XLEN=32

Returns
HPMCOUNTERx Register value

Definition at line 1960 of file core_feature_base.h.

1961 {
1962  switch (idx) {
1963  case 0: return __read_cycle_csr();
1964  case 2: return __read_instret_csr();
1965  case 3: return __RV_CSR_READ(CSR_MHPMCOUNTER3);
1966  case 4: return __RV_CSR_READ(CSR_MHPMCOUNTER4);
1967  case 5: return __RV_CSR_READ(CSR_MHPMCOUNTER5);
1968  case 6: return __RV_CSR_READ(CSR_MHPMCOUNTER6);
1969  case 7: return __RV_CSR_READ(CSR_MHPMCOUNTER7);
1970  case 8: return __RV_CSR_READ(CSR_MHPMCOUNTER8);
1971  case 9: return __RV_CSR_READ(CSR_MHPMCOUNTER9);
1972  case 10: return __RV_CSR_READ(CSR_MHPMCOUNTER10);
1973  case 11: return __RV_CSR_READ(CSR_MHPMCOUNTER11);
1974  case 12: return __RV_CSR_READ(CSR_MHPMCOUNTER12);
1975  case 13: return __RV_CSR_READ(CSR_MHPMCOUNTER13);
1976  case 14: return __RV_CSR_READ(CSR_MHPMCOUNTER14);
1977  case 15: return __RV_CSR_READ(CSR_MHPMCOUNTER15);
1978  case 16: return __RV_CSR_READ(CSR_MHPMCOUNTER16);
1979  case 17: return __RV_CSR_READ(CSR_MHPMCOUNTER17);
1980  case 18: return __RV_CSR_READ(CSR_MHPMCOUNTER18);
1981  case 19: return __RV_CSR_READ(CSR_MHPMCOUNTER19);
1982  case 20: return __RV_CSR_READ(CSR_MHPMCOUNTER20);
1983  case 21: return __RV_CSR_READ(CSR_MHPMCOUNTER21);
1984  case 22: return __RV_CSR_READ(CSR_MHPMCOUNTER22);
1985  case 23: return __RV_CSR_READ(CSR_MHPMCOUNTER23);
1986  case 24: return __RV_CSR_READ(CSR_MHPMCOUNTER24);
1987  case 25: return __RV_CSR_READ(CSR_MHPMCOUNTER25);
1988  case 26: return __RV_CSR_READ(CSR_MHPMCOUNTER26);
1989  case 27: return __RV_CSR_READ(CSR_MHPMCOUNTER27);
1990  case 28: return __RV_CSR_READ(CSR_MHPMCOUNTER28);
1991  case 29: return __RV_CSR_READ(CSR_MHPMCOUNTER29);
1992  case 30: return __RV_CSR_READ(CSR_MHPMCOUNTER30);
1993  case 31: return __RV_CSR_READ(CSR_MHPMCOUNTER31);
1994  default: return 0;
1995  }
1996 }
__STATIC_FORCEINLINE unsigned long __read_instret_csr()
Read the INSTRET register.
__STATIC_FORCEINLINE unsigned long __read_cycle_csr()
Read the CYCLE register.

References __read_cycle_csr(), __read_instret_csr(), __RV_CSR_READ, CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER11, CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER15, CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER19, CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER23, CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER27, CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER3, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER31, CSR_MHPMCOUNTER4, CSR_MHPMCOUNTER5, CSR_MHPMCOUNTER6, CSR_MHPMCOUNTER7, CSR_MHPMCOUNTER8, and CSR_MHPMCOUNTER9.

◆ __SB()

__STATIC_FORCEINLINE void __SB ( volatile void *  addr,
uint8_t  val 
)

Write 8bit value to address (8 bit)

Write 8 bit value.

Parameters
[in]addrAddress pointer to data
[in]valValue to set

Definition at line 2132 of file core_feature_base.h.

2133 {
2134  __ASM volatile ("sb %0, 0(%1)" : : "r" (val), "r" (addr));
2135 }

References __ASM.

◆ __set_hpm_counter()

__STATIC_FORCEINLINE void __set_hpm_counter ( unsigned long  idx,
uint64_t  value 
)

Set value for selected high performance monitor counter.

Parameters
[in]idxHPMCOUNTERx CSR index(3-31)
[in]valueHPMCOUNTERx Register value to set

Set value for high performance monitor couner register

Definition at line 1620 of file core_feature_base.h.

1621 {
1622  switch (idx) {
1623 #if __RISCV_XLEN == 32
1624  case 3: __RV_CSR_WRITE(CSR_MHPMCOUNTER3, 0); // prevent carry
1625  __RV_CSR_WRITE(CSR_MHPMCOUNTER3H, (uint32_t)(value >> 32));
1626  __RV_CSR_WRITE(CSR_MHPMCOUNTER3, (uint32_t)(value)); break;
1627  case 4: __RV_CSR_WRITE(CSR_MHPMCOUNTER4, 0); // prevent carry
1628  __RV_CSR_WRITE(CSR_MHPMCOUNTER4H, (uint32_t)(value >> 32));
1629  __RV_CSR_WRITE(CSR_MHPMCOUNTER4, (uint32_t)(value)); break;
1630  case 5: __RV_CSR_WRITE(CSR_MHPMCOUNTER5, 0); // prevent carry
1631  __RV_CSR_WRITE(CSR_MHPMCOUNTER5H, (uint32_t)(value >> 32));
1632  __RV_CSR_WRITE(CSR_MHPMCOUNTER5, (uint32_t)(value)); break;
1633  case 6: __RV_CSR_WRITE(CSR_MHPMCOUNTER6, 0); // prevent carry
1634  __RV_CSR_WRITE(CSR_MHPMCOUNTER6H, (uint32_t)(value >> 32));
1635  __RV_CSR_WRITE(CSR_MHPMCOUNTER6, (uint32_t)(value)); break;
1636  case 7: __RV_CSR_WRITE(CSR_MHPMCOUNTER7, 0); // prevent carry
1637  __RV_CSR_WRITE(CSR_MHPMCOUNTER7H, (uint32_t)(value >> 32));
1638  __RV_CSR_WRITE(CSR_MHPMCOUNTER7, (uint32_t)(value)); break;
1639  case 8: __RV_CSR_WRITE(CSR_MHPMCOUNTER8, 0); // prevent carry
1640  __RV_CSR_WRITE(CSR_MHPMCOUNTER8H, (uint32_t)(value >> 32));
1641  __RV_CSR_WRITE(CSR_MHPMCOUNTER8, (uint32_t)(value)); break;
1642  case 9: __RV_CSR_WRITE(CSR_MHPMCOUNTER9, 0); // prevent carry
1643  __RV_CSR_WRITE(CSR_MHPMCOUNTER9H, (uint32_t)(value >> 32));
1644  __RV_CSR_WRITE(CSR_MHPMCOUNTER9, (uint32_t)(value)); break;
1645  case 10: __RV_CSR_WRITE(CSR_MHPMCOUNTER10, 0); // prevent carry
1646  __RV_CSR_WRITE(CSR_MHPMCOUNTER10H, (uint32_t)(value >> 32));
1647  __RV_CSR_WRITE(CSR_MHPMCOUNTER10, (uint32_t)(value)); break;
1648  case 11: __RV_CSR_WRITE(CSR_MHPMCOUNTER11, 0); // prevent carry
1649  __RV_CSR_WRITE(CSR_MHPMCOUNTER11H, (uint32_t)(value >> 32));
1650  __RV_CSR_WRITE(CSR_MHPMCOUNTER11, (uint32_t)(value)); break;
1651  case 12: __RV_CSR_WRITE(CSR_MHPMCOUNTER12, 0); // prevent carry
1652  __RV_CSR_WRITE(CSR_MHPMCOUNTER12H, (uint32_t)(value >> 32));
1653  __RV_CSR_WRITE(CSR_MHPMCOUNTER12, (uint32_t)(value)); break;
1654  case 13: __RV_CSR_WRITE(CSR_MHPMCOUNTER13, 0); // prevent carry
1655  __RV_CSR_WRITE(CSR_MHPMCOUNTER13H, (uint32_t)(value >> 32));
1656  __RV_CSR_WRITE(CSR_MHPMCOUNTER13, (uint32_t)(value)); break;
1657  case 14: __RV_CSR_WRITE(CSR_MHPMCOUNTER14, 0); // prevent carry
1658  __RV_CSR_WRITE(CSR_MHPMCOUNTER14H, (uint32_t)(value >> 32));
1659  __RV_CSR_WRITE(CSR_MHPMCOUNTER14, (uint32_t)(value)); break;
1660  case 15: __RV_CSR_WRITE(CSR_MHPMCOUNTER15, 0); // prevent carry
1661  __RV_CSR_WRITE(CSR_MHPMCOUNTER15H, (uint32_t)(value >> 32));
1662  __RV_CSR_WRITE(CSR_MHPMCOUNTER15, (uint32_t)(value)); break;
1663  case 16: __RV_CSR_WRITE(CSR_MHPMCOUNTER16, 0); // prevent carry
1664  __RV_CSR_WRITE(CSR_MHPMCOUNTER16H, (uint32_t)(value >> 32));
1665  __RV_CSR_WRITE(CSR_MHPMCOUNTER16, (uint32_t)(value)); break;
1666  case 17: __RV_CSR_WRITE(CSR_MHPMCOUNTER17, 0); // prevent carry
1667  __RV_CSR_WRITE(CSR_MHPMCOUNTER17H, (uint32_t)(value >> 32));
1668  __RV_CSR_WRITE(CSR_MHPMCOUNTER17, (uint32_t)(value)); break;
1669  case 18: __RV_CSR_WRITE(CSR_MHPMCOUNTER18, 0); // prevent carry
1670  __RV_CSR_WRITE(CSR_MHPMCOUNTER18H, (uint32_t)(value >> 32));
1671  __RV_CSR_WRITE(CSR_MHPMCOUNTER18, (uint32_t)(value)); break;
1672  case 19: __RV_CSR_WRITE(CSR_MHPMCOUNTER19, 0); // prevent carry
1673  __RV_CSR_WRITE(CSR_MHPMCOUNTER19H, (uint32_t)(value >> 32));
1674  __RV_CSR_WRITE(CSR_MHPMCOUNTER19, (uint32_t)(value)); break;
1675  case 20: __RV_CSR_WRITE(CSR_MHPMCOUNTER20, 0); // prevent carry
1676  __RV_CSR_WRITE(CSR_MHPMCOUNTER20H, (uint32_t)(value >> 32));
1677  __RV_CSR_WRITE(CSR_MHPMCOUNTER20, (uint32_t)(value)); break;
1678  case 21: __RV_CSR_WRITE(CSR_MHPMCOUNTER21, 0); // prevent carry
1679  __RV_CSR_WRITE(CSR_MHPMCOUNTER21H, (uint32_t)(value >> 32));
1680  __RV_CSR_WRITE(CSR_MHPMCOUNTER21, (uint32_t)(value)); break;
1681  case 22: __RV_CSR_WRITE(CSR_MHPMCOUNTER22, 0); // prevent carry
1682  __RV_CSR_WRITE(CSR_MHPMCOUNTER22H, (uint32_t)(value >> 32));
1683  __RV_CSR_WRITE(CSR_MHPMCOUNTER22, (uint32_t)(value)); break;
1684  case 23: __RV_CSR_WRITE(CSR_MHPMCOUNTER23, 0); // prevent carry
1685  __RV_CSR_WRITE(CSR_MHPMCOUNTER23H, (uint32_t)(value >> 32));
1686  __RV_CSR_WRITE(CSR_MHPMCOUNTER23, (uint32_t)(value)); break;
1687  case 24: __RV_CSR_WRITE(CSR_MHPMCOUNTER24, 0); // prevent carry
1688  __RV_CSR_WRITE(CSR_MHPMCOUNTER24H, (uint32_t)(value >> 32));
1689  __RV_CSR_WRITE(CSR_MHPMCOUNTER24, (uint32_t)(value)); break;
1690  case 25: __RV_CSR_WRITE(CSR_MHPMCOUNTER25, 0); // prevent carry
1691  __RV_CSR_WRITE(CSR_MHPMCOUNTER25H, (uint32_t)(value >> 32));
1692  __RV_CSR_WRITE(CSR_MHPMCOUNTER25, (uint32_t)(value)); break;
1693  case 26: __RV_CSR_WRITE(CSR_MHPMCOUNTER26, 0); // prevent carry
1694  __RV_CSR_WRITE(CSR_MHPMCOUNTER26H, (uint32_t)(value >> 32));
1695  __RV_CSR_WRITE(CSR_MHPMCOUNTER26, (uint32_t)(value)); break;
1696  case 27: __RV_CSR_WRITE(CSR_MHPMCOUNTER27, 0); // prevent carry
1697  __RV_CSR_WRITE(CSR_MHPMCOUNTER27H, (uint32_t)(value >> 32));
1698  __RV_CSR_WRITE(CSR_MHPMCOUNTER27, (uint32_t)(value)); break;
1699  case 28: __RV_CSR_WRITE(CSR_MHPMCOUNTER28, 0); // prevent carry
1700  __RV_CSR_WRITE(CSR_MHPMCOUNTER28H, (uint32_t)(value >> 32));
1701  __RV_CSR_WRITE(CSR_MHPMCOUNTER28, (uint32_t)(value)); break;
1702  case 29: __RV_CSR_WRITE(CSR_MHPMCOUNTER29, 0); // prevent carry
1703  __RV_CSR_WRITE(CSR_MHPMCOUNTER29H, (uint32_t)(value >> 32));
1704  __RV_CSR_WRITE(CSR_MHPMCOUNTER29, (uint32_t)(value)); break;
1705  case 30: __RV_CSR_WRITE(CSR_MHPMCOUNTER30, 0); // prevent carry
1706  __RV_CSR_WRITE(CSR_MHPMCOUNTER30H, (uint32_t)(value >> 32));
1707  __RV_CSR_WRITE(CSR_MHPMCOUNTER30, (uint32_t)(value)); break;
1708  case 31: __RV_CSR_WRITE(CSR_MHPMCOUNTER31, 0); // prevent carry
1709  __RV_CSR_WRITE(CSR_MHPMCOUNTER31H, (uint32_t)(value >> 32));
1710  __RV_CSR_WRITE(CSR_MHPMCOUNTER31, (uint32_t)(value)); break;
1711 
1712 #elif __RISCV_XLEN == 64
1713  case 3: __RV_CSR_WRITE(CSR_MHPMCOUNTER3, (value)); break;
1714  case 4: __RV_CSR_WRITE(CSR_MHPMCOUNTER4, (value)); break;
1715  case 5: __RV_CSR_WRITE(CSR_MHPMCOUNTER5, (value)); break;
1716  case 6: __RV_CSR_WRITE(CSR_MHPMCOUNTER6, (value)); break;
1717  case 7: __RV_CSR_WRITE(CSR_MHPMCOUNTER7, (value)); break;
1718  case 8: __RV_CSR_WRITE(CSR_MHPMCOUNTER8, (value)); break;
1719  case 9: __RV_CSR_WRITE(CSR_MHPMCOUNTER9, (value)); break;
1720  case 10: __RV_CSR_WRITE(CSR_MHPMCOUNTER10, (value)); break;
1721  case 11: __RV_CSR_WRITE(CSR_MHPMCOUNTER11, (value)); break;
1722  case 12: __RV_CSR_WRITE(CSR_MHPMCOUNTER12, (value)); break;
1723  case 13: __RV_CSR_WRITE(CSR_MHPMCOUNTER13, (value)); break;
1724  case 14: __RV_CSR_WRITE(CSR_MHPMCOUNTER14, (value)); break;
1725  case 15: __RV_CSR_WRITE(CSR_MHPMCOUNTER15, (value)); break;
1726  case 16: __RV_CSR_WRITE(CSR_MHPMCOUNTER16, (value)); break;
1727  case 17: __RV_CSR_WRITE(CSR_MHPMCOUNTER17, (value)); break;
1728  case 18: __RV_CSR_WRITE(CSR_MHPMCOUNTER18, (value)); break;
1729  case 19: __RV_CSR_WRITE(CSR_MHPMCOUNTER19, (value)); break;
1730  case 20: __RV_CSR_WRITE(CSR_MHPMCOUNTER20, (value)); break;
1731  case 21: __RV_CSR_WRITE(CSR_MHPMCOUNTER21, (value)); break;
1732  case 22: __RV_CSR_WRITE(CSR_MHPMCOUNTER22, (value)); break;
1733  case 23: __RV_CSR_WRITE(CSR_MHPMCOUNTER23, (value)); break;
1734  case 24: __RV_CSR_WRITE(CSR_MHPMCOUNTER24, (value)); break;
1735  case 25: __RV_CSR_WRITE(CSR_MHPMCOUNTER25, (value)); break;
1736  case 26: __RV_CSR_WRITE(CSR_MHPMCOUNTER26, (value)); break;
1737  case 27: __RV_CSR_WRITE(CSR_MHPMCOUNTER27, (value)); break;
1738  case 28: __RV_CSR_WRITE(CSR_MHPMCOUNTER28, (value)); break;
1739  case 29: __RV_CSR_WRITE(CSR_MHPMCOUNTER29, (value)); break;
1740  case 30: __RV_CSR_WRITE(CSR_MHPMCOUNTER30, (value)); break;
1741  case 31: __RV_CSR_WRITE(CSR_MHPMCOUNTER31, (value)); break;
1742 
1743 #else
1744 #endif
1745  default: break;
1746  }
1747 }
#define __RV_CSR_WRITE(csr, val)
CSR operation Macro for csrw instruction.

References __RV_CSR_WRITE, CSR_MHPMCOUNTER10, CSR_MHPMCOUNTER10H, CSR_MHPMCOUNTER11, CSR_MHPMCOUNTER11H, CSR_MHPMCOUNTER12, CSR_MHPMCOUNTER12H, CSR_MHPMCOUNTER13, CSR_MHPMCOUNTER13H, CSR_MHPMCOUNTER14, CSR_MHPMCOUNTER14H, CSR_MHPMCOUNTER15, CSR_MHPMCOUNTER15H, CSR_MHPMCOUNTER16, CSR_MHPMCOUNTER16H, CSR_MHPMCOUNTER17, CSR_MHPMCOUNTER17H, CSR_MHPMCOUNTER18, CSR_MHPMCOUNTER18H, CSR_MHPMCOUNTER19, CSR_MHPMCOUNTER19H, CSR_MHPMCOUNTER20, CSR_MHPMCOUNTER20H, CSR_MHPMCOUNTER21, CSR_MHPMCOUNTER21H, CSR_MHPMCOUNTER22, CSR_MHPMCOUNTER22H, CSR_MHPMCOUNTER23, CSR_MHPMCOUNTER23H, CSR_MHPMCOUNTER24, CSR_MHPMCOUNTER24H, CSR_MHPMCOUNTER25, CSR_MHPMCOUNTER25H, CSR_MHPMCOUNTER26, CSR_MHPMCOUNTER26H, CSR_MHPMCOUNTER27, CSR_MHPMCOUNTER27H, CSR_MHPMCOUNTER28, CSR_MHPMCOUNTER28H, CSR_MHPMCOUNTER29, CSR_MHPMCOUNTER29H, CSR_MHPMCOUNTER3, CSR_MHPMCOUNTER30, CSR_MHPMCOUNTER30H, CSR_MHPMCOUNTER31, CSR_MHPMCOUNTER31H, CSR_MHPMCOUNTER3H, CSR_MHPMCOUNTER4, CSR_MHPMCOUNTER4H, CSR_MHPMCOUNTER5, CSR_MHPMCOUNTER5H, CSR_MHPMCOUNTER6, CSR_MHPMCOUNTER6H, CSR_MHPMCOUNTER7, CSR_MHPMCOUNTER7H, CSR_MHPMCOUNTER8, CSR_MHPMCOUNTER8H, CSR_MHPMCOUNTER9, and CSR_MHPMCOUNTER9H.

◆ __set_hpm_event()

__STATIC_FORCEINLINE void __set_hpm_event ( unsigned long  idx,
unsigned long  event 
)

Set event for selected high performance monitor event.

Parameters
[in]idxHPMEVENTx CSR index(3-31)
[in]eventHPMEVENTx Register value to set

Set event for high performance monitor event register

Definition at line 1533 of file core_feature_base.h.

1534 {
1535  switch (idx) {
1536  case 3: __RV_CSR_WRITE(CSR_MHPMEVENT3, event); break;
1537  case 4: __RV_CSR_WRITE(CSR_MHPMEVENT4, event); break;
1538  case 5: __RV_CSR_WRITE(CSR_MHPMEVENT5, event); break;
1539  case 6: __RV_CSR_WRITE(CSR_MHPMEVENT6, event); break;
1540  case 7: __RV_CSR_WRITE(CSR_MHPMEVENT7, event); break;
1541  case 8: __RV_CSR_WRITE(CSR_MHPMEVENT8, event); break;
1542  case 9: __RV_CSR_WRITE(CSR_MHPMEVENT9, event); break;
1543  case 10: __RV_CSR_WRITE(CSR_MHPMEVENT10, event); break;
1544  case 11: __RV_CSR_WRITE(CSR_MHPMEVENT11, event); break;
1545  case 12: __RV_CSR_WRITE(CSR_MHPMEVENT12, event); break;
1546  case 13: __RV_CSR_WRITE(CSR_MHPMEVENT13, event); break;
1547  case 14: __RV_CSR_WRITE(CSR_MHPMEVENT14, event); break;
1548  case 15: __RV_CSR_WRITE(CSR_MHPMEVENT15, event); break;
1549  case 16: __RV_CSR_WRITE(CSR_MHPMEVENT16, event); break;
1550  case 17: __RV_CSR_WRITE(CSR_MHPMEVENT17, event); break;
1551  case 18: __RV_CSR_WRITE(CSR_MHPMEVENT18, event); break;
1552  case 19: __RV_CSR_WRITE(CSR_MHPMEVENT19, event); break;
1553  case 20: __RV_CSR_WRITE(CSR_MHPMEVENT20, event); break;
1554  case 21: __RV_CSR_WRITE(CSR_MHPMEVENT21, event); break;
1555  case 22: __RV_CSR_WRITE(CSR_MHPMEVENT22, event); break;
1556  case 23: __RV_CSR_WRITE(CSR_MHPMEVENT23, event); break;
1557  case 24: __RV_CSR_WRITE(CSR_MHPMEVENT24, event); break;
1558  case 25: __RV_CSR_WRITE(CSR_MHPMEVENT25, event); break;
1559  case 26: __RV_CSR_WRITE(CSR_MHPMEVENT26, event); break;
1560  case 27: __RV_CSR_WRITE(CSR_MHPMEVENT27, event); break;
1561  case 28: __RV_CSR_WRITE(CSR_MHPMEVENT28, event); break;
1562  case 29: __RV_CSR_WRITE(CSR_MHPMEVENT29, event); break;
1563  case 30: __RV_CSR_WRITE(CSR_MHPMEVENT30, event); break;
1564  case 31: __RV_CSR_WRITE(CSR_MHPMEVENT31, event); break;
1565  default: break;
1566  }
1567 }

References __RV_CSR_WRITE, CSR_MHPMEVENT10, CSR_MHPMEVENT11, CSR_MHPMEVENT12, CSR_MHPMEVENT13, CSR_MHPMEVENT14, CSR_MHPMEVENT15, CSR_MHPMEVENT16, CSR_MHPMEVENT17, CSR_MHPMEVENT18, CSR_MHPMEVENT19, CSR_MHPMEVENT20, CSR_MHPMEVENT21, CSR_MHPMEVENT22, CSR_MHPMEVENT23, CSR_MHPMEVENT24, CSR_MHPMEVENT25, CSR_MHPMEVENT26, CSR_MHPMEVENT27, CSR_MHPMEVENT28, CSR_MHPMEVENT29, CSR_MHPMEVENT3, CSR_MHPMEVENT30, CSR_MHPMEVENT31, CSR_MHPMEVENT4, CSR_MHPMEVENT5, CSR_MHPMEVENT6, CSR_MHPMEVENT7, CSR_MHPMEVENT8, and CSR_MHPMEVENT9.

◆ __set_medeleg()

__STATIC_FORCEINLINE void __set_medeleg ( unsigned long  mask)

Set exceptions delegation to S mode.

Set certain exceptions of supervisor mode or user mode delegated from machined mode to supervisor mode.

Remarks
Exception should trigger in supervisor mode or user mode.

Definition at line 2005 of file core_feature_base.h.

2006 {
2007  __RV_CSR_WRITE(CSR_MEDELEG, mask);
2008 }
#define CSR_MEDELEG

References __RV_CSR_WRITE, and CSR_MEDELEG.

◆ __set_mideleg()

__STATIC_FORCEINLINE void __set_mideleg ( unsigned long  mask)

Set interrupt delegation to S mode.

Set certain interrupt of supervisor mode or user mode delegated from machined mode to supervisor mode.

Remarks
interrupt should trigger in supervisor mode or user mode.

Definition at line 2017 of file core_feature_base.h.

2018 {
2019  __RV_CSR_WRITE(CSR_MIDELEG, mask);
2020 }
#define CSR_MIDELEG

References __RV_CSR_WRITE, and CSR_MIDELEG.

◆ __set_wfi_sleepmode()

__STATIC_FORCEINLINE void __set_wfi_sleepmode ( WFI_SleepMode_Type  mode)

Set Sleep mode of WFI.

Set the SLEEPVALUE CSR register to control the WFI Sleep mode.

Parameters
[in]modeThe sleep mode to be set

Definition at line 1402 of file core_feature_base.h.

1403 {
1405 }
#define CSR_SLEEPVALUE

References __RV_CSR_WRITE, and CSR_SLEEPVALUE.

◆ __SH()

__STATIC_FORCEINLINE void __SH ( volatile void *  addr,
uint16_t  val 
)

Write 16bit value to address (16 bit)

Write 16 bit value.

Parameters
[in]addrAddress pointer to data
[in]valValue to set

Definition at line 2143 of file core_feature_base.h.

2144 {
2145  __ASM volatile ("sh %0, 0(%1)" : : "r" (val), "r" (addr));
2146 }

References __ASM.

◆ __SW()

__STATIC_FORCEINLINE void __SW ( volatile void *  addr,
uint32_t  val 
)

◆ __TXEVT()

__STATIC_FORCEINLINE void __TXEVT ( void  )

Send TX Event.

Set the CSR TXEVT to control send a TX Event. The Core will output signal tx_evt as output event signal.

Definition at line 1413 of file core_feature_base.h.

1414 {
1415  __RV_CSR_SET(CSR_TXEVT, 0x1);
1416 }
#define CSR_TXEVT

References __RV_CSR_SET, and CSR_TXEVT.

◆ __WFE()

__STATIC_FORCEINLINE void __WFE ( void  )

Wait For Event.

Wait For Event is executed using CSR_WFE.WFE=1 and WFI instruction. It will suspends execution until event, NMI or Debug happened. When Core is waked up, Core will resume previous execution

Definition at line 1357 of file core_feature_base.h.

1358 {
1360  __ASM volatile("wfi");
1362 }
#define WFE_WFE
#define CSR_WFE

References __ASM, __RV_CSR_CLEAR, __RV_CSR_SET, CSR_WFE, and WFE_WFE.

◆ __WFI()

__STATIC_FORCEINLINE void __WFI ( void  )

Wait For Interrupt.

Wait For Interrupt is is executed using CSR_WFE.WFE=0 and WFI instruction. It will suspends execution until interrupt, NMI or Debug happened. When Core is waked up by interrupt, if

  1. mstatus.MIE == 1(interrupt enabled), Core will enter ISR code
  2. mstatus.MIE == 0(interrupt disabled), Core will resume previous execution

Definition at line 1344 of file core_feature_base.h.

1345 {
1347  __ASM volatile("wfi");
1348 }

References __ASM, __RV_CSR_CLEAR, CSR_WFE, and WFE_WFE.