core_feature_eclic.h

/*
 * Copyright (c) 2019 Nuclei Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#ifndef __CORE_FEATURE_ECLIC__
#define __CORE_FEATURE_ECLIC__
 
/*
 * ECLIC Feature Configuration Macro:
 * 1. __ECLIC_PRESENT:  Define whether Enhanced Core Local Interrupt Controller (ECLIC) Unit is present or not
 *   * 0: Not present
 *   * 1: Present
 * 2. __ECLIC_BASEADDR:  Base address of the ECLIC unit.
 * 3. __ECLIC_INTCTLBITS:  Optional, if defined, it should set to the value of ECLIC_GetInfoCtlbits(), define the number of hardware bits are actually implemented in the clicintctl registers.
 *   Valid number is 1 - 8.
 * 4. __ECLIC_INTNUM:  Define the external interrupt number of ECLIC Unit
 * 5. __SMODE_PRESENT:  Define whether S-Mode present, if present, ECLIC will present with S-Mode ECLIC feature
 *   * 0: Not present
 *   * 1: Present
 * 6. __ECLIC_VER:  Optional, define the ECLIC version, if not defined, defaults to 1
 *   * 1: ECLICv1 (default)
 *   * 2: ECLICv2 (supports hardware context saving and shadow registers)
 *
 */
#ifdef __cplusplus
extern "C" {
#endif
 
#include "core_feature_base.h"
 
#if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1)
 
typedef union
{
    struct {
        __IM uint8_t _reserved0:1;
        __IOM uint8_t nlbits:4;                
        __IM uint8_t nmbits:2;                 
        __IM uint8_t _reserved1:1;
    } b;                                       
    uint8_t w;                                 
} CLICCFG_Type;
 
typedef union {
    struct {
        __IM uint32_t numint:13;               
        __IM uint32_t version:8;               
        __IM uint32_t intctlbits:4;            
        __IM uint32_t shd_num:4;               
        __IM uint32_t _reserved0:3;            
    } b;                                       
    __IM uint32_t w;                           
} CLICINFO_Type;
 
typedef struct {
    __IOM uint8_t INTIP;                       
    __IOM uint8_t INTIE;                       
    __IOM uint8_t INTATTR;                     
    __IOM uint8_t INTCTRL;                     
} CLIC_CTRL_Type;
 
typedef struct {
    __IOM uint8_t CFG;                         
    __IM uint8_t RESERVED0[3];
    __IM uint32_t INFO;                        
    __IM uint8_t RESERVED1;
#if defined(__SMODE_PRESENT) && (__SMODE_PRESENT == 1)
    __IOM uint8_t STH;                         
#else
    __IM uint8_t RESERVED2;
#endif
    __IM uint8_t RESERVED3;
    __IOM uint8_t MTH;                         
    uint32_t RESERVED4[1021];
#if defined(__SMODE_PRESENT) && (__SMODE_PRESENT == 1)
    CLIC_CTRL_Type CTRL[1024];                 
    __IM uint32_t RESERVED5[2];
    __IM uint8_t RESERVED6;
    __IOM uint8_t SSTH;                        
    __IM uint8_t RESERVED7;
    __IM uint8_t RESERVED8;
    __IM uint32_t RESERVED9[1021];
    CLIC_CTRL_Type SCTRL[1024];                
#else
    CLIC_CTRL_Type CTRL[4096];                 
#endif
} CLIC_Type;
 
#define CLIC_CLICCFG_NLBIT_Pos                 1U                                       
#define CLIC_CLICCFG_NLBIT_Msk                 (0xFUL << CLIC_CLICCFG_NLBIT_Pos)        
#define CLIC_CLICINFO_CTLBIT_Pos               21U                                      
#define CLIC_CLICINFO_CTLBIT_Msk               (0xFUL << CLIC_CLICINFO_CTLBIT_Pos)      
#define CLIC_CLICINFO_VER_Pos                  13U                                      
#define CLIC_CLICINFO_VER_Msk                  (0xFFUL << CLIC_CLICINFO_VER_Pos)        
#define CLIC_CLICINFO_NUM_Pos                  0U                                       
#define CLIC_CLICINFO_NUM_Msk                  (0x1FFFUL << CLIC_CLICINFO_NUM_Pos)      
#define CLIC_CLICINFO_SHD_NUM_Pos              25U                                      
#define CLIC_CLICINFO_SHD_NUM_Msk              (0xFUL << CLIC_CLICINFO_SHD_NUM_Pos)     
#define CLIC_INTIP_IP_Pos                      0U                                       
#define CLIC_INTIP_IP_Msk                      (0x1UL << CLIC_INTIP_IP_Pos)             
#define CLIC_INTIE_IE_Pos                      0U                                       
#define CLIC_INTIE_IE_Msk                      (0x1UL << CLIC_INTIE_IE_Pos)             
#if defined(__SMODE_PRESENT) && (__SMODE_PRESENT == 1)
#define CLIC_INTATTR_MODE_Pos                  6U                                       
#define CLIC_INTATTR_MODE_Msk                  (0x3U << CLIC_INTATTR_MODE_Pos)          
#endif
 
#define CLIC_INTATTR_TRIG_Pos                  1U                                       
#define CLIC_INTATTR_TRIG_Msk                  (0x3UL << CLIC_INTATTR_TRIG_Pos)         
#define CLIC_INTATTR_SHV_Pos                   0U                                       
#define CLIC_INTATTR_SHV_Msk                   (0x1UL << CLIC_INTATTR_SHV_Pos)          
#define ECLIC_MAX_NLBITS                       8U                                       
#define ECLIC_MODE_MTVEC_Msk                   3U                                       
#define ECLIC_NON_VECTOR_INTERRUPT             0x0                                      
#define ECLIC_VECTOR_INTERRUPT                 0x1                                      
typedef enum ECLIC_TRIGGER {
    ECLIC_LEVEL_TRIGGER = 0x0,          
    ECLIC_POSTIVE_EDGE_TRIGGER = 0x1,   
    ECLIC_NEGTIVE_EDGE_TRIGGER = 0x3,   
    ECLIC_MAX_TRIGGER = 0x3             
} ECLIC_TRIGGER_Type;
 
#ifndef __ECLIC_BASEADDR
/* Base address of ECLIC(__ECLIC_BASEADDR) should be defined in <Device.h> */
#error "__ECLIC_BASEADDR is not defined, please check!"
#endif
 
#ifndef __ECLIC_INTCTLBITS
/* Define __ECLIC_INTCTLBITS to get via ECLIC->INFO if not defined */
#define __ECLIC_INTCTLBITS                  (__ECLIC_GetInfoCtlbits())
#endif
 
#ifndef __ECLIC_VER
/* Define __ECLIC_VER to 1 if not defined, assume ECLICv1 by default */
#define __ECLIC_VER                         1U
#endif
 
/* ECLIC Memory mapping of Device */
#define ECLIC_BASE                          __ECLIC_BASEADDR                            
#define ECLIC                               ((CLIC_Type *) ECLIC_BASE)                   /* end of group NMSIS_Core_ECLIC_Registers */
 
/* ##########################   ECLIC functions  #################################### */
/* The following enum IRQn definition in this file
 * is only used for doxygen documentation generation,
 * The <Device>.h is the real file to define it by vendor
 */
#if defined(__ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__)
typedef enum IRQn {
    /* ========= Nuclei N/NX Core Specific Interrupt Numbers  =========== */
    /* Core Internal Interrupt IRQn definitions */
    Reserved0_IRQn            =   0,              
    Reserved1_IRQn            =   1,              
    Reserved2_IRQn            =   2,              
    SysTimerSW_IRQn           =   3,              
    Reserved3_IRQn            =   4,              
    Reserved4_IRQn            =   5,              
    Reserved5_IRQn            =   6,              
    SysTimer_IRQn             =   7,              
    Reserved6_IRQn            =   8,              
    Reserved7_IRQn            =   9,              
    Reserved8_IRQn            =  10,              
    Reserved9_IRQn            =  11,              
    Reserved10_IRQn           =  12,              
    Reserved11_IRQn           =  13,              
    Reserved12_IRQn           =  14,              
    Reserved13_IRQn           =  15,              
    Reserved14_IRQn           =  16,              
    Reserved15_IRQn           =  17,              
    Reserved16_IRQn           =  18,              
    /* ========= Device Specific Interrupt Numbers  =================== */
    /* ToDo: add here your device specific external interrupt numbers.
     * 19~max(NUM_INTERRUPT, 1023) is reserved number for user.
     * Maxmum interrupt supported could get from clicinfo.NUM_INTERRUPT.
     * According the interrupt handlers defined in startup_Device.S
     * eg.: Interrupt for Timer#1       eclic_tim1_handler   ->   TIM1_IRQn */
    FirstDeviceSpecificInterrupt_IRQn    = 19,    
    SOC_INT_MAX,                                  
} IRQn_Type;
#endif /* __ONLY_FOR_DOXYGEN_DOCUMENT_GENERATION__ */
 
#ifdef NMSIS_ECLIC_VIRTUAL
    #ifndef NMSIS_ECLIC_VIRTUAL_HEADER_FILE
        #define NMSIS_ECLIC_VIRTUAL_HEADER_FILE "nmsis_eclic_virtual.h"
    #endif
    #include NMSIS_ECLIC_VIRTUAL_HEADER_FILE
#else
    #define ECLIC_SetCfgNlbits            __ECLIC_SetCfgNlbits
    #define ECLIC_GetCfgNlbits            __ECLIC_GetCfgNlbits
    #define ECLIC_GetInfoVer              __ECLIC_GetInfoVer
    #define ECLIC_GetInfoCtlbits          __ECLIC_GetInfoCtlbits
    #define ECLIC_GetInfoNum              __ECLIC_GetInfoNum
    #define ECLIC_GetInfoShadowNum        __ECLIC_GetInfoShadowNum
    #define ECLIC_SetMth                  __ECLIC_SetMth
    #define ECLIC_GetMth                  __ECLIC_GetMth
    #define ECLIC_EnableIRQ               __ECLIC_EnableIRQ
    #define ECLIC_GetEnableIRQ            __ECLIC_GetEnableIRQ
    #define ECLIC_DisableIRQ              __ECLIC_DisableIRQ
    #define ECLIC_SetPendingIRQ           __ECLIC_SetPendingIRQ
    #define ECLIC_GetPendingIRQ           __ECLIC_GetPendingIRQ
    #define ECLIC_ClearPendingIRQ         __ECLIC_ClearPendingIRQ
    #define ECLIC_SetTrigIRQ              __ECLIC_SetTrigIRQ
    #define ECLIC_GetTrigIRQ              __ECLIC_GetTrigIRQ
    #define ECLIC_SetShvIRQ               __ECLIC_SetShvIRQ
    #define ECLIC_GetShvIRQ               __ECLIC_GetShvIRQ
    #define ECLIC_SetCtrlIRQ              __ECLIC_SetCtrlIRQ
    #define ECLIC_GetCtrlIRQ              __ECLIC_GetCtrlIRQ
    #define ECLIC_SetLevelIRQ             __ECLIC_SetLevelIRQ
    #define ECLIC_GetLevelIRQ             __ECLIC_GetLevelIRQ
    #define ECLIC_SetPriorityIRQ          __ECLIC_SetPriorityIRQ
    #define ECLIC_GetPriorityIRQ          __ECLIC_GetPriorityIRQ
#if __ECLIC_VER == 2
    #define ECLIC_EnableShadow            __ECLIC_EnableShadow
    #define ECLIC_DisableShadow           __ECLIC_DisableShadow
    #define ECLIC_SetShadowLevel          __ECLIC_SetShadowLevel
    #define ECLIC_GetShadowLevel          __ECLIC_GetShadowLevel
    #define ECLIC_SetShadowLevelReg       __ECLIC_SetShadowLevelReg
    #define ECLIC_GetShadowLevelReg       __ECLIC_GetShadowLevelReg
#endif
 
    /* For S-Mode */
#if defined(__SMODE_PRESENT) && (__SMODE_PRESENT == 1)
    #define ECLIC_SetModeIRQ              __ECLIC_SetModeIRQ
    #define ECLIC_SetSth                  __ECLIC_SetSth
    #define ECLIC_GetSth                  __ECLIC_GetSth
    #define ECLIC_SetPendingIRQ_S         __ECLIC_SetPendingIRQ_S
    #define ECLIC_GetPendingIRQ_S         __ECLIC_GetPendingIRQ_S
    #define ECLIC_ClearPendingIRQ_S       __ECLIC_ClearPendingIRQ_S
    #define ECLIC_SetTrigIRQ_S            __ECLIC_SetTrigIRQ_S
    #define ECLIC_GetTrigIRQ_S            __ECLIC_GetTrigIRQ_S
    #define ECLIC_SetShvIRQ_S             __ECLIC_SetShvIRQ_S
    #define ECLIC_GetShvIRQ_S             __ECLIC_GetShvIRQ_S
    #define ECLIC_SetCtrlIRQ_S            __ECLIC_SetCtrlIRQ_S
    #define ECLIC_GetCtrlIRQ_S            __ECLIC_GetCtrlIRQ_S
    #define ECLIC_SetLevelIRQ_S           __ECLIC_SetLevelIRQ_S
    #define ECLIC_GetLevelIRQ_S           __ECLIC_GetLevelIRQ_S
    #define ECLIC_SetPriorityIRQ_S        __ECLIC_SetPriorityIRQ_S
    #define ECLIC_GetPriorityIRQ_S        __ECLIC_GetPriorityIRQ_S
    #define ECLIC_EnableIRQ_S             __ECLIC_EnableIRQ_S
    #define ECLIC_GetEnableIRQ_S          __ECLIC_GetEnableIRQ_S
    #define ECLIC_DisableIRQ_S            __ECLIC_DisableIRQ_S
#if __ECLIC_VER == 2
    #define ECLIC_EnableShadow_S          __ECLIC_EnableShadow_S
    #define ECLIC_DisableShadow_S         __ECLIC_DisableShadow_S
    #define ECLIC_SetShadowLevel_S        __ECLIC_SetShadowLevel_S
    #define ECLIC_GetShadowLevel_S        __ECLIC_GetShadowLevel_S
    #define ECLIC_SetShadowLevelReg_S     __ECLIC_SetShadowLevelReg_S
    #define ECLIC_GetShadowLevelReg_S     __ECLIC_GetShadowLevelReg_S
#endif
 
#endif
#endif /* NMSIS_ECLIC_VIRTUAL */
 
#ifdef NMSIS_VECTAB_VIRTUAL
    #ifndef NMSIS_VECTAB_VIRTUAL_HEADER_FILE
        #define NMSIS_VECTAB_VIRTUAL_HEADER_FILE "nmsis_vectab_virtual.h"
    #endif
    #include NMSIS_VECTAB_VIRTUAL_HEADER_FILE
#else
    #define ECLIC_SetVector              __ECLIC_SetVector
    #define ECLIC_GetVector              __ECLIC_GetVector
 
#if defined(__SMODE_PRESENT) && (__SMODE_PRESENT == 1)
    #define ECLIC_SetVector_S            __ECLIC_SetVector_S
    #define ECLIC_GetVector_S            __ECLIC_GetVector_S
#endif
#endif  /* (NMSIS_VECTAB_VIRTUAL) */
 
__STATIC_FORCEINLINE void __ECLIC_SetCfgNlbits(uint32_t nlbits)
{
    uint8_t temp = ECLIC->CFG;
 
    ECLIC->CFG = (temp & ~CLIC_CLICCFG_NLBIT_Msk) | \
                 ((uint8_t)((nlbits << CLIC_CLICCFG_NLBIT_Pos) & CLIC_CLICCFG_NLBIT_Msk));
}
 
__STATIC_FORCEINLINE uint32_t __ECLIC_GetCfgNlbits(void)
{
    return ((uint32_t)((ECLIC->CFG & CLIC_CLICCFG_NLBIT_Msk) >> CLIC_CLICCFG_NLBIT_Pos));
}
 
__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoVer(void)
{
    return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_VER_Msk) >> CLIC_CLICINFO_VER_Pos));
}
 
__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoCtlbits(void)
{
    return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_CTLBIT_Msk) >> CLIC_CLICINFO_CTLBIT_Pos));
}
 
__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoNum(void)
{
    return ((uint32_t)((ECLIC->INFO & CLIC_CLICINFO_NUM_Msk) >> CLIC_CLICINFO_NUM_Pos));
}
 
__STATIC_FORCEINLINE uint32_t __ECLIC_GetInfoShadowNum(void)
{
    return ((uint32_t)((ECLIC->INFO & (CLIC_CLICINFO_SHD_NUM_Msk)) >> CLIC_CLICINFO_SHD_NUM_Pos));
}
 
__STATIC_FORCEINLINE void __ECLIC_SetMth(uint8_t mth)
{
    ECLIC->MTH = mth;
}
 
__STATIC_FORCEINLINE uint8_t __ECLIC_GetMth(void)
{
    return (ECLIC->MTH);
}
 
 
__STATIC_FORCEINLINE void __ECLIC_EnableIRQ(IRQn_Type IRQn)
{
    ECLIC->CTRL[IRQn].INTIE |= CLIC_INTIE_IE_Msk;
}
 
__STATIC_FORCEINLINE uint32_t __ECLIC_GetEnableIRQ(IRQn_Type IRQn)
{
    return ((uint32_t) (ECLIC->CTRL[IRQn].INTIE) & CLIC_INTIE_IE_Msk);
}
 
__STATIC_FORCEINLINE void __ECLIC_DisableIRQ(IRQn_Type IRQn)
{
    ECLIC->CTRL[IRQn].INTIE &= ~CLIC_INTIE_IE_Msk;
}
 
__STATIC_FORCEINLINE int32_t __ECLIC_GetPendingIRQ(IRQn_Type IRQn)
{
    return ((uint32_t)(ECLIC->CTRL[IRQn].INTIP) & CLIC_INTIP_IP_Msk);
}
 
__STATIC_FORCEINLINE void __ECLIC_SetPendingIRQ(IRQn_Type IRQn)
{
    ECLIC->CTRL[IRQn].INTIP |= CLIC_INTIP_IP_Msk;
}
 
__STATIC_FORCEINLINE void __ECLIC_ClearPendingIRQ(IRQn_Type IRQn)
{
    ECLIC->CTRL[IRQn].INTIP &= ~CLIC_INTIP_IP_Msk;
}
 
__STATIC_FORCEINLINE void __ECLIC_SetTrigIRQ(IRQn_Type IRQn, uint32_t trig)
{
    uint8_t temp = ECLIC->CTRL[IRQn].INTATTR;
 
    ECLIC->CTRL[IRQn].INTATTR = (temp & ~CLIC_INTATTR_TRIG_Msk) | \
                                ((uint8_t)(trig << CLIC_INTATTR_TRIG_Pos));
}
 
__STATIC_FORCEINLINE uint32_t __ECLIC_GetTrigIRQ(IRQn_Type IRQn)
{
    return ((uint32_t)(((ECLIC->CTRL[IRQn].INTATTR) & CLIC_INTATTR_TRIG_Msk) >> CLIC_INTATTR_TRIG_Pos));
}
 
__STATIC_FORCEINLINE void __ECLIC_SetShvIRQ(IRQn_Type IRQn, uint32_t shv)
{
    uint8_t temp = ECLIC->CTRL[IRQn].INTATTR;
 
    ECLIC->CTRL[IRQn].INTATTR = (temp & ~CLIC_INTATTR_SHV_Msk) | \
                                ((uint8_t)(shv << CLIC_INTATTR_SHV_Pos));
}
 
__STATIC_FORCEINLINE uint32_t __ECLIC_GetShvIRQ(IRQn_Type IRQn)
{
    return ((uint32_t)(((ECLIC->CTRL[IRQn].INTATTR) & CLIC_INTATTR_SHV_Msk) >> CLIC_INTATTR_SHV_Pos));
}
 
__STATIC_FORCEINLINE void __ECLIC_SetCtrlIRQ(IRQn_Type IRQn, uint8_t intctrl)
{
    ECLIC->CTRL[IRQn].INTCTRL = intctrl;
}
 
__STATIC_FORCEINLINE uint8_t __ECLIC_GetCtrlIRQ(IRQn_Type IRQn)
{
    return (ECLIC->CTRL[IRQn].INTCTRL);
}
 
__STATIC_INLINE void __ECLIC_SetLevelIRQ(IRQn_Type IRQn, uint8_t lvl_abs)
{
    uint8_t nlbits = __ECLIC_GetCfgNlbits();
    uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
 
    if (nlbits == 0) {
        return;
    }
 
    if (nlbits > intctlbits) {
        nlbits = intctlbits;
    }
    uint8_t maxlvl = ((1UL << nlbits) - 1);
    if (lvl_abs > maxlvl) {
        lvl_abs = maxlvl;
    }
    uint8_t lvl = lvl_abs << (ECLIC_MAX_NLBITS - nlbits);
    uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ(IRQn);
    cur_ctrl = cur_ctrl << nlbits;
    cur_ctrl = cur_ctrl >> nlbits;
    __ECLIC_SetCtrlIRQ(IRQn, (cur_ctrl | lvl));
}
 
__STATIC_INLINE uint8_t __ECLIC_GetLevelIRQ(IRQn_Type IRQn)
{
    uint8_t nlbits = __ECLIC_GetCfgNlbits();
    uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
 
    if (nlbits == 0) {
        return 0;
    }
 
    if (nlbits > intctlbits) {
        nlbits = intctlbits;
    }
    uint8_t intctrl = __ECLIC_GetCtrlIRQ(IRQn);
    uint8_t lvl_abs = intctrl >> (ECLIC_MAX_NLBITS - nlbits);
    return lvl_abs;
}
 
__STATIC_INLINE void __ECLIC_SetPriorityIRQ(IRQn_Type IRQn, uint8_t pri)
{
    uint8_t nlbits = __ECLIC_GetCfgNlbits();
    uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
    if (nlbits < intctlbits) {
        uint8_t maxpri = ((1UL << (intctlbits - nlbits)) - 1);
        if (pri > maxpri) {
            pri = maxpri;
        }
        pri = pri << (ECLIC_MAX_NLBITS - intctlbits);
        uint8_t mask = ((uint8_t)(-1)) >> intctlbits;
        pri = pri | mask;
        uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ(IRQn);
        cur_ctrl = cur_ctrl >> (ECLIC_MAX_NLBITS - nlbits);
        cur_ctrl = cur_ctrl << (ECLIC_MAX_NLBITS - nlbits);
        __ECLIC_SetCtrlIRQ(IRQn, (cur_ctrl | pri));
    }
}
 
__STATIC_INLINE uint8_t __ECLIC_GetPriorityIRQ(IRQn_Type IRQn)
{
    uint8_t nlbits = __ECLIC_GetCfgNlbits();
    uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
    if (nlbits < intctlbits) {
        uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ(IRQn);
        uint8_t pri = cur_ctrl << nlbits;
        pri = pri >> nlbits;
        pri = pri >> (ECLIC_MAX_NLBITS - intctlbits);
        return pri;
    } else {
        return 0;
    }
}
 
#if __ECLIC_VER == 2
 
__STATIC_FORCEINLINE void __ECLIC_EnableShadow(void)
{
    __RV_CSR_SET(CSR_MECLIC_CTL, MECLIC_CTL_SHADOW_EN);
}
 
__STATIC_FORCEINLINE void __ECLIC_DisableShadow(void)
{
    __RV_CSR_CLEAR(CSR_MECLIC_CTL, MECLIC_CTL_SHADOW_EN);
}
 
__STATIC_INLINE void __ECLIC_SetShadowLevel(unsigned long idx, uint8_t level)
{
    /* Check if idx is valid (0-7) */
    if (idx > 7) {
        return;
    }
 
    uint8_t nlbits = (uint8_t)__ECLIC_GetCfgNlbits();
    /* Limit the level value to the available number of bits */
    uint8_t max_level = (1U << nlbits) - 1;
    if (level > max_level) {
        level = max_level;
    }
 
    /* Position the level value in the upper nlbits of the 8-bit field and set the low (8-nlbits) bits to 1 */
    uint8_t level_shifted = (uint8_t)((level << (8 - nlbits)) | ((1U << (8 - nlbits)) - 1));
 
#if __RISCV_XLEN == 64
    /* For RV64, all 8 shadow registers are in CSR_MSHADGPRLVL0 */
    /* Calculate the bit position for the 8-bit field of the specified index */
    uint32_t bit_pos = idx << 3;  /* idx * 8 using bit shift */
    /* Create mask to clear the 8-bit field for the specified index */
    uint64_t mask = (uint64_t)0xFFUL << bit_pos;
    /* Read, modify, and write the CSR register */
    uint64_t current_val = __RV_CSR_READ(CSR_MSHADGPRLVL0);
    current_val = (current_val & ~mask) | (((uint64_t)level_shifted) << bit_pos);
    __RV_CSR_WRITE(CSR_MSHADGPRLVL0, current_val);
#else
    /* For RV32, calculate bit position and select appropriate register */
    if (idx < 4) {
        /* Shadow registers 1-4 are in CSR_MSHADGPRLVL0 */
        uint32_t bit_pos = idx << 3;  /* idx * 8 using bit shift */
        uint32_t mask = 0xFFUL << bit_pos;
        uint32_t current_val = __RV_CSR_READ(CSR_MSHADGPRLVL0);
        current_val = (current_val & ~mask) | (((uint32_t)level_shifted) << bit_pos);
        __RV_CSR_WRITE(CSR_MSHADGPRLVL0, current_val);
    } else {
        /* Shadow registers 5-8 are in CSR_MSHADGPRLVL1 */
        uint32_t bit_pos = (idx - 4) << 3;  /* (idx - 4) * 8 using bit shift */
        uint32_t mask = 0xFFUL << bit_pos;
        uint32_t current_val = __RV_CSR_READ(CSR_MSHADGPRLVL1);
        current_val = (current_val & ~mask) | (((uint32_t)level_shifted) << bit_pos);
        __RV_CSR_WRITE(CSR_MSHADGPRLVL1, current_val);
    }
#endif
}
 
__STATIC_INLINE uint8_t __ECLIC_GetShadowLevel(unsigned long idx)
{
    /* Check if idx is valid (0-7) */
    if (idx > 7) {
        return 0;
    }
 
    uint8_t nlbits = (uint8_t)__ECLIC_GetCfgNlbits();
 
#if __RISCV_XLEN == 64
    /* For RV64, all 8 shadow registers are in CSR_MSHADGPRLVL0 */
    /* Calculate the bit position for the 8-bit field of the specified index */
    uint32_t bit_pos = idx << 3;  /* idx * 8 using bit shift */
    /* Read the CSR register and extract the 8-bit field */
    uint64_t current_val = __RV_CSR_READ(CSR_MSHADGPRLVL0);
    uint8_t extracted_val = (uint8_t)((current_val >> bit_pos) & 0xFF);
    /* Extract the level from the upper nlbits of the 8-bit field */
    uint8_t level = (extracted_val >> (8 - nlbits));
    return level;
#else
    /* For RV32, calculate bit position and select appropriate register */
    if (idx < 4) {
        /* Shadow registers 1-4 are in CSR_MSHADGPRLVL0 */
        uint32_t bit_pos = idx << 3;  /* idx * 8 using bit shift */
        /* Read the CSR register and extract the 8-bit field */
        uint32_t current_val = __RV_CSR_READ(CSR_MSHADGPRLVL0);
        uint8_t extracted_val = (uint8_t)((current_val >> bit_pos) & 0xFF);
        /* Extract the level from the upper nlbits of the 8-bit field */
        uint8_t level = (extracted_val >> (8 - nlbits));
        return level;
    } else {
        /* Shadow registers 5-8 are in CSR_MSHADGPRLVL1 */
        uint32_t bit_pos = (idx - 4) << 3;  /* (idx - 4) * 8 using bit shift */
        /* Read the CSR register and extract the 8-bit field */
        uint32_t current_val = __RV_CSR_READ(CSR_MSHADGPRLVL1);
        uint8_t extracted_val = (uint8_t)((current_val >> bit_pos) & 0xFF);
        /* Extract the level from the upper nlbits of the 8-bit field */
        uint8_t level = (extracted_val >> (8 - nlbits));
        return level;
    }
#endif
}
 
__STATIC_INLINE void __ECLIC_SetShadowLevelReg(uint64_t value)
{
#if __RISCV_XLEN == 64
    __RV_CSR_WRITE(CSR_MSHADGPRLVL0, value);
#else
    __RV_CSR_WRITE(CSR_MSHADGPRLVL0, (uint32_t)value);
    __RV_CSR_WRITE(CSR_MSHADGPRLVL1, (uint32_t)(value >> 32));
#endif
}
 
__STATIC_INLINE uint64_t __ECLIC_GetShadowLevelReg(void)
{
#if __RISCV_XLEN == 64
    return __RV_CSR_READ(CSR_MSHADGPRLVL0);
#else
    uint64_t value = __RV_CSR_READ(CSR_MSHADGPRLVL1);
    value <<= 32;
    value |= __RV_CSR_READ(CSR_MSHADGPRLVL0);
    return value;
#endif
}
#endif
 
__STATIC_INLINE void __ECLIC_SetVector(IRQn_Type IRQn, rv_csr_t vector)
{
    unsigned long vec_base;
    vec_base = ((unsigned long)__RV_CSR_READ(CSR_MTVT));
    vec_base += ((unsigned long)IRQn) * sizeof(unsigned long);
    (* (unsigned long *) vec_base) = vector;
#if (defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1))
#if (defined(__CCM_PRESENT) && (__CCM_PRESENT == 1))
    MFlushDCacheLine((unsigned long)vec_base);
#endif
#endif
#if (defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1))
#if (defined(__CCM_PRESENT) && (__CCM_PRESENT == 1))
    MInvalICacheLine((unsigned long)vec_base);
#else
    __FENCE_I();
#endif
#endif
}
 
__STATIC_FORCEINLINE rv_csr_t __ECLIC_GetVector(IRQn_Type IRQn)
{
#if __RISCV_XLEN == 32
    return (*(uint32_t *)(__RV_CSR_READ(CSR_MTVT) + IRQn * 4));
#elif __RISCV_XLEN == 64
    return (*(uint64_t *)(__RV_CSR_READ(CSR_MTVT) + IRQn * 8));
#else // TODO Need cover for XLEN=128 case in future
    return (*(uint64_t *)(__RV_CSR_READ(CSR_MTVT) + IRQn * 8));
#endif
}
 
#if defined(__SMODE_PRESENT) && (__SMODE_PRESENT == 1)
 
__STATIC_FORCEINLINE void __ECLIC_SetModeIRQ(IRQn_Type IRQn, uint32_t mode)
{
    /*
     * only 1 or 3 can be assigned to mode in one step.the default value of mode is 3,
     * which can't be clear to 0 firstly, then OR it to 1
     */
    ECLIC->CTRL[IRQn].INTATTR = (uint8_t)(mode << CLIC_INTATTR_MODE_Pos) + \
        (ECLIC->CTRL[IRQn].INTATTR & (~CLIC_INTATTR_MODE_Msk));
}
 
__STATIC_FORCEINLINE void __ECLIC_SetSth(uint8_t sth)
{
    ECLIC->STH = sth;
}
 
__STATIC_FORCEINLINE uint8_t __ECLIC_GetSth(void)
{
    return (ECLIC->STH);
}
 
__STATIC_FORCEINLINE void __ECLIC_SetPendingIRQ_S(IRQn_Type IRQn)
{
    ECLIC->SCTRL[IRQn].INTIP |= CLIC_INTIP_IP_Msk;
}
 
__STATIC_FORCEINLINE int32_t __ECLIC_GetPendingIRQ_S(IRQn_Type IRQn)
{
    return ((uint32_t)(ECLIC->SCTRL[IRQn].INTIP) & CLIC_INTIP_IP_Msk);
}
 
__STATIC_FORCEINLINE void __ECLIC_ClearPendingIRQ_S(IRQn_Type IRQn)
{
    ECLIC->SCTRL[IRQn].INTIP &= ~CLIC_INTIP_IP_Msk;
}
 
__STATIC_FORCEINLINE void __ECLIC_SetTrigIRQ_S(IRQn_Type IRQn, uint32_t trig)
{
    uint8_t temp = ECLIC->SCTRL[IRQn].INTATTR;
 
    ECLIC->SCTRL[IRQn].INTATTR = (temp & ~CLIC_INTATTR_TRIG_Msk) | \
                                 ((uint8_t)(trig << CLIC_INTATTR_TRIG_Pos));
}
 
__STATIC_FORCEINLINE uint8_t __ECLIC_GetTrigIRQ_S(IRQn_Type IRQn)
{
    return ((uint8_t)(((ECLIC->SCTRL[IRQn].INTATTR) & CLIC_INTATTR_TRIG_Msk) >> CLIC_INTATTR_TRIG_Pos));
}
 
 
__STATIC_FORCEINLINE void __ECLIC_SetShvIRQ_S(IRQn_Type IRQn, uint32_t shv)
{
    uint8_t temp = ECLIC->SCTRL[IRQn].INTATTR;
 
    ECLIC->SCTRL[IRQn].INTATTR = (temp & ~CLIC_INTATTR_SHV_Msk) | \
                                 ((uint8_t)(shv << CLIC_INTATTR_SHV_Pos));
}
 
__STATIC_FORCEINLINE uint8_t __ECLIC_GetShvIRQ_S(IRQn_Type IRQn)
{
    return ((uint8_t)(((ECLIC->SCTRL[IRQn].INTATTR) & CLIC_INTATTR_SHV_Msk) >> CLIC_INTATTR_SHV_Pos));
}
 
__STATIC_FORCEINLINE void __ECLIC_SetCtrlIRQ_S(IRQn_Type IRQn, uint8_t intctrl)
{
    ECLIC->SCTRL[IRQn].INTCTRL = intctrl;
}
 
__STATIC_FORCEINLINE uint8_t __ECLIC_GetCtrlIRQ_S(IRQn_Type IRQn)
{
    return (ECLIC->SCTRL[IRQn].INTCTRL);
}
 
__STATIC_INLINE void __ECLIC_SetLevelIRQ_S(IRQn_Type IRQn, uint8_t lvl_abs)
{
    uint8_t nlbits = __ECLIC_GetCfgNlbits();
    uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
 
    if (nlbits == 0) {
        return;
    }
 
    if (nlbits > intctlbits) {
        nlbits = intctlbits;
    }
    uint8_t maxlvl = ((1UL << nlbits) - 1);
    if (lvl_abs > maxlvl) {
        lvl_abs = maxlvl;
    }
    uint8_t lvl = lvl_abs << (ECLIC_MAX_NLBITS - nlbits);
    uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ_S(IRQn);
    cur_ctrl = cur_ctrl << nlbits;
    cur_ctrl = cur_ctrl >> nlbits;
    __ECLIC_SetCtrlIRQ_S(IRQn, (cur_ctrl | lvl));
}
 
 
__STATIC_INLINE uint8_t __ECLIC_GetLevelIRQ_S(IRQn_Type IRQn)
{
    uint8_t nlbits = __ECLIC_GetCfgNlbits();
    uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
 
    if (nlbits == 0) {
        return 0;
    }
 
    if (nlbits > intctlbits) {
        nlbits = intctlbits;
    }
    uint8_t intctrl = __ECLIC_GetCtrlIRQ_S(IRQn);
    uint8_t lvl_abs = intctrl >> (ECLIC_MAX_NLBITS - nlbits);
    return lvl_abs;
}
 
__STATIC_INLINE void __ECLIC_SetPriorityIRQ_S(IRQn_Type IRQn, uint8_t pri)
{
    uint8_t nlbits = __ECLIC_GetCfgNlbits();
    uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
    if (nlbits < intctlbits) {
        uint8_t maxpri = ((1UL << (intctlbits - nlbits)) - 1);
        if (pri > maxpri) {
            pri = maxpri;
        }
        pri = pri << (ECLIC_MAX_NLBITS - intctlbits);
        uint8_t mask = ((uint8_t)(-1)) >> intctlbits;
        pri = pri | mask;
        uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ_S(IRQn);
        cur_ctrl = cur_ctrl >> (ECLIC_MAX_NLBITS - nlbits);
        cur_ctrl = cur_ctrl << (ECLIC_MAX_NLBITS - nlbits);
        __ECLIC_SetCtrlIRQ_S(IRQn, (cur_ctrl | pri));
    }
}
 
__STATIC_INLINE uint8_t __ECLIC_GetPriorityIRQ_S(IRQn_Type IRQn)
{
    uint8_t nlbits = __ECLIC_GetCfgNlbits();
    uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
    if (nlbits < intctlbits) {
        uint8_t cur_ctrl = __ECLIC_GetCtrlIRQ_S(IRQn);
        uint8_t pri = cur_ctrl << nlbits;
        pri = pri >> nlbits;
        pri = pri >> (ECLIC_MAX_NLBITS - intctlbits);
        return pri;
    } else {
        return 0;
    }
}
 
__STATIC_FORCEINLINE void __ECLIC_EnableIRQ_S(IRQn_Type IRQn)
{
    ECLIC->SCTRL[IRQn].INTIE |= CLIC_INTIE_IE_Msk;
}
 
__STATIC_FORCEINLINE uint8_t __ECLIC_GetEnableIRQ_S(IRQn_Type IRQn)
{
    return ((uint8_t) (ECLIC->SCTRL[IRQn].INTIE) & CLIC_INTIE_IE_Msk);
}
 
__STATIC_FORCEINLINE void __ECLIC_DisableIRQ_S(IRQn_Type IRQn)
{
    ECLIC->SCTRL[IRQn].INTIE &= ~CLIC_INTIE_IE_Msk;
}
 
__STATIC_INLINE void __ECLIC_SetVector_S(IRQn_Type IRQn, rv_csr_t vector)
{
    volatile unsigned long vec_base;
    vec_base = ((unsigned long)__RV_CSR_READ(CSR_STVT));
    vec_base += ((unsigned long)IRQn) * sizeof(unsigned long);
    (* (unsigned long *) vec_base) = vector;
#if (defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1))
#if (defined(__CCM_PRESENT) && (__CCM_PRESENT == 1))
    SFlushDCacheLine((unsigned long)vec_base);
#endif
#endif
#if (defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1))
#if (defined(__CCM_PRESENT) && (__CCM_PRESENT == 1))
    SInvalICacheLine((unsigned long)vec_base);
#else
    __FENCE_I();
#endif
#endif
}
 
__STATIC_FORCEINLINE rv_csr_t __ECLIC_GetVector_S(IRQn_Type IRQn)
{
#if __RISCV_XLEN == 32
    return (*(uint32_t *)(__RV_CSR_READ(CSR_STVT) + IRQn * 4));
#elif __RISCV_XLEN == 64
    return (*(uint64_t *)(__RV_CSR_READ(CSR_STVT) + IRQn * 8));
#else // TODO Need cover for XLEN=128 case in future
    return (*(uint64_t *)(__RV_CSR_READ(CSR_STVT) + IRQn * 8));
#endif
}
 
#if __ECLIC_VER == 2
 
__STATIC_FORCEINLINE void __ECLIC_EnableShadow_S(void)
{
    __RV_CSR_SET(CSR_SECLIC_CTL, SECLIC_CTL_SHADOW_EN);
}
 
__STATIC_FORCEINLINE void __ECLIC_DisableShadow_S(void)
{
    __RV_CSR_CLEAR(CSR_SECLIC_CTL, SECLIC_CTL_SHADOW_EN);
}
 
__STATIC_INLINE void __ECLIC_SetShadowLevel_S(unsigned long idx, uint8_t level)
{
    /* Check if idx is valid (0-7) */
    if (idx > 7) {
        return;
    }
 
    uint8_t nlbits = (uint8_t)__ECLIC_GetCfgNlbits();
    /* Limit the level value to the available number of bits */
    uint8_t max_level = (1U << nlbits) - 1;
    if (level > max_level) {
        level = max_level;
    }
 
    /* Position the level value in the upper nlbits of the 8-bit field and set the low (8-nlbits) bits to 1 */
    uint8_t level_shifted = (uint8_t)((level << (8 - nlbits)) | ((1U << (8 - nlbits)) - 1));
 
#if __RISCV_XLEN == 64
    /* For RV64, all 8 shadow registers are in CSR_SSHADGPRLVL0 */
    /* Calculate the bit position for the 8-bit field of the specified index */
    uint32_t bit_pos = idx << 3;  /* idx * 8 using bit shift */
    /* Create mask to clear the 8-bit field for the specified index */
    uint64_t mask = (uint64_t)0xFFUL << bit_pos;
    /* Read, modify, and write the CSR register */
    uint64_t current_val = __RV_CSR_READ(CSR_SSHADGPRLVL0);
    current_val = (current_val & ~mask) | (((uint64_t)level_shifted) << bit_pos);
    __RV_CSR_WRITE(CSR_SSHADGPRLVL0, current_val);
#else
    /* For RV32, calculate bit position and select appropriate register */
    if (idx < 4) {
        /* Shadow registers 1-4 are in CSR_SSHADGPRLVL0 */
        uint32_t bit_pos = idx << 3;  /* idx * 8 using bit shift */
        uint32_t mask = 0xFFUL << bit_pos;
        uint32_t current_val = __RV_CSR_READ(CSR_SSHADGPRLVL0);
        current_val = (current_val & ~mask) | (((uint32_t)level_shifted) << bit_pos);
        __RV_CSR_WRITE(CSR_SSHADGPRLVL0, current_val);
    } else {
        /* Shadow registers 5-8 are in CSR_SSHADGPRLVL1 */
        uint32_t bit_pos = (idx - 4) << 3;  /* (idx - 4) * 8 using bit shift */
        uint32_t mask = 0xFFUL << bit_pos;
        uint32_t current_val = __RV_CSR_READ(CSR_SSHADGPRLVL1);
        current_val = (current_val & ~mask) | (((uint32_t)level_shifted) << bit_pos);
        __RV_CSR_WRITE(CSR_SSHADGPRLVL1, current_val);
    }
#endif
}
 
__STATIC_INLINE uint8_t __ECLIC_GetShadowLevel_S(unsigned long idx)
{
    /* Check if idx is valid (0-7) */
    if (idx > 7) {
        return 0;
    }
 
    uint8_t nlbits = (uint8_t)__ECLIC_GetCfgNlbits();
 
#if __RISCV_XLEN == 64
    /* For RV64, all 8 shadow registers are in CSR_SSHADGPRLVL0 */
    /* Calculate the bit position for the 8-bit field of the specified index */
    uint32_t bit_pos = idx << 3;  /* idx * 8 using bit shift */
    /* Read the CSR register and extract the 8-bit field */
    uint64_t current_val = __RV_CSR_READ(CSR_SSHADGPRLVL0);
    uint8_t extracted_val = (uint8_t)((current_val >> bit_pos) & 0xFF);
    /* Extract the level from the upper nlbits of the 8-bit field */
    uint8_t level = (extracted_val >> (8 - nlbits));
    return level;
#else
    /* For RV32, calculate bit position and select appropriate register */
    if (idx < 4) {
        /* Shadow registers 1-4 are in CSR_SSHADGPRLVL0 */
        uint32_t bit_pos = idx << 3;  /* idx * 8 using bit shift */
        /* Read the CSR register and extract the 8-bit field */
        uint32_t current_val = __RV_CSR_READ(CSR_SSHADGPRLVL0);
        uint8_t extracted_val = (uint8_t)((current_val >> bit_pos) & 0xFF);
        /* Extract the level from the upper nlbits of the 8-bit field */
        uint8_t level = (extracted_val >> (8 - nlbits));
        return level;
    } else {
        /* Shadow registers 5-8 are in CSR_SSHADGPRLVL1 */
        uint32_t bit_pos = (idx - 4) << 3;  /* (idx - 4) * 8 using bit shift */
        /* Read the CSR register and extract the 8-bit field */
        uint32_t current_val = __RV_CSR_READ(CSR_SSHADGPRLVL1);
        uint8_t extracted_val = (uint8_t)((current_val >> bit_pos) & 0xFF);
        /* Extract the level from the upper nlbits of the 8-bit field */
        uint8_t level = (extracted_val >> (8 - nlbits));
        return level;
    }
#endif
}
 
__STATIC_INLINE void __ECLIC_SetShadowLevelReg_S(uint64_t value)
{
#if __RISCV_XLEN == 64
    __RV_CSR_WRITE(CSR_SSHADGPRLVL0, value);
#else
    __RV_CSR_WRITE(CSR_SSHADGPRLVL0, (uint32_t)value);
    __RV_CSR_WRITE(CSR_SSHADGPRLVL1, (uint32_t)(value >> 32));
#endif
}
 
__STATIC_INLINE uint64_t __ECLIC_GetShadowLevelReg_S(void)
{
#if __RISCV_XLEN == 64
    return __RV_CSR_READ(CSR_SSHADGPRLVL0);
#else
    uint64_t value = __RV_CSR_READ(CSR_SSHADGPRLVL1);
    value <<= 32;
    value |= __RV_CSR_READ(CSR_SSHADGPRLVL0);
    return value;
#endif
}
 
#endif
 
#endif /* defined(__SMODE_PRESENT) && (__SMODE_PRESENT == 1) */
 
__STATIC_FORCEINLINE void __set_exc_entry(rv_csr_t addr)
{
    addr &= (rv_csr_t)(~0x3F);
    addr |= ECLIC_MODE_MTVEC_Msk;
    __RV_CSR_WRITE(CSR_MTVEC, addr);
}
 
__STATIC_FORCEINLINE rv_csr_t __get_exc_entry(void)
{
    unsigned long addr = __RV_CSR_READ(CSR_MTVEC);
    return (addr & ~ECLIC_MODE_MTVEC_Msk);
}
 
__STATIC_INLINE void __set_nonvec_entry(rv_csr_t addr)
{
    if (__RV_CSR_READ(CSR_MTVT2) & 0x1) {
        __RV_CSR_WRITE(CSR_MTVT2, addr | 0x01);
    } else {
        addr &= (rv_csr_t)(~0x3F);
        addr |= ECLIC_MODE_MTVEC_Msk;
        __RV_CSR_WRITE(CSR_MTVEC, addr);
    }
}
 
__STATIC_INLINE rv_csr_t __get_nonvec_entry(void)
{
    if (__RV_CSR_READ(CSR_MTVT2) & 0x1) {
        return __RV_CSR_READ(CSR_MTVT2) & (~(rv_csr_t)(0x1));
    } else {
        rv_csr_t addr = __RV_CSR_READ(CSR_MTVEC);
        return (addr & ~ECLIC_MODE_MTVEC_Msk);
    }
}
 
__STATIC_FORCEINLINE rv_csr_t __get_nmi_entry(void)
{
    return __RV_CSR_READ(CSR_MNVEC);
}
 
/* NOTE: SSUBM CSR is introduced in ECLIC v2, without this the S_Mode vector interrupt nesting
 * and non-vector interrupt nesting will not work properly */
#if __ECLIC_VER == 2
#define SAVE_SSUBM_VAR()        rv_csr_t __ssubm = __RV_CSR_READ(CSR_SSUBM);
#define RESTORE_SSUBM_VAR()     __RV_CSR_WRITE(CSR_SSUBM, __ssubm);
#else
#define SAVE_SSUBM_VAR()
#define RESTORE_SSUBM_VAR()
#endif
 
#define SAVE_IRQ_CSR_CONTEXT()                                              \
        rv_csr_t __mcause = __RV_CSR_READ(CSR_MCAUSE);                      \
        rv_csr_t __mepc = __RV_CSR_READ(CSR_MEPC);                          \
        rv_csr_t __msubm = __RV_CSR_READ(CSR_MSUBM);                        \
        __enable_irq();
 
#define SAVE_IRQ_CSR_CONTEXT_S()                                            \
        rv_csr_t __scause = __RV_CSR_READ(CSR_SCAUSE);                      \
        rv_csr_t __sepc = __RV_CSR_READ(CSR_SEPC);                          \
        SAVE_SSUBM_VAR();                                                   \
        __enable_irq_s();
 
 
#define RESTORE_IRQ_CSR_CONTEXT()                                           \
        __disable_irq();                                                    \
        __RV_CSR_WRITE(CSR_MSUBM, __msubm);                                 \
        __RV_CSR_WRITE(CSR_MEPC, __mepc);                                   \
        __RV_CSR_WRITE(CSR_MCAUSE, __mcause);
 
#define RESTORE_IRQ_CSR_CONTEXT_S()                                         \
        __disable_irq_s();                                                  \
        RESTORE_SSUBM_VAR();                                                \
        __RV_CSR_WRITE(CSR_SEPC, __sepc);                                   \
        __RV_CSR_WRITE(CSR_SCAUSE, __scause);
 /* End of Doxygen Group NMSIS_Core_IntExc */
 
#endif /* defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1) */
 
#ifdef __cplusplus
}
#endif
#endif /* __CORE_FEATURE_ECLIC__ */