Access to the structure of ECLIC Memory Map, which is compatible with TEE. More...

Data Fields
__IOM uint8_t	CFG
	Offset: 0x000 (R/W) CLIC configuration register. More...

__IM uint8_t	RESERVED0 [3]

__IM uint32_t	INFO
	Offset: 0x004 (R/ ) CLIC information register. More...

__IM uint8_t	RESERVED1

__IOM uint8_t	STH
	Offset: 0x009 (R/W ) CLIC supervisor mode interrupt-level threshold. More...

__IM uint8_t	RESERVED3

__IOM uint8_t	MTH
	Offset: 0x00B(R/W) CLIC machine mode interrupt-level threshold. More...

uint32_t	RESERVED4 [1021]

CLIC_CTRL_Type	CTRL [1024]
	Offset: 0x1000 (R/W) CLIC machine mode register structure for INTIP, INTIE, INTATTR, INTCTL. More...

__IM uint32_t	RESERVED5 [2]

__IM uint8_t	RESERVED6

__IOM uint8_t	SSTH
	Offset: 0x2009 (R) CLIC supervisor mode threshold register, which is a mirror to mintthresh.sth. More...

__IM uint8_t	RESERVED7

__IM uint8_t	RESERVED8

__IM uint32_t	RESERVED9 [1021]

CLIC_CTRL_Type	SCTRL [1024]
	Offset: 0x3000 (R/W) CLIC supervisor mode register structure for INTIP, INTIE, INTATTR, INTCTL. More...

Detailed Description

Access to the structure of ECLIC Memory Map, which is compatible with TEE.

Definition at line 93 of file core_feature_eclic.h.

Field Documentation

◆ CFG

__IOM uint8_t CLIC_Type::CFG

Offset: 0x000 (R/W) CLIC configuration register.

Definition at line 94 of file core_feature_eclic.h.

◆ CTRL

CLIC_CTRL_Type CLIC_Type::CTRL[1024]

Offset: 0x1000 (R/W) CLIC machine mode register structure for INTIP, INTIE, INTATTR, INTCTL.

Definition at line 107 of file core_feature_eclic.h.

◆ INFO

__IM uint32_t CLIC_Type::INFO

Offset: 0x004 (R/ ) CLIC information register.

Definition at line 96 of file core_feature_eclic.h.

◆ MTH

__IOM uint8_t CLIC_Type::MTH

Offset: 0x00B(R/W) CLIC machine mode interrupt-level threshold.

Definition at line 104 of file core_feature_eclic.h.

◆ RESERVED0

__IM uint8_t CLIC_Type::RESERVED0[3]

Definition at line 95 of file core_feature_eclic.h.

◆ RESERVED1

__IM uint8_t CLIC_Type::RESERVED1

Definition at line 97 of file core_feature_eclic.h.

◆ RESERVED3

__IM uint8_t CLIC_Type::RESERVED3

Definition at line 103 of file core_feature_eclic.h.

◆ RESERVED4

uint32_t CLIC_Type::RESERVED4[1021]

Definition at line 105 of file core_feature_eclic.h.

◆ RESERVED5

__IM uint32_t CLIC_Type::RESERVED5[2]

Definition at line 108 of file core_feature_eclic.h.

◆ RESERVED6

__IM uint8_t CLIC_Type::RESERVED6

Definition at line 109 of file core_feature_eclic.h.

◆ RESERVED7

__IM uint8_t CLIC_Type::RESERVED7

Definition at line 111 of file core_feature_eclic.h.

◆ RESERVED8

__IM uint8_t CLIC_Type::RESERVED8

Definition at line 112 of file core_feature_eclic.h.

◆ RESERVED9

__IM uint32_t CLIC_Type::RESERVED9[1021]

Definition at line 113 of file core_feature_eclic.h.

◆ SCTRL

CLIC_CTRL_Type CLIC_Type::SCTRL[1024]

Offset: 0x3000 (R/W) CLIC supervisor mode register structure for INTIP, INTIE, INTATTR, INTCTL.

Definition at line 114 of file core_feature_eclic.h.

◆ SSTH

__IOM uint8_t CLIC_Type::SSTH

Offset: 0x2009 (R) CLIC supervisor mode threshold register, which is a mirror to mintthresh.sth.

Definition at line 110 of file core_feature_eclic.h.

◆ STH

__IOM uint8_t CLIC_Type::STH

Offset: 0x009 (R/W ) CLIC supervisor mode interrupt-level threshold.

Definition at line 99 of file core_feature_eclic.h.

Data Fields