core_feature_cidu.h

/*
 * Copyright (c) 2019 Nuclei Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#ifndef __CORE_FEATURE_CIDU_H__
#define __CORE_FEATURE_CIDU_H__
/*
 * CIDU Feature Configuration Macro:
 * 1. __CIDU_PRESENT:  Define whether Cluster Interrupt Distribution Unit is present or not.
 *   * 0: Not present
 *   * 1: Present
 * 2. __CIDU_BASEADDR:  Define the base address of the CIDU.
 */
#ifdef __cplusplus
extern "C" {
#endif
 
#include "core_feature_base.h"
 
#if defined(__CIDU_PRESENT) && (__CIDU_PRESENT == 1)
 
/* ##########################  CIDU functions  #################################### */
#ifndef __CIDU_BASEADDR
/* Base address of CIDU(__CIDU_BASEADDR) should be defined in <Device.h> */
#error "__CIDU_BASEADDR is not defined, please check!"
#endif
 
#define CIDU_BASE                                __CIDU_BASEADDR
#define CIDU_RECEIVE_INTERRUPT_EN(core_id)       (0x1UL << core_id)   
#define CIDU_CORE_INT_STATUS_OFS      0x0        
#define CIDU_SEMAPHORE_OFS            0x80       
#define CIDU_ICI_SHADOW_OFS           0x3FFC     
#define CIDU_INT_INDICATOR_OFS        0x4000     
#define CIDU_INT_MASK_OFS             0x8000     
#define CIDU_CORE_NUM_OFS             0xC084     
#define CIDU_INT_NUM_OFS              0xC090     
#define CIDU_CORE_INT_STATUS_ADDR(n)  (unsigned long)((CIDU_BASE) + (CIDU_CORE_INT_STATUS_OFS) + ((n) << 2))    
#define CIDU_SEMAPHORE_ADDR(n)        (unsigned long)((CIDU_BASE) + (CIDU_SEMAPHORE_OFS) + ((n) << 2))          
#define CIDU_ICI_SHADOW_ADDR          (unsigned long)((CIDU_BASE) + (CIDU_ICI_SHADOW_OFS))                      
#define CIDU_INT_INDICATOR_ADDR(n)    (unsigned long)((CIDU_BASE) + (CIDU_INT_INDICATOR_OFS) + ((n) << 2))      
#define CIDU_INT_MASK_ADDR(n)         (unsigned long)((CIDU_BASE) + (CIDU_INT_MASK_OFS) + ((n) << 2))           
#define CIDU_CORE_NUM_ADDR            (unsigned long)((CIDU_BASE) + (CIDU_CORE_NUM_OFS))                        
#define CIDU_INT_NUM_ADDR             (unsigned long)((CIDU_BASE) + (CIDU_INT_NUM_OFS))                         
/* SEND_CORE_ID position in ICI_SHADOW_REG register */
#define CIDU_ICI_SEND_CORE_ID_POS     16
 
__STATIC_FORCEINLINE uint32_t CIDU_GetCoreNum(void)
{
    uint32_t val;
    uint32_t* addr = (uint32_t*)CIDU_CORE_NUM_ADDR;
 
    val = __LW(addr);
    return val;
}
 
__STATIC_FORCEINLINE uint32_t CIDU_GetIntNum(void)
{
    uint32_t val;
    uint32_t* addr = (uint32_t*)CIDU_INT_NUM_ADDR;
 
    val = __LW(addr);
    return val;
} /* End of Doxygen Group NMSIS_Core_CIDU */
 
__STATIC_FORCEINLINE void CIDU_BroadcastExtInterrupt(uint32_t int_id, uint32_t to_cores)
{
    uint32_t* addr = (uint32_t*)CIDU_INT_INDICATOR_ADDR(int_id);
 
    __SW(addr, (uint32_t)to_cores);
}
 
__STATIC_FORCEINLINE uint32_t CIDU_GetBroadcastModeStatus(uint32_t int_id)
{
    uint32_t val = 0;
    uint32_t* addr = (uint32_t*)CIDU_INT_INDICATOR_ADDR(int_id);
 
    val = __LW(addr);
    return val;
}
 
__STATIC_INLINE long CIDU_SetFirstClaimMode(uint32_t int_id, uint32_t core_id)
{
    uint32_t val = 0;
    uint32_t* addr = (uint32_t*)CIDU_INT_MASK_ADDR(int_id);
    uint32_t mask = 1UL << core_id;
 
    __SW(addr, mask);
    val = __LW(addr);
    if (mask == val) {
        return 0;
    }
    return -1;
}
 
__STATIC_FORCEINLINE void CIDU_ResetFirstClaimMode(uint32_t int_id)
{
    uint32_t val = 0;
    uint32_t* addr = (uint32_t*)CIDU_INT_MASK_ADDR(int_id);
 
    /* clear by writing all 1 */
    __SW(addr, 0xFFFFFFFF);
}
 
__STATIC_FORCEINLINE uint32_t CIDU_GetClaimStatus(uint32_t int_id)
{
    uint32_t val = 0;
    uint32_t* addr = (uint32_t*)CIDU_INT_MASK_ADDR(int_id);
 
    val = __LW(addr);
    return val;
} /* End of Doxygen Group NMSIS_Core_Distribute_Interrupt */
 
__STATIC_FORCEINLINE void CIDU_TriggerInterCoreInt(uint32_t send_core_id, uint32_t recv_core_id)
{
    uint32_t val = 0;
    uint32_t* addr = (uint32_t*)CIDU_ICI_SHADOW_ADDR;
 
    val = (uint32_t)(send_core_id << CIDU_ICI_SEND_CORE_ID_POS) | (uint32_t)(recv_core_id);
    __SW(addr, (uint32_t)val);
}
 
__STATIC_FORCEINLINE uint32_t CIDU_QueryCoreIntSenderMask(uint32_t recv_core_id)
{
    uint32_t val = 0;
    uint32_t* addr = (uint32_t*)CIDU_CORE_INT_STATUS_ADDR(recv_core_id);
 
    val = __LW(addr);
    return val;
}
 
__STATIC_FORCEINLINE void CIDU_ClearInterCoreIntReq(uint32_t send_core_id, uint32_t recv_core_id)
{
    uint32_t val = 0;
    uint32_t* addr = (uint32_t*)CIDU_CORE_INT_STATUS_ADDR(recv_core_id);
 
    val = (uint32_t)(1UL << send_core_id);
    __SW(addr, val);
} /* End of Doxygen Group NMSIS_Core_ICI */
 
__STATIC_FORCEINLINE uint32_t CIDU_GetSemaphoreStatus(uint32_t semph_n)
{
    uint32_t val;
    uint32_t* addr = (uint32_t*)CIDU_SEMAPHORE_ADDR(semph_n);
 
    val = __LW(addr);
    return val;
}
 
__STATIC_INLINE long CIDU_CheckSemaphoreAcquired(uint32_t semph_n, uint32_t core_id)
{
    uint32_t val;
    val = CIDU_GetSemaphoreStatus(semph_n);
    if (core_id != val) {
        return -1;
    }
    return 0;
}
 
__STATIC_INLINE long CIDU_AcquireSemaphore(uint32_t semph_n, uint32_t core_id)
{
    long semaphore_status = -1;
    uint32_t* addr = (uint32_t*)CIDU_SEMAPHORE_ADDR(semph_n);
 
    __SW(addr, core_id);
    semaphore_status = CIDU_CheckSemaphoreAcquired(semph_n, core_id);
    return semaphore_status;
}
 
__STATIC_INLINE void CIDU_AcquireSemaphore_Block(uint32_t semph_n, uint32_t core_id)
{
    int32_t semaphore_status = -1;
 
    while(0 != semaphore_status) {
        semaphore_status = CIDU_AcquireSemaphore(semph_n, core_id);
    }
}
 
__STATIC_FORCEINLINE void CIDU_ReleaseSemaphore(uint32_t semph_n)
{
    uint32_t* addr = (uint32_t*)CIDU_SEMAPHORE_ADDR(semph_n);
 
    /* Release by writing all 1 */
    __SW(addr, 0xFFFFFFFF);
} /* End of Doxygen Group NMSIS_Core_Semaphore */
 /* End of Doxygen Group NMSIS_Core_CIDU_Functions */
#endif /* defined(__CIDU_PRESENT) && (__CIDU_PRESENT == 1) */
 
#ifdef __cplusplus
}
#endif
#endif /* __CORE_FEATURE_CIDU_H__ */