NMSIS-Core  Version 1.5.0
NMSIS-Core support for Nuclei processor-based devices
core_feature_timer.h
1 /*
2  * Copyright (c) 2019 Nuclei Limited. All rights reserved.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Licensed under the Apache License, Version 2.0 (the License); you may
7  * not use this file except in compliance with the License.
8  * You may obtain a copy of the License at
9  *
10  * www.apache.org/licenses/LICENSE-2.0
11  *
12  * Unless required by applicable law or agreed to in writing, software
13  * distributed under the License is distributed on an AS IS BASIS, WITHOUT
14  * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
15  * See the License for the specific language governing permissions and
16  * limitations under the License.
17  */
18 #ifndef __CORE_FEATURE_TIMER_H__
19 #define __CORE_FEATURE_TIMER_H__
24 /*
25  * System Timer Feature Configuration Macro:
26  * 1. __SYSTIMER_PRESENT: Must, Define whether Private System Timer is present or not.
27  * * 0: Not present
28  * * 1: Present
29  * 2. __SYSTIMER_BASEADDR: Must, Define the base address of the System Timer.
30  * 3. __SYSTIMER_HARTID: Optional, Define the system timer hart index of the cpu, important for case when cpu hartid and cpu hart index are different, only set it if your cpu is single core.
31  */
32 #ifdef __cplusplus
33 extern "C" {
34 #endif
35 
36 #include "core_feature_base.h"
37 
38 #if defined(__SYSTIMER_PRESENT) && (__SYSTIMER_PRESENT == 1)
55 typedef struct {
56 #if defined(CPU_SERIES) && CPU_SERIES == 100
57  __IOM uint32_t MTIMER;
58  __IOM uint32_t RESERVED1;
59  __IOM uint32_t MTIMERCMP;
60  __IOM uint32_t RESERVED2;
61 #else
62  __IOM uint64_t MTIMER;
63  __IOM uint64_t MTIMERCMP;
64 #endif
65  __IOM uint32_t RESERVED0[0x3F7];
66  __IOM uint32_t MTIME_SRW_CTRL;
67  __IOM uint32_t MSFTRST;
68  __IOM uint32_t SSIP;
69  __IOM uint32_t MTIMECTL;
70  __IOM uint32_t MSIP;
72 
73 /* Timer Control / Status Register Definitions */
74 #define SysTimer_MTIMECTL_TIMESTOP_Pos 0U
75 #define SysTimer_MTIMECTL_TIMESTOP_Msk (1UL << SysTimer_MTIMECTL_TIMESTOP_Pos)
76 #define SysTimer_MTIMECTL_CMPCLREN_Pos 1U
77 #define SysTimer_MTIMECTL_CMPCLREN_Msk (1UL << SysTimer_MTIMECTL_CMPCLREN_Pos)
78 #define SysTimer_MTIMECTL_CLKSRC_Pos 2U
79 #define SysTimer_MTIMECTL_CLKSRC_Msk (1UL << SysTimer_MTIMECTL_CLKSRC_Pos)
80 #define SysTimer_MTIMECTL_HDBG_Pos 3U
81 #define SysTimer_MTIMECTL_HDBG_Msk (1UL << SysTimer_MTIMECTL_HDBG_Pos)
82 #define SysTimer_MTIMECTL_MTIME_SRC_Pos 4U
83 #define SysTimer_MTIMECTL_MTIME_SRC_Msk (1UL << SysTimer_MTIMECTL_MTIME_SRC_Pos)
85 #define SysTimer_MSIP_MSIP_Pos 0U
86 #define SysTimer_MSIP_MSIP_Msk (1UL << SysTimer_MSIP_MSIP_Pos)
88 #define SysTimer_SSIP_SSIP_Pos 0U
89 #define SysTimer_SSIP_SSIP_Msk (1UL << SysTimer_SSIP_SSIP_Pos)
91 #define SysTimer_MTIME_SRW_CTRL_SRW_Pos 0U
92 #define SysTimer_MTIME_SRW_CTRL_SRW_Msk (1UL << SysTimer_MTIME_SRW_CTRL_SRW_Pos)
94 #if defined(CPU_SERIES) && CPU_SERIES == 100
95 #define SysTimer_MTIMER_Msk (0xFFFFFFFFUL)
96 #define SysTimer_MTIMERCMP_Msk (0xFFFFFFFFUL)
97 #else
98 #define SysTimer_MTIMER_Msk (0xFFFFFFFFFFFFFFFFULL)
99 #define SysTimer_MTIMERCMP_Msk (0xFFFFFFFFFFFFFFFFULL)
100 #endif
101 #define SysTimer_MTIMECTL_Msk (0xFFFFFFFFUL)
102 #define SysTimer_MSIP_Msk (0xFFFFFFFFUL)
103 #define SysTimer_MSFTRST_Msk (0xFFFFFFFFUL)
105 #define SysTimer_MSFRST_KEY (0x80000A5FUL)
107 #define SysTimer_CLINT_MSIP_OFS (0x1000UL)
108 #define SysTimer_CLINT_MTIMECMP_OFS (0x5000UL)
109 #define SysTimer_CLINT_MTIME_OFS (0xCFF8UL)
110 #define SysTimer_CLINT_SSIP_OFS (0xD000UL)
112 #ifndef __SYSTIMER_BASEADDR
113 /* Base address of SYSTIMER(__SYSTIMER_BASEADDR) should be defined in <Device.h> */
114 #error "__SYSTIMER_BASEADDR is not defined, please check!"
115 #endif
116 /* System Timer Memory mapping of Device */
117 #define SysTimer_BASE __SYSTIMER_BASEADDR
118 #define SysTimer ((SysTimer_Type *) SysTimer_BASE)
120 /* System Timer Clint register base */
121 #define SysTimer_CLINT_MSIP_BASE(hartid) (unsigned long)((SysTimer_BASE) + (SysTimer_CLINT_MSIP_OFS) + ((hartid) << 2))
122 #define SysTimer_CLINT_MTIMECMP_BASE(hartid) (unsigned long)((SysTimer_BASE) + (SysTimer_CLINT_MTIMECMP_OFS) + ((hartid) << 3))
123 #define SysTimer_CLINT_MTIME_BASE (unsigned long)((SysTimer_BASE) + (SysTimer_CLINT_MTIME_OFS))
124 #define SysTimer_CLINT_SSIP_BASE(hartid) (unsigned long)((SysTimer_BASE) + (SysTimer_CLINT_SSIP_OFS) + ((hartid) << 2))
125  /* end of group NMSIS_Core_SysTimer_Registers */
127 
128 /* ################################## SysTimer function ############################################ */
142 #ifndef __SYSTIMER_HARTID
143 #define SysTimer_GetHartID() (__get_hart_index())
144 #else
145 #define SysTimer_GetHartID() (__SYSTIMER_HARTID)
146 #endif
147 
148 #if defined(__SSTC_PRESENT) && (__SSTC_PRESENT == 1)
149 #ifndef __SYSTIMER_HARTID
150 #define SysTimer_GetHartID_S() (__get_hart_index_s())
151 #else
152 #define SysTimer_GetHartID_S() (__SYSTIMER_HARTID)
153 #endif
154 #endif
155 
166 {
167 #if (__RISCV_XLEN == 32) && !(defined(CPU_SERIES) && CPU_SERIES == 100)
168  uint8_t *addr;
169  addr = (uint8_t *)(&(SysTimer->MTIMER));
170  __SW(addr, 0); // prevent carry
171  __SW(addr + 4, (uint32_t)(value >> 32));
172  __SW(addr, (uint32_t)(value));
173 #else
174  SysTimer->MTIMER = value;
175 #endif
176 }
177 
188 {
189 #if (__RISCV_XLEN == 32) && !(defined(CPU_SERIES) && CPU_SERIES == 100)
190  volatile uint32_t high0, low, high;
191  uint64_t full;
192  uint8_t *addr;
193 
194  addr = (uint8_t *)(&(SysTimer->MTIMER));
195 
196  high0 = __LW(addr + 4);
197  low = __LW(addr);
198  high = __LW(addr + 4);
199  if (high0 != high) {
200  low = __LW(addr);
201  }
202  full = (((uint64_t)high) << 32) | low;
203  return full;
204 #else
205  return SysTimer->MTIMER;
206 #endif
207 }
208 
223 {
224 #if (defined(CPU_SERIES) && CPU_SERIES == 100)
225  SysTimer->MTIMERCMP = value;
226 #else
227  if (hartid == 0) {
228 #if __RISCV_XLEN == 32
229  uint8_t *addr;
230  addr = (uint8_t *)(&(SysTimer->MTIMERCMP));
231  __SW(addr, -1U); // prevent load > timecmp
232  __SW(addr + 4, (uint32_t)(value >> 32));
233  __SW(addr, (uint32_t)(value));
234 #else
235  SysTimer->MTIMERCMP = value;
236 #endif
237  } else {
238  uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MTIMECMP_BASE(hartid));
239 #if __RISCV_XLEN == 32
240  __SW(addr, -1U); // prevent load > timecmp
241  __SW(addr + 4, (uint32_t)(value >> 32));
242  __SW(addr, (uint32_t)value);
243 #else
244  __SD(addr, value);
245 #endif
246  }
247 #endif
248 }
249 
263 {
264 #if (defined(CPU_SERIES) && CPU_SERIES == 100)
265  SysTimer->MTIMERCMP = value;
266 #else
267  unsigned long hartid = SysTimer_GetHartID();
268  SysTimer_SetHartCompareValue(value, hartid);
269 #endif
270 }
271 
284 {
285 #if (defined(CPU_SERIES) && CPU_SERIES == 100)
286  return SysTimer->MTIMERCMP;
287 #else
288  if (hartid == 0) {
289  return SysTimer->MTIMERCMP;
290  } else {
291  uint64_t full;
292  uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MTIMECMP_BASE(hartid));
293 #if __RISCV_XLEN == 32
294  // MTIMECMP didn't increase
295  uint32_t high, low;
296 
297  high = __LW(addr + 4);
298  low = __LW(addr);
299  full = (((uint64_t)high) << 32) | low;
300 #else
301  full = __LD(addr);
302 #endif
303  return full;
304  }
305 #endif
306 }
307 
318 {
319 #if (defined(CPU_SERIES) && CPU_SERIES == 100)
320  return SysTimer->MTIMERCMP;
321 #else
322  unsigned long hartid = SysTimer_GetHartID();
323  return SysTimer_GetHartCompareValue(hartid);
324 #endif
325 }
326 
334 {
336 }
337 
345 {
347 }
348 
364 {
365  SysTimer->MTIMECTL = (mctl & SysTimer_MTIMECTL_Msk);
366 }
367 
377 {
378  return (SysTimer->MTIMECTL & SysTimer_MTIMECTL_Msk);
379 }
380 
392 __STATIC_FORCEINLINE void SysTimer_SetHartSWIRQ(unsigned long hartid)
393 {
394 #if (defined(CPU_SERIES) && CPU_SERIES == 100)
396 #else
397  if (hartid == 0) {
399  } else {
400  uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MSIP_BASE(hartid));
402  }
403 #endif
404 }
405 
416 {
417 #if (defined(CPU_SERIES) && CPU_SERIES == 100)
419 #else
420  unsigned long hartid = SysTimer_GetHartID();
421  SysTimer_SetHartSWIRQ(hartid);
422 #endif
423 }
424 
437 {
438 #if (defined(CPU_SERIES) && CPU_SERIES == 100)
440 #else
441  if (hartid == 0) {
443  } else {
444  uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MSIP_BASE(hartid));
445  __SW(addr, 0);
446  }
447 #endif
448 }
449 
460 {
461 #if (defined(CPU_SERIES) && CPU_SERIES == 100)
463 #else
464  unsigned long hartid = SysTimer_GetHartID();
465  SysTimer_ClearHartSWIRQ(hartid);
466 #endif
467 }
468 
483 __STATIC_FORCEINLINE uint32_t SysTimer_GetHartMsipValue(unsigned long hartid)
484 {
485 #if (defined(CPU_SERIES) && CPU_SERIES == 100)
486  return (uint32_t)(SysTimer->MSIP);
487 #else
488  if (hartid == 0) {
489  return (uint32_t)(SysTimer->MSIP);
490  } else {
491  uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MSIP_BASE(hartid));
492  return __LW(addr);
493  }
494 #endif
495 }
496 
510 {
511 #if (defined(CPU_SERIES) && CPU_SERIES == 100)
512  return (uint32_t)(SysTimer->MSIP);
513 #else
514  unsigned long hartid = SysTimer_GetHartID();
515  return SysTimer_GetHartMsipValue(hartid);
516 #endif
517 }
518 
529 __STATIC_FORCEINLINE void SysTimer_SetHartMsipValue(uint32_t msip, unsigned long hartid)
530 {
531 #if (defined(CPU_SERIES) && CPU_SERIES == 100)
532  SysTimer->MSIP = (msip);
533 #else
534  if (hartid == 0) {
535  SysTimer->MSIP = (msip);
536  } else {
537  uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MSIP_BASE(hartid));
538  __SW(addr, msip);
539  }
540 #endif
541 }
542 
551 {
552 #if (defined(CPU_SERIES) && CPU_SERIES == 100)
553  SysTimer->MSIP = (msip);
554 #else
555  unsigned long hartid = SysTimer_GetHartID();
556  SysTimer_SetHartMsipValue(msip, hartid);
557 #endif
558 }
559 
560 #if defined(__SSTC_PRESENT) && (__SSTC_PRESENT == 1)
574 {
575 #if __RISCV_XLEN == 32
576  __RV_CSR_WRITE(CSR_STIMECMP, -1U); // prevent load > timecmp
577  __RV_CSR_WRITE(CSR_STIMECMPH, (uint32_t)(value >> 32));
578  __RV_CSR_WRITE(CSR_STIMECMP, (uint32_t)value);
579 #else
581 #endif
582 }
583 
594 {
595  uint64_t full;
596 #if __RISCV_XLEN == 32
597  uint32_t high, low;
598 
601  full = (((uint64_t)high) << 32) | low;
602 #else
603  full = __RV_CSR_READ(CSR_STIMECMP);
604 #endif
605  return full;
606 }
607 
619 {
620  if (hartid == 0) {
622  } else {
623  uint8_t *addr = (uint8_t *)(SysTimer_CLINT_SSIP_BASE(hartid));
625  }
626 }
627 
638 {
639  unsigned long hartid = SysTimer_GetHartID_S();
640  SysTimer_SetHartSWIRQ_S(hartid);
641 }
642 
654 {
655  if (hartid == 0) {
657  } else {
658  uint8_t *addr = (uint8_t *)(SysTimer_CLINT_SSIP_BASE(hartid));
659  __SW(addr, 0);
660  }
661 }
662 
673 {
674  unsigned long hartid = SysTimer_GetHartID_S();
676 }
677 
691 __STATIC_FORCEINLINE uint32_t SysTimer_GetHartSsipValue(unsigned long hartid)
692 {
693  if (hartid == 0) {
694  return (uint32_t)(SysTimer->SSIP);
695  } else {
696  uint8_t *addr = (uint8_t *)(SysTimer_CLINT_SSIP_BASE(hartid));
697  return __LW(addr);
698  }
699 }
700 
714 {
715  unsigned long hartid = SysTimer_GetHartID_S();
716  return SysTimer_GetHartSsipValue(hartid);
717 }
718 
728 __STATIC_FORCEINLINE void SysTimer_SetHartSsipValue(uint32_t ssip, unsigned long hartid)
729 {
730  if (hartid == 0) {
731  SysTimer->SSIP = (ssip);
732  } else {
733  uint8_t *addr = (uint8_t *)(SysTimer_CLINT_SSIP_BASE(hartid));
734  __SW(addr, ssip);
735  }
736 }
737 
746 {
747  unsigned long hartid = SysTimer_GetHartID();
748  SysTimer_SetHartSsipValue(ssip, hartid);
749 }
750 
757 __STATIC_FORCEINLINE void SysTimer_SendIPI_S(unsigned long hartid)
758 {
759  uint8_t *addr = (uint8_t *)(SysTimer_CLINT_SSIP_BASE(hartid));
760  __SW(addr, 1);
761 }
762 
769 __STATIC_FORCEINLINE void SysTimer_ClearIPI_S(unsigned long hartid)
770 {
771  uint8_t *addr = (uint8_t *)(SysTimer_CLINT_SSIP_BASE(hartid));
772  __SW(addr, 0);
773 }
774 
783 {
785 #if __RISCV_XLEN == 32
787 #else
789 #endif
790 }
791 
799 {
801 #if __RISCV_XLEN == 32
803 #else
805 #endif
806 }
807 #endif
808 
820 {
821  SysTimer->MSFTRST = SysTimer_MSFRST_KEY;
822  // will reset cpu, never return
823  while (1);
824 }
825 
832 __STATIC_FORCEINLINE void SysTimer_SendIPI(unsigned long hartid)
833 {
834 #if (defined(CPU_SERIES) && CPU_SERIES == 100)
835  SysTimer->MSIP = 1;
836 #else
837  uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MSIP_BASE(hartid));
838  __SW(addr, 1);
839 #endif
840 }
841 
848 __STATIC_FORCEINLINE void SysTimer_ClearIPI(unsigned long hartid)
849 {
850 #if (defined(CPU_SERIES) && CPU_SERIES == 100)
851  SysTimer->MSIP = 0;
852 #else
853  uint8_t *addr = (uint8_t *)(SysTimer_CLINT_MSIP_BASE(hartid));
854  __SW(addr, 0);
855 #endif
856 }
857 
865 {
866  SysTimer->MTIME_SRW_CTRL &= ~SysTimer_MTIME_SRW_CTRL_SRW_Msk;
867 }
868 
876 {
877  SysTimer->MTIME_SRW_CTRL |= SysTimer_MTIME_SRW_CTRL_SRW_Msk;
878 }
879 
880 #if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
881 
907 {
908  rv_counter_t loadticks = SysTimer_GetLoadValue();
909  SysTimer_SetCompareValue(ticks + loadticks);
910 
911 #if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1)
915 #endif
916  return (0UL);
917 }
918 
946 __STATIC_INLINE uint32_t SysTick_HartConfig(rv_counter_t ticks, unsigned long hartid)
947 {
948  rv_counter_t loadticks = SysTimer_GetLoadValue();
949  SysTimer_SetHartCompareValue(ticks + loadticks, hartid);
950 
951 #if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1)
955 #endif
956  return (0UL);
957 }
958 
983 {
984  rv_counter_t cur_ticks = SysTimer_GetLoadValue();
985 
986  rv_counter_t reload_ticks = ticks + cur_ticks;
987 
988  SysTimer_SetCompareValue(reload_ticks);
989 
990  return (0UL);
991 }
992 
1018 __STATIC_INLINE uint32_t SysTick_HartReload(rv_counter_t ticks, unsigned long hartid)
1019 {
1020  rv_counter_t cur_ticks = SysTimer_GetLoadValue();
1021  rv_counter_t reload_ticks = ticks + cur_ticks;
1022 
1023  SysTimer_SetHartCompareValue(reload_ticks, hartid);
1024 
1025  return (0UL);
1026 }
1027 
1028 #if defined(__SSTC_PRESENT) && (__SSTC_PRESENT == 1)
1040 {
1041  rv_counter_t loadticks = __get_rv_time();
1042  SysTimer_SetCompareValue_S(ticks + loadticks);
1043 
1044 #if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1)
1045 #if defined(__SMODE_PRESENT) && (__SMODE_PRESENT == 1)
1047  ECLIC_SetLevelIRQ_S(SysTimer_S_IRQn, 0);
1048  ECLIC_EnableIRQ_S(SysTimer_S_IRQn);
1049 #endif
1050 #endif
1051  return (0UL);
1052 }
1053 
1063 {
1064  rv_counter_t cur_ticks = __get_rv_time();
1065 
1066  rv_counter_t reload_ticks = ticks + cur_ticks;
1067 
1068  SysTimer_SetCompareValue_S(reload_ticks);
1069 
1070  return (0UL);
1071 }
1072 #endif
1073 
1074 #endif /* defined(__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) */ /* End of Doxygen Group NMSIS_Core_SysTimer */
1076 
1077 #endif /* defined(__SYSTIMER_PRESENT) && (__SYSTIMER_PRESENT == 1) */
1078 
1079 #ifdef __cplusplus
1080 }
1081 #endif
1082 #endif /* __CORE_FEATURE_TIMER_H__ */
__STATIC_FORCEINLINE void __SW(volatile void *addr, uint32_t val)
Write 32bit value to address (32 bit)
__STATIC_FORCEINLINE uint32_t __LW(volatile void *addr)
Load 32bit value from address (32 bit)
#define MCOUNTEREN_TIME
#define MENVCFGH_STCE
#define MENVCFG_STCE
#define __RV_CSR_CLEAR(csr, val)
CSR operation Macro for csrc instruction.
#define __RV_CSR_READ(csr)
CSR operation Macro for csrr instruction.
__STATIC_INLINE rv_counter_t __get_rv_time(void)
Read whole 64 bits value of real-time clock.
#define __RV_CSR_WRITE(csr, val)
CSR operation Macro for csrw instruction.
#define __RV_CSR_SET(csr, val)
CSR operation Macro for csrs instruction.
#define CSR_MCOUNTEREN
#define CSR_STIMECMPH
#define CSR_STIMECMP
#define CSR_MENVCFG
#define CSR_MENVCFGH
#define __STATIC_FORCEINLINE
Define a static function that should be always inlined by the compiler.
Definition: nmsis_gcc.h:70
#define __STATIC_INLINE
Define a static function that may be inlined by the compiler.
Definition: nmsis_gcc.h:65
#define ECLIC_NON_VECTOR_INTERRUPT
Non-Vector Interrupt Mode of ECLIC.
#define ECLIC_SetShvIRQ
#define ECLIC_SetShvIRQ_S
#define ECLIC_SetLevelIRQ
#define ECLIC_EnableIRQ_S
#define ECLIC_EnableIRQ
#define ECLIC_SetLevelIRQ_S
@ SysTimer_IRQn
System Timer Interrupt.
#define __IOM
Defines 'read/write' structure member permissions.
uint64_t rv_counter_t
Type of RISC-V Counter such as cycle, instret, time, depends on the XLEN defined in RISC-V,...
#define SysTimer_MSFRST_KEY
SysTick Timer Software Reset Request Key.
#define SysTimer_CLINT_MTIMECMP_BASE(hartid)
#define SysTimer
SysTick configuration struct.
#define SysTimer_MTIME_SRW_CTRL_SRW_Msk
SysTick Timer MTIME_SRW_CTRL: SRW Mask.
#define SysTimer_MSIP_MSIP_Msk
SysTick Timer MSIP: MSIP Mask.
#define SysTimer_CLINT_MSIP_BASE(hartid)
#define SysTimer_MTIMECTL_Msk
SysTick Timer MTIMECTL/MSTOP value Mask.
#define SysTimer_CLINT_SSIP_BASE(hartid)
#define SysTimer_MTIMECTL_TIMESTOP_Msk
SysTick Timer MTIMECTL: TIMESTOP Mask.
#define SysTimer_SSIP_SSIP_Msk
SysTick Timer SSIP: SSIP Mask.
__STATIC_FORCEINLINE uint32_t SysTimer_GetSsipValue(void)
Get system timer SSIP register value.
__STATIC_FORCEINLINE uint32_t SysTimer_GetMsipValue(void)
Get system timer MSIP register value in machine mode.
__STATIC_INLINE rv_counter_t SysTimer_GetHartCompareValue(unsigned long hartid)
Get system timer compare value by hartid.
__STATIC_FORCEINLINE void SysTimer_SetHartSWIRQ(unsigned long hartid)
Trigger or set software interrupt via system timer by hartid.
__STATIC_INLINE uint32_t SysTick_Config_S(rv_counter_t ticks)
System Tick Configuration in supervisor mode.
__STATIC_FORCEINLINE rv_counter_t SysTimer_GetCompareValue(void)
Get system timer compare value in machine mode.
__STATIC_INLINE void SysTimer_SetCompareValue_S(uint64_t value)
Set system timer smode compare value.
__STATIC_FORCEINLINE void SysTimer_EnableSAccess(void)
Enable supervisor mode systimer register read/write access right.
#define SysTimer_GetHartID()
SysTimer_GetHartID() is used to get timer hartid which might not be the same as cpu hart id,...
__STATIC_FORCEINLINE void SysTimer_DisableSSTC(void)
Disable SSTC stimecmp csr access right for supervisor mode.
__STATIC_FORCEINLINE void SysTimer_DisableSAccess(void)
Disable supervisor mode systimer register read/write access right.
__STATIC_INLINE rv_counter_t SysTimer_GetLoadValue(void)
Get system timer load value.
#define SysTimer_GetHartID_S()
__STATIC_INLINE uint32_t SysTick_Reload(rv_counter_t ticks)
System Tick Reload.
__STATIC_FORCEINLINE void SysTimer_ClearIPI_S(unsigned long hartid)
clear ipi to target hart using Systimer Clint SSIP
__STATIC_INLINE void SysTimer_SetHartCompareValue(rv_counter_t value, unsigned long hartid)
Set system timer compare value by hartid.
__STATIC_FORCEINLINE uint32_t SysTimer_GetHartSsipValue(unsigned long hartid)
Get system timer SSIP register value by hartid.
__STATIC_FORCEINLINE void SysTimer_SendIPI(unsigned long hartid)
send ipi to target hart using Systimer Clint MSIP
__STATIC_INLINE uint32_t SysTick_HartReload(rv_counter_t ticks, unsigned long hartid)
System Tick Reload By hartid.
__STATIC_FORCEINLINE void SysTimer_ClearHartSWIRQ_S(unsigned long hartid)
Clear system timer supervisor mode software interrupt pending request by hartid.
__STATIC_FORCEINLINE void SysTimer_ClearSWIRQ(void)
Clear system timer software interrupt pending request in machine mode.
__STATIC_FORCEINLINE void SysTimer_ClearIPI(unsigned long hartid)
clear ipi to target hart using Systimer Clint MSIP
__STATIC_FORCEINLINE void SysTimer_SetCompareValue(rv_counter_t value)
Set system timer compare value in machine mode.
__STATIC_INLINE uint32_t SysTick_Reload_S(rv_counter_t ticks)
System Tick Reload in supervisor mode.
__STATIC_FORCEINLINE uint32_t SysTimer_GetHartMsipValue(unsigned long hartid)
Get system timer MSIP register value by hartid.
__STATIC_FORCEINLINE void SysTimer_EnableSSTC(void)
Enable SSTC access right for supervisor mode.
__STATIC_FORCEINLINE void SysTimer_SetHartSWIRQ_S(unsigned long hartid)
Trigger or set supervisor mode software interrupt via system timer by hartid.
__STATIC_FORCEINLINE void SysTimer_ClearHartSWIRQ(unsigned long hartid)
Clear system timer software interrupt pending request by hartid.
__STATIC_FORCEINLINE void SysTimer_SetHartSsipValue(uint32_t ssip, unsigned long hartid)
Set system timer SSIP register value by hartid.
__STATIC_INLINE void SysTimer_SetLoadValue(rv_counter_t value)
Set system timer load value.
__STATIC_FORCEINLINE void SysTimer_SetHartMsipValue(uint32_t msip, unsigned long hartid)
Set system timer MSIP register value by hartid.
__STATIC_FORCEINLINE void SysTimer_Start(void)
Enable system timer counter running.
__STATIC_INLINE uint32_t SysTick_Config(rv_counter_t ticks)
System Tick Configuration.
__STATIC_FORCEINLINE void SysTimer_SetSWIRQ(void)
Trigger or set software interrupt via system timer in machine mode.
__STATIC_FORCEINLINE void SysTimer_SetMsipValue(uint32_t msip)
Set system timer MSIP register value in machine mode.
__STATIC_FORCEINLINE void SysTimer_SetSWIRQ_S(void)
Trigger or set supervisor software interrupt via system timer.
__STATIC_FORCEINLINE void SysTimer_SoftwareReset(void)
Do software reset request.
__STATIC_FORCEINLINE void SysTimer_ClearSWIRQ_S(void)
Clear system timer supervisor mode software interrupt pending request.
__STATIC_INLINE uint64_t SysTimer_GetCompareValue_S(void)
Get system timer smode compare value.
__STATIC_FORCEINLINE void SysTimer_SendIPI_S(unsigned long hartid)
send ipi to target hart using Systimer Clint SSIP
__STATIC_FORCEINLINE void SysTimer_SetSsipValue(uint32_t ssip)
Set system timer SSIP register value.
__STATIC_INLINE uint32_t SysTick_HartConfig(rv_counter_t ticks, unsigned long hartid)
System Tick Configuration By hartid.
__STATIC_FORCEINLINE void SysTimer_SetControlValue(uint32_t mctl)
Set system timer control value.
__STATIC_FORCEINLINE void SysTimer_Stop(void)
Stop system timer counter running.
__STATIC_FORCEINLINE uint32_t SysTimer_GetControlValue(void)
Get system timer control value.
Structure type to access the System Timer (SysTimer).
__IOM uint32_t MTIMECTL
Offset: 0xFF8 (R/W) System Timer Control Register, previously MSTOP register.
__IOM uint64_t MTIMER
Offset: 0x000 (R/W) System Timer current value 64bits Register.
__IOM uint32_t MSFTRST
Offset: 0xFF0 (R/W) System Timer Software Core Reset Register.
__IOM uint32_t SSIP
Offset: 0xFF4 (R/W) S-Mode System Timer SW interrupt Register, not present in N100.
__IOM uint32_t MSIP
Offset: 0xFFC (R/W) M-Mode System Timer SW interrupt Register.
__IOM uint64_t MTIMERCMP
Offset: 0x008 (R/W) System Timer compare Value 64bits Register.
__IOM uint32_t MTIME_SRW_CTRL
Offset: 0xFEC (R/W) Control S-mode can access this timer or not, not present in N100.