CSR_MISA_Type Union Reference

Union type to access MISA CSR register. More...

Data Fields
struct {
rv_csr_t   a:1
	bit: 0 Atomic extension More...
rv_csr_t   b:1
	bit: 1 Tentatively reserved for Bit-Manipulation extension More...
rv_csr_t   c:1
	bit: 2 Compressed extension More...
rv_csr_t   d:1
	bit: 3 Double-precision floating-point extension More...
rv_csr_t   e:1
	bit: 4 RV32E base ISA More...
rv_csr_t   f:1
	bit: 5 Single-precision floating-point extension More...
rv_csr_t   g:1
	bit: 6 Additional standard extensions present More...
rv_csr_t   h:1
	bit: 7 Hypervisor extension More...
rv_csr_t   i:1
	bit: 8 RV32I/64I/128I base ISA More...
rv_csr_t   j:1
	bit: 9 Tentatively reserved for Dynamically Translated Languages extension More...
rv_csr_t   _reserved1:1
	bit: 10 Reserved More...
rv_csr_t   l:1
	bit: 11 Tentatively reserved for Decimal Floating-Point extension More...
rv_csr_t   m:1
	bit: 12 Integer Multiply/Divide extension More...
rv_csr_t   n:1
	bit: 13 User-level interrupts supported More...
rv_csr_t   _reserved2:1
	bit: 14 Reserved More...
rv_csr_t   p:1
	bit: 15 Tentatively reserved for Packed-SIMD extension More...
rv_csr_t   q:1
	bit: 16 Quad-precision floating-point extension More...
rv_csr_t   _resreved3:1
	bit: 17 Reserved More...
rv_csr_t   s:1
	bit: 18 Supervisor mode implemented More...
rv_csr_t   t:1
	bit: 19 Tentatively reserved for Transactional Memory extension More...
rv_csr_t   u:1
	bit: 20 User mode implemented More...
rv_csr_t   v:1
	bit: 21 Tentatively reserved for Vector extension More...
rv_csr_t   _reserved4:1
	bit: 22 Reserved More...
rv_csr_t   x:1
	bit: 23 Non-standard extensions present More...
rv_csr_t   _reserved5:6
	bit: 24..29 Reserved More...
rv_csr_t   mxl:2
	bit: 30..31 Machine XLEN More...
}	b
	Structure used for bit access. More...

Detailed Description

Union type to access MISA CSR register.

Definition at line 68 of file core_feature_base.h.

Field Documentation

_reserved1

rv_csr_t CSR_MISA_Type::_reserved1

bit: 10 Reserved

Definition at line 80 of file core_feature_base.h.

_reserved2

rv_csr_t CSR_MISA_Type::_reserved2

bit: 14 Reserved

Definition at line 84 of file core_feature_base.h.

_reserved4

rv_csr_t CSR_MISA_Type::_reserved4

bit: 22 Reserved

Definition at line 92 of file core_feature_base.h.

_reserved5

rv_csr_t CSR_MISA_Type::_reserved5

bit: 24..29 Reserved

Definition at line 98 of file core_feature_base.h.

_resreved3

rv_csr_t CSR_MISA_Type::_resreved3

bit: 17 Reserved

Definition at line 87 of file core_feature_base.h.

a

rv_csr_t CSR_MISA_Type::a

bit: 0 Atomic extension

Definition at line 70 of file core_feature_base.h.

b [1/2]

rv_csr_t CSR_MISA_Type::b

bit: 1 Tentatively reserved for Bit-Manipulation extension

Definition at line 71 of file core_feature_base.h.

b [2/2]

struct { ... } CSR_MISA_Type::b

Structure used for bit access.

c

rv_csr_t CSR_MISA_Type::c

bit: 2 Compressed extension

Definition at line 72 of file core_feature_base.h.

d

rv_csr_t CSR_MISA_Type::d

bit: 3 Double-precision floating-point extension

Type used for csr data access.

Definition at line 73 of file core_feature_base.h.

e

rv_csr_t CSR_MISA_Type::e

bit: 4 RV32E base ISA

Definition at line 74 of file core_feature_base.h.

f

rv_csr_t CSR_MISA_Type::f

bit: 5 Single-precision floating-point extension

Definition at line 75 of file core_feature_base.h.

g

rv_csr_t CSR_MISA_Type::g

bit: 6 Additional standard extensions present

Definition at line 76 of file core_feature_base.h.

h

rv_csr_t CSR_MISA_Type::h

bit: 7 Hypervisor extension

Definition at line 77 of file core_feature_base.h.

i

rv_csr_t CSR_MISA_Type::i

bit: 8 RV32I/64I/128I base ISA

Definition at line 78 of file core_feature_base.h.

j

rv_csr_t CSR_MISA_Type::j

bit: 9 Tentatively reserved for Dynamically Translated Languages extension

Definition at line 79 of file core_feature_base.h.

l

rv_csr_t CSR_MISA_Type::l

bit: 11 Tentatively reserved for Decimal Floating-Point extension

Definition at line 81 of file core_feature_base.h.

m

rv_csr_t CSR_MISA_Type::m

bit: 12 Integer Multiply/Divide extension

Definition at line 82 of file core_feature_base.h.

mxl

rv_csr_t CSR_MISA_Type::mxl

bit: 30..31 Machine XLEN

Definition at line 99 of file core_feature_base.h.

n

rv_csr_t CSR_MISA_Type::n

bit: 13 User-level interrupts supported

Definition at line 83 of file core_feature_base.h.

p

rv_csr_t CSR_MISA_Type::p

bit: 15 Tentatively reserved for Packed-SIMD extension

Definition at line 85 of file core_feature_base.h.

q

rv_csr_t CSR_MISA_Type::q

bit: 16 Quad-precision floating-point extension

Definition at line 86 of file core_feature_base.h.

s

rv_csr_t CSR_MISA_Type::s

bit: 18 Supervisor mode implemented

Definition at line 88 of file core_feature_base.h.

t

rv_csr_t CSR_MISA_Type::t

bit: 19 Tentatively reserved for Transactional Memory extension

Definition at line 89 of file core_feature_base.h.

u

rv_csr_t CSR_MISA_Type::u

bit: 20 User mode implemented

Definition at line 90 of file core_feature_base.h.

v

rv_csr_t CSR_MISA_Type::v

bit: 21 Tentatively reserved for Vector extension

Definition at line 91 of file core_feature_base.h.

x

rv_csr_t CSR_MISA_Type::x

bit: 23 Non-standard extensions present

Definition at line 93 of file core_feature_base.h.