NMSIS-Core  Version 1.4.0
NMSIS-Core support for Nuclei processor-based devices

Union type to access MCAUSE CSR register. More...

Data Fields

struct {
   rv_csr_t   exccode:12
 bit: 0..11 exception or interrupt code More...
 
   rv_csr_t   _reserved0:4
 bit: 12..15 Reserved More...
 
   rv_csr_t   mpil:8
 bit: 16..23 Previous interrupt level More...
 
   rv_csr_t   _reserved1:3
 bit: 24..26 Reserved More...
 
   rv_csr_t   mpie:1
 bit: 27 Interrupt enable flag before enter interrupt More...
 
   rv_csr_t   mpp:2
 bit: 28..29 Privilede mode flag before enter interrupt More...
 
   rv_csr_t   minhv:1
 bit: 30 Machine interrupt vector table More...
 
   rv_csr_t   interrupt:1
 bit: XLEN-1 trap type. More...
 
b
 Structure used for bit access. More...
 
rv_csr_t d
 Type used for csr data access. More...
 

Detailed Description

Union type to access MCAUSE CSR register.

Definition at line 183 of file core_feature_base.h.

Field Documentation

◆ _reserved0

rv_csr_t CSR_MCAUSE_Type::_reserved0

bit: 12..15 Reserved

Definition at line 186 of file core_feature_base.h.

◆ _reserved1

rv_csr_t CSR_MCAUSE_Type::_reserved1

bit: 24..26 Reserved

Definition at line 188 of file core_feature_base.h.

◆ 

struct { ... } CSR_MCAUSE_Type::b

Structure used for bit access.

◆ d

rv_csr_t CSR_MCAUSE_Type::d

Type used for csr data access.

Definition at line 197 of file core_feature_base.h.

◆ exccode

rv_csr_t CSR_MCAUSE_Type::exccode

bit: 0..11 exception or interrupt code

Definition at line 185 of file core_feature_base.h.

◆ interrupt

rv_csr_t CSR_MCAUSE_Type::interrupt

bit: XLEN-1 trap type.

0 means exception and 1 means interrupt

Definition at line 195 of file core_feature_base.h.

◆ minhv

rv_csr_t CSR_MCAUSE_Type::minhv

bit: 30 Machine interrupt vector table

Definition at line 191 of file core_feature_base.h.

◆ mpie

rv_csr_t CSR_MCAUSE_Type::mpie

bit: 27 Interrupt enable flag before enter interrupt

Definition at line 189 of file core_feature_base.h.

◆ mpil

rv_csr_t CSR_MCAUSE_Type::mpil

bit: 16..23 Previous interrupt level

Definition at line 187 of file core_feature_base.h.

◆ mpp

rv_csr_t CSR_MCAUSE_Type::mpp

bit: 28..29 Privilede mode flag before enter interrupt

Definition at line 190 of file core_feature_base.h.