SIMD 8bit Shift Instructions
 __STATIC_FORCEINLINE unsigned long __RV_KSLL8 (unsigned long a, unsigned int b)
 __STATIC_FORCEINLINE unsigned long __RV_KSLRA8 (unsigned long a, int b)
 __STATIC_FORCEINLINE unsigned long __RV_KSLRA8_U (unsigned long a, int b)
 __STATIC_FORCEINLINE unsigned long __RV_SLL8 (unsigned long a, unsigned int b)
 __STATIC_FORCEINLINE unsigned long __RV_SRA8 (unsigned long a, unsigned int b)
 __STATIC_FORCEINLINE unsigned long __RV_SRA8_U (unsigned long a, unsigned int b)
 __STATIC_FORCEINLINE unsigned long __RV_SRL8 (unsigned long a, unsigned int b)
 __STATIC_FORCEINLINE unsigned long __RV_SRL8_U (unsigned long a, unsigned int b)

__RV_KSLLI8(a, b)

__RV_SLLI8(a, b)

__RV_SRAI8(a, b)

__RV_SRAI8_U(a, b)

__RV_SRLI8(a, b)

__RV_SRLI8_U(a, b)
 group NMSIS_Core_DSP_Intrinsic_SIMD_8B_SHIFT
SIMD 8bit Shift Instructions.
there are 14 SIMD 8bit shift instructions.
Defines

__RV_KSLLI8(a, b)
KSLLI8 (SIMD 8bit Saturating Shift Left Logical Immediate)
Type: SIMD
Syntax:
KSLLI8 Rd, Rs1, imm3u
Purpose
:
Do 8bit elements logical left shift operations with saturation simultaneously. The shift amount is an immediate value.
Description
:
The 8bit data elements in Rs1 are leftshifted logically. The shifted out bits are filled with zero and the shift amount is specified by the imm3u constant. Any shifted value greater than 2^71 is saturated to 2^71. Any shifted value smaller than 2^7 is saturated to 2^7. And the saturated results are written to Rd. If any saturation is performed, set OV bit to 1.
Operations:
sa = imm3u[2:0]; if (sa != 0) { res[(7+sa):0] = Rs1.B[x] << sa; if (res > (2^7)1) { res = 0x7f; OV = 1; } else if (res < 2^7) { res = 0x80; OV = 1; } Rd.B[x] = res[7:0]; } else { Rd = Rs1; } for RV32: x=3...0, for RV64: x=7...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type

__RV_SLLI8(a, b)
SLLI8 (SIMD 8bit Shift Left Logical Immediate)
Type: SIMD
Syntax:
SLLI8 Rd, Rs1, imm3u
Purpose
:
Do 8bit elements logical left shift operations simultaneously. The shift amount is an immediate value.
Description
:
The 8bit elements in Rs1 are leftshifted logically. And the results are written to Rd. The shifted out bits are filled with zero and the shift amount is specified by the imm3u constant.
Operations:
sa = imm3u[2:0]; Rd.B[x] = Rs1.B[x] << sa; for RV32: x=3...0, for RV64: x=7...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type

__RV_SRAI8(a, b)
SRAI8 (SIMD 8bit Shift Right Arithmetic Immediate)
Type: SIMD
Syntax:
SRAI8 Rd, Rs1, imm3u SRAI8.u Rd, Rs1, imm3u
Purpose
:
Do 8bit element arithmetic right shift operations simultaneously. The shift amount is an immediate value. The
.u
form performs additional rounding up operations on the shifted results.Description
:
The 8bit data elements in Rs1 are rightshifted arithmetically, that is, the shifted out bits are filled with the signbit of the data elements. The shift amount is specified by the imm3u constant. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 8bit data element to calculate the final results. And the results are written to Rd.Operations:
sa = imm3u[2:0]; if (sa > 0) { if (`.u` form) { // SRA8.u res[7:1] = SE9(Rs1.B[x][7:sa1]) + 1; Rd.B[x] = res[7:0]; } else { // SRA8 Rd.B[x] = SE8(Rd.B[x][7:sa]) } } else { Rd = Rs1; } for RV32: x=3...0, for RV64: x=7...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type

__RV_SRAI8_U(a, b)
SRAI8.u (SIMD 8bit Rounding Shift Right Arithmetic Immediate)
Type: SIMD
Syntax:
SRAI8 Rd, Rs1, imm3u SRAI8.u Rd, Rs1, imm3u
Purpose
:
Do 8bit element arithmetic right shift operations simultaneously. The shift amount is an immediate value. The
.u
form performs additional rounding up operations on the shifted results.Description
:
The 8bit data elements in Rs1 are rightshifted arithmetically, that is, the shifted out bits are filled with the signbit of the data elements. The shift amount is specified by the imm3u constant. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 8bit data element to calculate the final results. And the results are written to Rd.Operations:
sa = imm3u[2:0]; if (sa > 0) { if (`.u` form) { // SRA8.u res[7:1] = SE9(Rs1.B[x][7:sa1]) + 1; Rd.B[x] = res[7:0]; } else { // SRA8 Rd.B[x] = SE8(Rd.B[x][7:sa]) } } else { Rd = Rs1; } for RV32: x=3...0, for RV64: x=7...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type

__RV_SRLI8(a, b)
SRLI8 (SIMD 8bit Shift Right Logical Immediate)
Type: SIMD
Syntax:
SRLI8 Rt, Ra, imm3u SRLI8.u Rt, Ra, imm3u
Purpose
:
Do 8bit elements logical right shift operations simultaneously. The shift amount is an immediate value. The
.u
form performs additional rounding up operations on the shifted results.Description
:
The 8bit data elements in Rs1 are rightshifted logically, that is, the shifted out bits are filled with zero. The shift amount is specified by the imm3u constant. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 8bit data element to calculate the final results. And the results are written to Rd.Operations:
sa = imm3u[2:0]; if (sa > 0) { if (`.u` form) { // SRLI8.u res[8:0] = ZE9(Rs1.B[x][7:sa1]) + 1; Rd.B[x] = res[8:1]; } else { // SRLI8 Rd.B[x] = ZE8(Rs1.B[x][7:sa]); } } else { Rd = Rs1; } for RV32: x=3...0, for RV64: x=7...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type

__RV_SRLI8_U(a, b)
SRLI8.u (SIMD 8bit Rounding Shift Right Logical Immediate)
Type: SIMD
Syntax:
SRLI8 Rt, Ra, imm3u SRLI8.u Rt, Ra, imm3u
Purpose
:
Do 8bit elements logical right shift operations simultaneously. The shift amount is an immediate value. The
.u
form performs additional rounding up operations on the shifted results.Description
:
The 8bit data elements in Rs1 are rightshifted logically, that is, the shifted out bits are filled with zero. The shift amount is specified by the imm3u constant. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 8bit data element to calculate the final results. And the results are written to Rd.Operations:
sa = imm3u[2:0]; if (sa > 0) { if (`.u` form) { // SRLI8.u res[8:0] = ZE9(Rs1.B[x][7:sa1]) + 1; Rd.B[x] = res[8:1]; } else { // SRLI8 Rd.B[x] = ZE8(Rs1.B[x][7:sa]); } } else { Rd = Rs1; } for RV32: x=3...0, for RV64: x=7...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type
Functions
 __STATIC_FORCEINLINE unsigned long __RV_KSLL8 (unsigned long a, unsigned int b)
KSLL8 (SIMD 8bit Saturating Shift Left Logical)
Type: SIMD
Syntax:
KSLL8 Rd, Rs1, Rs2
Purpose
:
Do 8bit elements logical left shift operations with saturation simultaneously. The shift amount is a variable from a GPR.
Description
:
The 8bit data elements in Rs1 are leftshifted logically. The shifted out bits are filled with zero and the shift amount is specified by the loworder 3bits of the value in the Rs2 register. Any shifted value greater than 2^71 is saturated to 2^71. Any shifted value smaller than 2^7 is saturated to 2^7. And the saturated results are written to Rd. If any saturation is performed, set OV bit to 1.
Operations:
sa = Rs2[2:0]; if (sa != 0) { res[(7+sa):0] = Rs1.B[x] << sa; if (res > (2^7)1) { res = 0x7f; OV = 1; } else if (res < 2^7) { res = 0x80; OV = 1; } Rd.B[x] = res[7:0]; } else { Rd = Rs1; } for RV32: x=3...0, for RV64: x=7...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type
 __STATIC_FORCEINLINE unsigned long __RV_KSLRA8 (unsigned long a, int b)
KSLRA8 (SIMD 8bit Shift Left Logical with Saturation or Shift Right Arithmetic)
Type: SIMD
Syntax:
KSLRA8 Rd, Rs1, Rs2 KSLRA8.u Rd, Rs1, Rs2
Purpose
:
Do 8bit elements logical left (positive) or arithmetic right (negative) shift operation with Q7 saturation for the left shift. The
.u
form performs additional rounding up operations for the right shift.Description
:
The 8bit data elements of Rs1 are leftshifted logically or rightshifted arithmetically based on the value of Rs2[3:0]. Rs2[3:0] is in the signed range of [2^3, 2^31]. A positive Rs2[3:0] means logical left shift and a negative Rs2[3:0] means arithmetic right shift. The shift amount is the absolute value of Rs2[3:0]. However, the behavior of
Rs2[3:0]==2^3 (0x8)
is defined to be equivalent to the behavior ofRs2[3:0]==(2^31) (0x9)
. The leftshifted results are saturated to the 8bit signed integer range of [2^7, 2^71]. For the.u
form of the instruction, the rightshifted results are added a 1 to the most significant discarded bit position for rounding effect. After the shift, saturation, or rounding, the final results are written to Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:4] will not affect this instruction.Operations:
if (Rs2[3:0] < 0) { sa = Rs2[3:0]; sa = (sa == 8)? 7 : sa; if (`.u` form) { res[7:1] = SE9(Rs1.B[x][7:sa1]) + 1; Rd.B[x] = res[7:0]; } else { Rd.B[x] = SE8(Rs1.B[x][7:sa]); } } else { sa = Rs2[2:0]; res[(7+sa):0] = Rs1.B[x] <<(logic) sa; if (res > (2^7)1) { res[7:0] = 0x7f; OV = 1; } else if (res < 2^7) { res[7:0] = 0x80; OV = 1; } Rd.B[x] = res[7:0]; } for RV32: x=3...0, for RV64: x=7...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] int type of value stored in b
 Returns
value stored in unsigned long type
 __STATIC_FORCEINLINE unsigned long __RV_KSLRA8_U (unsigned long a, int b)
KSLRA8.u (SIMD 8bit Shift Left Logical with Saturation or Rounding Shift Right Arithmetic)
Type: SIMD
Syntax:
KSLRA8 Rd, Rs1, Rs2 KSLRA8.u Rd, Rs1, Rs2
Purpose
:
Do 8bit elements logical left (positive) or arithmetic right (negative) shift operation with Q7 saturation for the left shift. The
.u
form performs additional rounding up operations for the right shift.Description
:
The 8bit data elements of Rs1 are leftshifted logically or rightshifted arithmetically based on the value of Rs2[3:0]. Rs2[3:0] is in the signed range of [2^3, 2^31]. A positive Rs2[3:0] means logical left shift and a negative Rs2[3:0] means arithmetic right shift. The shift amount is the absolute value of Rs2[3:0]. However, the behavior of
Rs2[3:0]==2^3 (0x8)
is defined to be equivalent to the behavior ofRs2[3:0]==(2^31) (0x9)
. The leftshifted results are saturated to the 8bit signed integer range of [2^7, 2^71]. For the.u
form of the instruction, the rightshifted results are added a 1 to the most significant discarded bit position for rounding effect. After the shift, saturation, or rounding, the final results are written to Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:4] will not affect this instruction.Operations:
if (Rs2[3:0] < 0) { sa = Rs2[3:0]; sa = (sa == 8)? 7 : sa; if (`.u` form) { res[7:1] = SE9(Rs1.B[x][7:sa1]) + 1; Rd.B[x] = res[7:0]; } else { Rd.B[x] = SE8(Rs1.B[x][7:sa]); } } else { sa = Rs2[2:0]; res[(7+sa):0] = Rs1.B[x] <<(logic) sa; if (res > (2^7)1) { res[7:0] = 0x7f; OV = 1; } else if (res < 2^7) { res[7:0] = 0x80; OV = 1; } Rd.B[x] = res[7:0]; } for RV32: x=3...0, for RV64: x=7...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] int type of value stored in b
 Returns
value stored in unsigned long type
 __STATIC_FORCEINLINE unsigned long __RV_SLL8 (unsigned long a, unsigned int b)
SLL8 (SIMD 8bit Shift Left Logical)
Type: SIMD
Syntax:
SLL8 Rd, Rs1, Rs2
Purpose
:
Do 8bit elements logical left shift operations simultaneously. The shift amount is a variable from a GPR.
Description
:
The 8bit elements in Rs1 are leftshifted logically. And the results are written to Rd. The shifted out bits are filled with zero and the shift amount is specified by the loworder 3bits of the value in the Rs2 register.
Operations:
sa = Rs2[2:0]; Rd.B[x] = Rs1.B[x] << sa; for RV32: x=3...0, for RV64: x=7...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type
 __STATIC_FORCEINLINE unsigned long __RV_SRA8 (unsigned long a, unsigned int b)
SRA8 (SIMD 8bit Shift Right Arithmetic)
Type: SIMD
Syntax:
SRA8 Rd, Rs1, Rs2 SRA8.u Rd, Rs1, Rs2
Purpose
:
Do 8bit element arithmetic right shift operations simultaneously. The shift amount is a variable from a GPR. The
.u
form performs additional rounding up operations on the shifted results.Description
:
The 8bit data elements in Rs1 are rightshifted arithmetically, that is, the shifted out bits are filled with the signbit of the data elements. The shift amount is specified by the loworder 3bits of the value in the Rs2 register. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 8bit data element to calculate the final results. And the results are written to Rd.Operations:
sa = Rs2[2:0]; if (sa > 0) { if (`.u` form) { // SRA8.u res[7:1] = SE9(Rs1.B[x][7:sa1]) + 1; Rd.B[x] = res[7:0]; } else { // SRA8 Rd.B[x] = SE8(Rd.B[x][7:sa]) } } else { Rd = Rs1; } for RV32: x=3...0, for RV64: x=7...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type
 __STATIC_FORCEINLINE unsigned long __RV_SRA8_U (unsigned long a, unsigned int b)
SRA8.u (SIMD 8bit Rounding Shift Right Arithmetic)
Type: SIMD
Syntax:
SRA8 Rd, Rs1, Rs2 SRA8.u Rd, Rs1, Rs2
Purpose
:
Do 8bit element arithmetic right shift operations simultaneously. The shift amount is a variable from a GPR. The
.u
form performs additional rounding up operations on the shifted results.Description
:
The 8bit data elements in Rs1 are rightshifted arithmetically, that is, the shifted out bits are filled with the signbit of the data elements. The shift amount is specified by the loworder 3bits of the value in the Rs2 register. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 8bit data element to calculate the final results. And the results are written to Rd.Operations:
sa = Rs2[2:0]; if (sa > 0) { if (`.u` form) { // SRA8.u res[7:1] = SE9(Rs1.B[x][7:sa1]) + 1; Rd.B[x] = res[7:0]; } else { // SRA8 Rd.B[x] = SE8(Rd.B[x][7:sa]) } } else { Rd = Rs1; } for RV32: x=3...0, for RV64: x=7...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type
 __STATIC_FORCEINLINE unsigned long __RV_SRL8 (unsigned long a, unsigned int b)
SRL8 (SIMD 8bit Shift Right Logical)
Type: SIMD
Syntax:
SRL8 Rt, Ra, Rb SRL8.u Rt, Ra, Rb
Purpose
:
Do 8bit elements logical right shift operations simultaneously. The shift amount is a variable from a GPR. The
.u
form performs additional rounding up operations on the shifted results.Description
:
The 8bit data elements in Rs1 are rightshifted logically, that is, the shifted out bits are filled with zero. The shift amount is specified by the loworder 3bits of the value in the Rs2 register. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 8bit data element to calculate the final results. And the results are written to Rd.Operations:
sa = Rs2[2:0]; if (sa > 0) { if (`.u` form) { // SRL8.u res[8:0] = ZE9(Rs1.B[x][7:sa1]) + 1; Rd.B[x] = res[8:1]; } else { // SRL8 Rd.B[x] = ZE8(Rs1.B[x][7:sa]); } } else { Rd = Rs1; } for RV32: x=3...0, for RV64: x=7...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type
 __STATIC_FORCEINLINE unsigned long __RV_SRL8_U (unsigned long a, unsigned int b)
SRL8.u (SIMD 8bit Rounding Shift Right Logical)
Type: SIMD
Syntax:
SRL8 Rt, Ra, Rb SRL8.u Rt, Ra, Rb
Purpose
:
Do 8bit elements logical right shift operations simultaneously. The shift amount is a variable from a GPR. The
.u
form performs additional rounding up operations on the shifted results.Description
:
The 8bit data elements in Rs1 are rightshifted logically, that is, the shifted out bits are filled with zero. The shift amount is specified by the loworder 3bits of the value in the Rs2 register. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 8bit data element to calculate the final results. And the results are written to Rd.Operations:
sa = Rs2[2:0]; if (sa > 0) { if (`.u` form) { // SRL8.u res[8:0] = ZE9(Rs1.B[x][7:sa1]) + 1; Rd.B[x] = res[8:1]; } else { // SRL8 Rd.B[x] = ZE8(Rs1.B[x][7:sa]); } } else { Rd = Rs1; } for RV32: x=3...0, for RV64: x=7...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type

__RV_KSLLI8(a, b)