SIMD 16bit Shift Instructions¶

__STATIC_FORCEINLINE unsigned long __RV_KSLL16(unsigned long a, unsigned int b)

__STATIC_FORCEINLINE unsigned long __RV_KSLRA16(unsigned long a, int b)

__STATIC_FORCEINLINE unsigned long __RV_KSLRA16_U(unsigned long a, int b)

__STATIC_FORCEINLINE unsigned long __RV_SLL16(unsigned long a, unsigned int b)

__STATIC_FORCEINLINE unsigned long __RV_SRA16(unsigned long a, unsigned long b)

__STATIC_FORCEINLINE unsigned long __RV_SRA16_U(unsigned long a, unsigned long b)

__STATIC_FORCEINLINE unsigned long __RV_SRL16(unsigned long a, unsigned int b)

__STATIC_FORCEINLINE unsigned long __RV_SRL16_U(unsigned long a, unsigned int b)

__RV_KSLLI16
(a, b)¶

__RV_SLLI16
(a, b)¶

__RV_SRAI16
(a, b)¶

__RV_SRAI16_U
(a, b)¶

__RV_SRLI16
(a, b)¶

__RV_SRLI16_U
(a, b)¶

group
NMSIS_Core_DSP_Intrinsic_SIMD_16B_SHIFT
SIMD 16bit Shift Instructions.
there are 14 SIMD 16bit shift instructions.
Defines

__RV_KSLLI16
(a, b) KSLLI16 (SIMD 16bit Saturating Shift Left Logical Immediate)
Type: SIMD
Syntax:
KSLLI16 Rd, Rs1, imm4u
Purpose:
Do 16bit elements logical left shift operations with saturation simultaneously. The shift amount is an immediate value.
Description:
The 16bit data elements in Rs1 are leftshifted logically. The shifted out bits are filled with zero and the shift amount is specified by the imm4u constant. Any shifted value greater than 2^151 is saturated to 2^151. Any shifted value smaller than 2^15 is saturated to 2^15. And the saturated results are written to Rd. If any saturation is performed, set OV bit to 1.
Operations:
sa = imm4u[3:0]; if (sa != 0) { res[(15+sa):0] = Rs1.H[x] << sa; if (res > (2^15)1) { res = 0x7fff; OV = 1; } else if (res < 2^15) { res = 0x8000; OV = 1; } Rd.H[x] = res[15:0]; } else { Rd = Rs1; } for RV32: x=1...0, for RV64: x=3...0
 Return
value stored in unsigned long type
 Parameters
[in] a
: unsigned long type of value stored in a[in] b
: unsigned int type of value stored in b

__RV_SLLI16
(a, b) SLLI16 (SIMD 16bit Shift Left Logical Immediate)
Type: SIMD
Syntax:
SLLI16 Rd, Rs1, imm4[3:0]
Purpose:
Do 16bit element logical left shift operations simultaneously. The shift amount is an immediate value.
Description:
The 16bit elements in Rs1 are leftshifted logically. The shifted out bits are filled with zero and the shift amount is specified by the imm4[3:0] constant. And the results are written to Rd.
Operations:
sa = imm4[3:0]; Rd.H[x] = Rs1.H[x] << sa; for RV32: x=1...0, for RV64: x=3...0
 Return
value stored in unsigned long type
 Parameters
[in] a
: unsigned long type of value stored in a[in] b
: unsigned int type of value stored in b

__RV_SRAI16
(a, b) SRAI16 (SIMD 16bit Shift Right Arithmetic Immediate)
Type: SIMD
Syntax:
SRAI16 Rd, Rs1, imm4u SRAI16.u Rd, Rs1, imm4u
Purpose:
Do 16bit elements arithmetic right shift operations simultaneously. The shift amount is an immediate value. The
.u
form performs additional rounding up operations on the shifted results.Description:
The 16bit data elements in Rs1 are rightshifted arithmetically, that is, the shifted out bits are filled with the signbit of the 16bit data elements. The shift amount is specified by the imm4u constant. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 16bit data to calculate the final results. And the results are written to Rd.Operations:
sa = imm4u[3:0]; if (sa > 0) { if (`.u` form) { // SRAI16.u res[15:1] = SE17(Rs1.H[x][15:sa1]) + 1; Rd.H[x] = res[15:0]; } else { // SRAI16 Rd.H[x] = SE16(Rs1.H[x][15:sa]); } } else { Rd = Rs1; } for RV32: x=1...0, for RV64: x=3...0
 Return
value stored in unsigned long type
 Parameters
[in] a
: unsigned long type of value stored in a[in] b
: unsigned long type of value stored in b

__RV_SRAI16_U
(a, b) SRAI16.u (SIMD 16bit Rounding Shift Right Arithmetic Immediate)
Type: SIMD
Syntax:
SRAI16 Rd, Rs1, imm4u SRAI16.u Rd, Rs1, imm4u
Purpose:
Do 16bit elements arithmetic right shift operations simultaneously. The shift amount is an immediate value. The
.u
form performs additional rounding up operations on the shifted results.Description:
The 16bit data elements in Rs1 are rightshifted arithmetically, that is, the shifted out bits are filled with the signbit of the 16bit data elements. The shift amount is specified by the imm4u constant. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 16bit data to calculate the final results. And the results are written to Rd.Operations:
sa = imm4u[3:0]; if (sa > 0) { if (`.u` form) { // SRAI16.u res[15:1] = SE17(Rs1.H[x][15:sa1]) + 1; Rd.H[x] = res[15:0]; } else { // SRAI16 Rd.H[x] = SE16(Rs1.H[x][15:sa]); } } else { Rd = Rs1; } for RV32: x=1...0, for RV64: x=3...0
 Return
value stored in unsigned long type
 Parameters
[in] a
: unsigned long type of value stored in a[in] b
: unsigned long type of value stored in b

__RV_SRLI16
(a, b) SRLI16 (SIMD 16bit Shift Right Logical Immediate)
Type: SIMD
Syntax:
SRLI16 Rt, Ra, imm4u SRLI16.u Rt, Ra, imm4u
Purpose:
Do 16bit elements logical right shift operations simultaneously. The shift amount is an immediate value. The
.u
form performs additional rounding up operations on the shifted results.Description:
The 16bit data elements in Rs1 are rightshifted logically, that is, the shifted out bits are filled with zero. The shift amount is specified by the imm4u constant. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 16bit data element to calculate the final results. And the results are written to Rd.Operations:
sa = imm4u; if (sa > 0) { if (`.u` form) { // SRLI16.u res[16:0] = ZE17(Rs1.H[x][15:sa1]) + 1; Rd.H[x] = res[16:1]; } else { // SRLI16 Rd.H[x] = ZE16(Rs1.H[x][15:sa]); } } else { Rd = Rs1; } for RV32: x=1...0, for RV64: x=3...0
 Return
value stored in unsigned long type
 Parameters
[in] a
: unsigned long type of value stored in a[in] b
: unsigned int type of value stored in b

__RV_SRLI16_U
(a, b) SRLI16.u (SIMD 16bit Rounding Shift Right Logical Immediate)
Type: SIMD
Syntax:
SRLI16 Rt, Ra, imm4u SRLI16.u Rt, Ra, imm4u
Purpose:
Do 16bit elements logical right shift operations simultaneously. The shift amount is an immediate value. The
.u
form performs additional rounding up operations on the shifted results.Description:
The 16bit data elements in Rs1 are rightshifted logically, that is, the shifted out bits are filled with zero. The shift amount is specified by the imm4u constant. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 16bit data element to calculate the final results. And the results are written to Rd.Operations:
sa = imm4u; if (sa > 0) { if (`.u` form) { // SRLI16.u res[16:0] = ZE17(Rs1.H[x][15:sa1]) + 1; Rd.H[x] = res[16:1]; } else { // SRLI16 Rd.H[x] = ZE16(Rs1.H[x][15:sa]); } } else { Rd = Rs1; } for RV32: x=1...0, for RV64: x=3...0
 Return
value stored in unsigned long type
 Parameters
[in] a
: unsigned long type of value stored in a[in] b
: unsigned int type of value stored in b
Functions

__STATIC_FORCEINLINE unsigned long __RV_KSLL16(unsigned long a, unsigned int b)
KSLL16 (SIMD 16bit Saturating Shift Left Logical)
Type: SIMD
Syntax:
KSLL16 Rd, Rs1, Rs2
Purpose:
Do 16bit elements logical left shift operations with saturation simultaneously. The shift amount is a variable from a GPR.
Description:
The 16bit data elements in Rs1 are leftshifted logically. The shifted out bits are filled with zero and the shift amount is specified by the loworder 4bits of the value in the Rs2 register. Any shifted value greater than 2^151 is saturated to 2^151. Any shifted value smaller than 2^15 is saturated to 2^15. And the saturated results are written to Rd. If any saturation is performed, set OV bit to 1.
Operations:
sa = Rs2[3:0]; if (sa != 0) { res[(15+sa):0] = Rs1.H[x] << sa; if (res > (2^15)1) { res = 0x7fff; OV = 1; } else if (res < 2^15) { res = 0x8000; OV = 1; } Rd.H[x] = res[15:0]; } else { Rd = Rs1; } for RV32: x=1...0, for RV64: x=3...0
 Return
value stored in unsigned long type
 Parameters
[in] a
: unsigned long type of value stored in a[in] b
: unsigned int type of value stored in b

__STATIC_FORCEINLINE unsigned long __RV_KSLRA16(unsigned long a, int b)
KSLRA16 (SIMD 16bit Shift Left Logical with Saturation or Shift Right Arithmetic)
Type: SIMD
Syntax:
KSLRA16 Rd, Rs1, Rs2 KSLRA16.u Rd, Rs1, Rs2
Purpose:
Do 16bit elements logical left (positive) or arithmetic right (negative) shift operation with Q15 saturation for the left shift. The
.u
form performs additional rounding up operations for the right shift.Description:
The 16bit data elements of Rs1 are leftshifted logically or rightshifted arithmetically based on the value of Rs2[4:0]. Rs2[4:0] is in the signed range of [2^4, 2^41]. A positive Rs2[4:0] means logical left shift and a negative Rs2[4:0] means arithmetic right shift. The shift amount is the absolute value of Rs2[4:0]. However, the behavior of
Rs2[4:0]==2^4 (0x10)
is defined to be equivalent to the behavior ofRs2[4:0]==(2^41) (0x11)
. The leftshifted results are saturated to the 16bit signed integer range of [2^15, 2^151]. For the.u
form of the instruction, the rightshifted results are added a 1 to the most significant discarded bit position for rounding effect. After the shift, saturation, or rounding, the final results are written to Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:5] will not affect this instruction.Operations:
if (Rs2[4:0] < 0) { sa = Rs2[4:0]; sa = (sa == 16)? 15 : sa; if (`.u` form) { res[15:1] = SE17(Rs1.H[x][15:sa1]) + 1; Rd.H[x] = res[15:0]; } else { Rd.H[x] = SE16(Rs1.H[x][15:sa]); } } else { sa = Rs2[3:0]; res[(15+sa):0] = Rs1.H[x] <<(logic) sa; if (res > (2^15)1) { res[15:0] = 0x7fff; OV = 1; } else if (res < 2^15) { res[15:0] = 0x8000; OV = 1; } d.H[x] = res[15:0]; } for RV32: x=1...0, for RV64: x=3...0
 Return
value stored in unsigned long type
 Parameters
[in] a
: unsigned long type of value stored in a[in] b
: int type of value stored in b

__STATIC_FORCEINLINE unsigned long __RV_KSLRA16_U(unsigned long a, int b)
KSLRA16.u (SIMD 16bit Shift Left Logical with Saturation or Rounding Shift Right Arithmetic)
Type: SIMD
Syntax:
KSLRA16 Rd, Rs1, Rs2 KSLRA16.u Rd, Rs1, Rs2
Purpose:
Do 16bit elements logical left (positive) or arithmetic right (negative) shift operation with Q15 saturation for the left shift. The
.u
form performs additional rounding up operations for the right shift.Description:
The 16bit data elements of Rs1 are leftshifted logically or rightshifted arithmetically based on the value of Rs2[4:0]. Rs2[4:0] is in the signed range of [2^4, 2^41]. A positive Rs2[4:0] means logical left shift and a negative Rs2[4:0] means arithmetic right shift. The shift amount is the absolute value of Rs2[4:0]. However, the behavior of
Rs2[4:0]==2^4 (0x10)
is defined to be equivalent to the behavior ofRs2[4:0]==(2^41) (0x11)
. The leftshifted results are saturated to the 16bit signed integer range of [2^15, 2^151]. For the.u
form of the instruction, the rightshifted results are added a 1 to the most significant discarded bit position for rounding effect. After the shift, saturation, or rounding, the final results are written to Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:5] will not affect this instruction.Operations:
if (Rs2[4:0] < 0) { sa = Rs2[4:0]; sa = (sa == 16)? 15 : sa; if (`.u` form) { res[15:1] = SE17(Rs1.H[x][15:sa1]) + 1; Rd.H[x] = res[15:0]; } else { Rd.H[x] = SE16(Rs1.H[x][15:sa]); } } else { sa = Rs2[3:0]; res[(15+sa):0] = Rs1.H[x] <<(logic) sa; if (res > (2^15)1) { res[15:0] = 0x7fff; OV = 1; } else if (res < 2^15) { res[15:0] = 0x8000; OV = 1; } d.H[x] = res[15:0]; } for RV32: x=1...0, for RV64: x=3...0
 Return
value stored in unsigned long type
 Parameters
[in] a
: unsigned long type of value stored in a[in] b
: int type of value stored in b

__STATIC_FORCEINLINE unsigned long __RV_SLL16(unsigned long a, unsigned int b)
SLL16 (SIMD 16bit Shift Left Logical)
Type: SIMD
Syntax:
SLL16 Rd, Rs1, Rs2
Purpose:
Do 16bit elements logical left shift operations simultaneously. The shift amount is a variable from a GPR.
Description:
The 16bit elements in Rs1 are leftshifted logically. And the results are written to Rd. The shifted out bits are filled with zero and the shift amount is specified by the loworder 4bits of the value in the Rs2 register.
Operations:
sa = Rs2[3:0]; Rd.H[x] = Rs1.H[x] << sa; for RV32: x=1...0, for RV64: x=3...0
 Return
value stored in unsigned long type
 Parameters
[in] a
: unsigned long type of value stored in a[in] b
: unsigned int type of value stored in b

__STATIC_FORCEINLINE unsigned long __RV_SRA16(unsigned long a, unsigned long b)
SRA16 (SIMD 16bit Shift Right Arithmetic)
Type: SIMD
Syntax:
SRA16 Rd, Rs1, Rs2 SRA16.u Rd, Rs1, Rs2
Purpose:
Do 16bit element arithmetic right shift operations simultaneously. The shift amount is a variable from a GPR. The
.u
form performs additional rounding up operations on the shifted results.Description:
The 16bit data elements in Rs1 are rightshifted arithmetically, that is, the shifted out bits are filled with the signbit of the data elements. The shift amount is specified by the loworder 4bits of the value in the Rs2 register. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 16bit data element to calculate the final results. And the results are written to Rd.Operations:
sa = Rs2[3:0]; if (sa != 0) { if (`.u` form) { // SRA16.u res[15:1] = SE17(Rs1.H[x][15:sa1]) + 1; Rd.H[x] = res[15:0]; } else { // SRA16 Rd.H[x] = SE16(Rs1.H[x][15:sa]) } } else { Rd = Rs1; } for RV32: x=1...0, for RV64: x=3...0
 Return
value stored in unsigned long type
 Parameters
[in] a
: unsigned long type of value stored in a[in] b
: unsigned long type of value stored in b

__STATIC_FORCEINLINE unsigned long __RV_SRA16_U(unsigned long a, unsigned long b)
SRA16.u (SIMD 16bit Rounding Shift Right Arithmetic)
Type: SIMD
Syntax:
SRA16 Rd, Rs1, Rs2 SRA16.u Rd, Rs1, Rs2
Purpose:
Do 16bit element arithmetic right shift operations simultaneously. The shift amount is a variable from a GPR. The
.u
form performs additional rounding up operations on the shifted results.Description:
The 16bit data elements in Rs1 are rightshifted arithmetically, that is, the shifted out bits are filled with the signbit of the data elements. The shift amount is specified by the loworder 4bits of the value in the Rs2 register. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 16bit data element to calculate the final results. And the results are written to Rd.Operations:
sa = Rs2[3:0]; if (sa != 0) { if (`.u` form) { // SRA16.u res[15:1] = SE17(Rs1.H[x][15:sa1]) + 1; Rd.H[x] = res[15:0]; } else { // SRA16 Rd.H[x] = SE16(Rs1.H[x][15:sa]) } } else { Rd = Rs1; } for RV32: x=1...0, for RV64: x=3...0
 Return
value stored in unsigned long type
 Parameters
[in] a
: unsigned long type of value stored in a[in] b
: unsigned long type of value stored in b

__STATIC_FORCEINLINE unsigned long __RV_SRL16(unsigned long a, unsigned int b)
SRL16 (SIMD 16bit Shift Right Logical)
Type: SIMD
Syntax:
SRL16 Rt, Ra, Rb SRL16.u Rt, Ra, Rb
Purpose:
Do 16bit elements logical right shift operations simultaneously. The shift amount is a variable from a GPR. The
.u
form performs additional rounding upoperations on the shifted results.Description:
The 16bit data elements in Rs1 are rightshifted logically, that is, the shifted out bits are filled with zero. The shift amount is specified by the loworder 4bits of the value in the Rs2 register. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 16bit data element to calculate the final results. And the results are written to Rd.Operations:
sa = Rs2[3:0]; if (sa > 0) { if (`.u` form) { // SRL16.u res[16:0] = ZE17(Rs1.H[x][15:sa1]) + 1; Rd.H[x] = res[16:1]; } else { // SRL16 Rd.H[x] = ZE16(Rs1.H[x][15:sa]); } } else { Rd = Rs1; } for RV32: x=1...0, for RV64: x=3...0
 Return
value stored in unsigned long type
 Parameters
[in] a
: unsigned long type of value stored in a[in] b
: unsigned int type of value stored in b

__STATIC_FORCEINLINE unsigned long __RV_SRL16_U(unsigned long a, unsigned int b)
SRL16.u (SIMD 16bit Rounding Shift Right Logical)
Type: SIMD
Syntax:
SRL16 Rt, Ra, Rb SRL16.u Rt, Ra, Rb
Purpose:
Do 16bit elements logical right shift operations simultaneously. The shift amount is a variable from a GPR. The
.u
form performs additional rounding upoperations on the shifted results.Description:
The 16bit data elements in Rs1 are rightshifted logically, that is, the shifted out bits are filled with zero. The shift amount is specified by the loworder 4bits of the value in the Rs2 register. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 16bit data element to calculate the final results. And the results are written to Rd.Operations:
sa = Rs2[3:0]; if (sa > 0) { if (`.u` form) { // SRL16.u res[16:0] = ZE17(Rs1.H[x][15:sa1]) + 1; Rd.H[x] = res[16:1]; } else { // SRL16 Rd.H[x] = ZE16(Rs1.H[x][15:sa]); } } else { Rd = Rs1; } for RV32: x=1...0, for RV64: x=3...0
 Return
value stored in unsigned long type
 Parameters
[in] a
: unsigned long type of value stored in a[in] b
: unsigned int type of value stored in b
