NMSIS Core API
If you want to access doxygen generated NMSIS Core API, please click NMSIS Core Doxygen API Documentation.
- Version Control
- Compiler Control
__has_builtin
__ASM
__INLINE
__STATIC_INLINE
__STATIC_FORCEINLINE
__NO_RETURN
__USED
__WEAK
__VECTOR_SIZE
__PACKED
__PACKED_STRUCT
__PACKED_UNION
__UNALIGNED_UINT16_WRITE
__UNALIGNED_UINT16_READ
__UNALIGNED_UINT32_WRITE
__UNALIGNED_UINT32_READ
__ALIGNED
__RESTRICT
__COMPILER_BARRIER
__USUALLY
__RARELY
__INTERRUPT
__MACHINE_INTERRUPT
__SUPERVISOR_INTERRUPT
__USER_INTERRUPT
T_UINT16_WRITE
T_UINT16_READ
T_UINT32_WRITE
T_UINT32_READ
- Core CSR Register Access
- Core CSR Encoding
- Register Define and Type Definitions
- CPU Intrinsic Functions
- Intrinsic Functions for SIMD Instructions
- SIMD Data Processing Instructions
- Non-SIMD Instructions
- Partial-SIMD Data Processing Instructions
- 64-bit Profile Instructions
- RV64 Only Instructions
- Nuclei Default SIMD DSP Additional Instructions
- Nuclei N1 SIMD DSP Additional Instructions
- Nuclei N2 SIMD DSP Additional Instructions
- Nuclei N3 SIMD DSP Additional Instructions
- Intrinsic Functions for Bitmanipulation Instructions
- Intrinsic Functions for Vector Instructions
- Peripheral Access
- Systick Timer(SysTimer)
- Interrupts and Exceptions
- PLIC Interrupt
PLIC_Init
PLIC_Init_S
PLIC_ClaimInterrupt
PLIC_ClaimInterrupt_S
PLIC_CompleteInterrupt
PLIC_CompleteInterrupt_S
PLIC_GetInterruptEnable
PLIC_GetInterruptEnable_S
PLIC_EnableInterrupt
PLIC_EnableInterrupt_S
PLIC_DisableInterrupt
PLIC_DisableInterrupt_S
PLIC_SetThreshold
PLIC_SetThreshold_S
PLIC_GetThreshold
PLIC_GetThreshold_S
- CIDU Functions
- FPU Functions
- PMP Functions
- SPMP/sMPU Functions
- PMA Functions
- Cache Functions
- System Device Configuration
CLINT_MSIP
SMP_CTRLREG
exc_entry_s()
irq_entry_s()
default_intexc_handler()
SystemCoreClockUpdate()
SystemInit()
SystemBannerPrint()
irq_entry()
exc_entry()
ECLIC_Interrupt_Init()
CLINT_Interrupt_Init()
PLIC_Interrupt_Init()
Interrupt_Init()
ECLIC_Register_IRQ()
Core_Register_IRQ()
Core_Register_IRQ_S()
PLIC_Register_IRQ()
PLIC_Register_IRQ_S()
ECLIC_Register_IRQ_S()
__sync_harts()
Trap_Init()
_premain_init()
_postmain_fini()
_init()
_fini()
SystemCoreClock
vector_base
CpuIRegionBase
- Interrupt Exception NMI Handling
- ARM Compatiable Functions
- NMSIS Bench and Test Helper Functions
READ_CYCLE
BENCH_DECLARE_VAR
BENCH_INIT
BENCH_RESET
BENCH_START
BENCH_SAMPLE
BENCH_END
BENCH_STOP
BENCH_STAT
BENCH_GET_USECYC
BENCH_GET_SUMCYC
BENCH_GET_LPCNT
BENCH_ERROR
BENCH_STATUS
EVENT_SEL_INSTRUCTION_COMMIT
EVENT_SEL_MEMORY_ACCESS
EVENT_SEL_TYPE_0
EVENT_SEL_TYPE_1
EVENT_SEL_TYPE_2
EVENT_SEL_TYPE_3
EVENT_INSTRUCTION_COMMIT_CYCLE_COUNT
EVENT_INSTRUCTION_COMMIT_RETIRED_COUNT
EVENT_INSTRUCTION_COMMIT_INTEGER_LOAD
EVENT_INSTRUCTION_COMMIT_INTEGER_STORE
EVENT_INSTRUCTION_COMMIT_ATOMIC_MEMORY_OPERATION
EVENT_INSTRUCTION_COMMIT_SYSTEM
EVENT_INSTRUCTION_COMMIT_INTEGER_COMPUTATIONAL
EVENT_INSTRUCTION_COMMIT_CONDITIONAL_BRANCH
EVENT_INSTRUCTION_COMMIT_TAKEN_CONDITIONAL_BRANCH
EVENT_INSTRUCTION_COMMIT_JAL
EVENT_INSTRUCTION_COMMIT_JALR
EVENT_INSTRUCTION_COMMIT_RETURN
EVENT_INSTRUCTION_COMMIT_CONTROL_TRANSFER
EVENT_INSTRUCTION_COMMIT_FENCE_INSTRUCTION
EVENT_INSTRUCTION_COMMIT_INTEGER_MULTIPLICATION
EVENT_INSTRUCTION_COMMIT_INTEGER_DIVISION_REMAINDER
EVENT_INSTRUCTION_COMMIT_FLOATING_POINT_LOAD
EVENT_INSTRUCTION_COMMIT_FLOATING_POINT_STORE
EVENT_INSTRUCTION_COMMIT_FLOATING_POINT_ADDITION_SUBTRACTION
EVENT_INSTRUCTION_COMMIT_FLOATING_POINT_MULTIPLICATION
EVENT_INSTRUCTION_COMMIT_FLOATING_POINT_FUSED_MULTIPLY_ADD_SUB
EVENT_INSTRUCTION_COMMIT_FLOATING_POINT_DIVISION_OR_SQUARE_ROOT
EVENT_INSTRUCTION_COMMIT_OTHER_FLOATING_POINT_INSTRUCTION
EVENT_INSTRUCTION_COMMIT_CONDITIONAL_BRANCH_PREDICTION_FAIL
EVENT_INSTRUCTION_COMMIT_JALR_PREDICTION_FAIL
EVENT_INSTRUCTION_COMMIT_POP_PREDICTION_FAIL
EVENT_INSTRUCTION_COMMIT_FENCEI_INSTRUCTION
EVENT_INSTRUCTION_COMMIT_SFENCE_INSTRUCTION
EVENT_INSTRUCTION_COMMIT_ECALL_INSTRUCTION
EVENT_INSTRUCTION_COMMIT_EXCEPTION_INSTRUCTION
EVENT_INSTRUCTION_COMMIT_INTERRUPT_INSTRUCTION
EVENT_MEMORY_ACCESS_ICACHE_MISS
EVENT_MEMORY_ACCESS_DCACHE_MISS
EVENT_MEMORY_ACCESS_ITLB_MISS
EVENT_MEMORY_ACCESS_DTLB_MISS
EVENT_MEMORY_ACCESS_MAIN_DTLB_MISS
EVENT_MEMORY_ACCESS_MAIN_TLB_MISS
EVENT_MEMORY_ACCESS_L2_CACHE_ACCESS
EVENT_MEMORY_ACCESS_L2_CACHE_MISS
EVENT_MEMORY_ACCESS_MEMORY_BUS_REQUEST
EVENT_MEMORY_ACCESS_IFU_STALL_CYCLE
EVENT_MEMORY_ACCESS_EXU_STALL_CYCLE
EVENT_MEMORY_ACCESS_TIMER
EVENT_TYPE_0_CYCLE_COUNT
EVENT_TYPE_0_RETIRED_COUNT
EVENT_TYPE_0_INTEGER_LOAD
EVENT_TYPE_0_INTEGER_STORE
EVENT_TYPE_0_ATOMIC_MEMORY_OPERATION
EVENT_TYPE_0_SYSTEM
EVENT_TYPE_0_INTEGER_COMPUTATIONAL
EVENT_TYPE_0_CONDITIONAL_BRANCH
EVENT_TYPE_0_TAKEN_CONDITIONAL_BRANCH
EVENT_TYPE_0_JAL
EVENT_TYPE_0_JALR
EVENT_TYPE_0_RETURN
EVENT_TYPE_0_CONTROL_TRANSFER
EVENT_TYPE_0_FENCE_INSTRUCTION
EVENT_TYPE_0_INTEGER_MULTIPLICATION
EVENT_TYPE_0_INTEGER_DIVISION_REMAINDER
EVENT_TYPE_0_FLOATING_POINT_LOAD
EVENT_TYPE_0_FLOATING_POINT_STORE
EVENT_TYPE_0_FLOATING_POINT_ADDITION_SUBTRACTION
EVENT_TYPE_0_FLOATING_POINT_MULTIPLICATION
EVENT_TYPE_0_FLOATING_POINT_FUSED_MULTIPLY_ADD_SUB
EVENT_TYPE_0_FLOATING_POINT_DIVISION_OR_SQUARE_ROOT
EVENT_TYPE_0_OTHER_FLOATING_POINT_INSTRUCTION
EVENT_TYPE_0_CONDITIONAL_BRANCH_PREDICTION_FAIL
EVENT_TYPE_0_JALR_PREDICTION_FAIL
EVENT_TYPE_0_POP_PREDICTION_FAIL
EVENT_TYPE_0_FENCEI_INSTRUCTION
EVENT_TYPE_0_SFENCE_INSTRUCTION
EVENT_TYPE_0_ECALL_INSTRUCTION
EVENT_TYPE_0_EXCEPTION_INSTRUCTION
EVENT_TYPE_0_INTERRUPT_INSTRUCTION
EVENT_TYPE_1_ICACHE_READ_MISS
EVENT_TYPE_1_DCACHE_RW_MISS
EVENT_TYPE_1_ITLB_READ_MISS
EVENT_TYPE_1_DTLB_RW_MISS
EVENT_TYPE_1_MAIN_TLB_MISS
EVENT_TYPE_1_L2_CACHE_ACCESS
EVENT_TYPE_1_L2_CACHE_MISS
EVENT_TYPE_1_MEMORY_BUS_REQUEST
EVENT_TYPE_1_IFU_STALL_CYCLE
EVENT_TYPE_1_EXU_STALL_CYCLE
EVENT_TYPE_1_TIMER
EVENT_TYPE_2_BRANCH_INSTRUCTION_COMMIT
EVENT_TYPE_2_BRANCH_PREDICT_FAIL_COMMIT
EVENT_TYPE_3_DCACHE_READ
EVENT_TYPE_3_DCACHE_READ_MISS
EVENT_TYPE_3_DCACHE_WRITE
EVENT_TYPE_3_DCACHE_WRITE_MISS
EVENT_TYPE_3_DCACHE_PREFETCH
EVENT_TYPE_3_DCACHE_PREFETCH_MISS
EVENT_TYPE_3_ICACHE_READ
EVENT_TYPE_3_ICACHE_PREFETCH
EVENT_TYPE_3_ICACHE_PREFETCH_MISS
EVENT_TYPE_3_L2_CACHE_READ_HIT
EVENT_TYPE_3_L2_CACHE_READ_MISS
EVENT_TYPE_3_L2_CACHE_WRITE_HIT
EVENT_TYPE_3_L2_CACHE_WRITE_MISS
EVENT_TYPE_3_L2_CACHE_PREFETCH_HIT
EVENT_TYPE_3_L2_CACHE_PREFETCH_MISS
EVENT_TYPE_3_DTLB_READ
EVENT_TYPE_3_DTLB_READ_MISS
EVENT_TYPE_3_DTLB_WRITE
EVENT_TYPE_3_DTLB_WRITE_MISS
EVENT_TYPE_3_ITLB_READ
EVENT_TYPE_3_BTB_READ
EVENT_TYPE_3_BTB_READ_MISS
EVENT_TYPE_3_BTB_WRITE
EVENT_TYPE_3_BTB_WRITE_MISS
MSU_EVENT_ENABLE
MEVENT_EN
SEVENT_EN
UEVENT_EN
READ_HPM_COUNTER
HPM_DECLARE_VAR
HPM_SEL_ENABLE
HPM_SEL_EVENT
HPM_EVENT
HPM_INIT
HPM_RESET
HPM_START
HPM_SAMPLE
HPM_END
HPM_STOP
HPM_STAT
HPM_GET_USECYC
HPM_GET_SUMCYC
HPM_GET_LPCNT
NMSIS_TEST_PASS
NMSIS_TEST_FAIL