NMSIS Core API
If you want to access doxygen generated NMSIS Core API, please click NMSIS Core Doxygen API Documentation.
- Version Control
- Compiler Control
__has_builtin__ASM__INLINE__STATIC_INLINE__STATIC_FORCEINLINE__NO_RETURN__USED__WEAK__VECTOR_SIZE__PACKED__PACKED_STRUCT__PACKED_UNION__UNALIGNED_UINT16_WRITE__UNALIGNED_UINT16_READ__UNALIGNED_UINT32_WRITE__UNALIGNED_UINT32_READ__ALIGNED__RESTRICT__COMPILER_BARRIER__USUALLY__RARELY__INTERRUPT__MACHINE_INTERRUPT__SUPERVISOR_INTERRUPT__USER_INTERRUPTT_UINT16_WRITET_UINT16_READT_UINT32_WRITET_UINT32_READ
- Core CSR Register Access
- Core CSR Encoding
- Register Define and Type Definitions
- CPU Intrinsic Functions
- Intrinsic Functions for SIMD Instructions
- SIMD Data Processing Instructions
- Non-SIMD Instructions
- Partial-SIMD Data Processing Instructions
- 64-bit Profile Instructions
- RV64 Only Instructions
- Nuclei Default SIMD DSP Additional Instructions
- Nuclei N1 SIMD DSP Additional Instructions
- Nuclei N2 SIMD DSP Additional Instructions
- Nuclei N3 SIMD DSP Additional Instructions
- Intrinsic Functions for Bitmanipulation Instructions
- Intrinsic Functions for Vector Instructions
- Peripheral Access
- Systick Timer(SysTimer)
- Interrupts and Exceptions
- PLIC Interrupt
PLIC_InitPLIC_Init_SPLIC_ClaimInterruptPLIC_ClaimInterrupt_SPLIC_CompleteInterruptPLIC_CompleteInterrupt_SPLIC_GetInterruptEnablePLIC_GetInterruptEnable_SPLIC_EnableInterruptPLIC_EnableInterrupt_SPLIC_DisableInterruptPLIC_DisableInterrupt_SPLIC_SetThresholdPLIC_SetThreshold_SPLIC_GetThresholdPLIC_GetThreshold_S
- CIDU Functions
- FPU Functions
- PMP Functions
- SPMP/sMPU Functions
- PMA Functions
- Cache Functions
- System Device Configuration
CLINT_MSIPSMP_CTRLREGexc_entry_s()irq_entry_s()default_intexc_handler()SystemCoreClockUpdate()SystemInit()SystemBannerPrint()irq_entry()exc_entry()ECLIC_Interrupt_Init()CLINT_Interrupt_Init()PLIC_Interrupt_Init()Interrupt_Init()ECLIC_Register_IRQ()Core_Register_IRQ()Core_Register_IRQ_S()PLIC_Register_IRQ()PLIC_Register_IRQ_S()ECLIC_Register_IRQ_S()__sync_harts()Trap_Init()_premain_init()_postmain_fini()_init()_fini()SystemCoreClockvector_baseCpuIRegionBase- Interrupt Exception NMI Handling
- ARM Compatiable Functions
- NMSIS Bench and Test Helper Functions
READ_CYCLEBENCH_DECLARE_VARBENCH_INITBENCH_RESETBENCH_STARTBENCH_SAMPLEBENCH_ENDBENCH_STOPBENCH_STATBENCH_GET_USECYCBENCH_GET_SUMCYCBENCH_GET_LPCNTBENCH_ERRORBENCH_STATUSEVENT_SEL_INSTRUCTION_COMMITEVENT_SEL_MEMORY_ACCESSEVENT_SEL_TYPE_0EVENT_SEL_TYPE_1EVENT_SEL_TYPE_2EVENT_SEL_TYPE_3EVENT_INSTRUCTION_COMMIT_CYCLE_COUNTEVENT_INSTRUCTION_COMMIT_RETIRED_COUNTEVENT_INSTRUCTION_COMMIT_INTEGER_LOADEVENT_INSTRUCTION_COMMIT_INTEGER_STOREEVENT_INSTRUCTION_COMMIT_ATOMIC_MEMORY_OPERATIONEVENT_INSTRUCTION_COMMIT_SYSTEMEVENT_INSTRUCTION_COMMIT_INTEGER_COMPUTATIONALEVENT_INSTRUCTION_COMMIT_CONDITIONAL_BRANCHEVENT_INSTRUCTION_COMMIT_TAKEN_CONDITIONAL_BRANCHEVENT_INSTRUCTION_COMMIT_JALEVENT_INSTRUCTION_COMMIT_JALREVENT_INSTRUCTION_COMMIT_RETURNEVENT_INSTRUCTION_COMMIT_CONTROL_TRANSFEREVENT_INSTRUCTION_COMMIT_FENCE_INSTRUCTIONEVENT_INSTRUCTION_COMMIT_INTEGER_MULTIPLICATIONEVENT_INSTRUCTION_COMMIT_INTEGER_DIVISION_REMAINDEREVENT_INSTRUCTION_COMMIT_FLOATING_POINT_LOADEVENT_INSTRUCTION_COMMIT_FLOATING_POINT_STOREEVENT_INSTRUCTION_COMMIT_FLOATING_POINT_ADDITION_SUBTRACTIONEVENT_INSTRUCTION_COMMIT_FLOATING_POINT_MULTIPLICATIONEVENT_INSTRUCTION_COMMIT_FLOATING_POINT_FUSED_MULTIPLY_ADD_SUBEVENT_INSTRUCTION_COMMIT_FLOATING_POINT_DIVISION_OR_SQUARE_ROOTEVENT_INSTRUCTION_COMMIT_OTHER_FLOATING_POINT_INSTRUCTIONEVENT_INSTRUCTION_COMMIT_CONDITIONAL_BRANCH_PREDICTION_FAILEVENT_INSTRUCTION_COMMIT_JALR_PREDICTION_FAILEVENT_INSTRUCTION_COMMIT_POP_PREDICTION_FAILEVENT_INSTRUCTION_COMMIT_FENCEI_INSTRUCTIONEVENT_INSTRUCTION_COMMIT_SFENCE_INSTRUCTIONEVENT_INSTRUCTION_COMMIT_ECALL_INSTRUCTIONEVENT_INSTRUCTION_COMMIT_EXCEPTION_INSTRUCTIONEVENT_INSTRUCTION_COMMIT_INTERRUPT_INSTRUCTIONEVENT_MEMORY_ACCESS_ICACHE_MISSEVENT_MEMORY_ACCESS_DCACHE_MISSEVENT_MEMORY_ACCESS_ITLB_MISSEVENT_MEMORY_ACCESS_DTLB_MISSEVENT_MEMORY_ACCESS_MAIN_DTLB_MISSEVENT_MEMORY_ACCESS_MAIN_TLB_MISSEVENT_MEMORY_ACCESS_L2_CACHE_ACCESSEVENT_MEMORY_ACCESS_L2_CACHE_MISSEVENT_MEMORY_ACCESS_MEMORY_BUS_REQUESTEVENT_MEMORY_ACCESS_IFU_STALL_CYCLEEVENT_MEMORY_ACCESS_EXU_STALL_CYCLEEVENT_MEMORY_ACCESS_TIMEREVENT_TYPE_0_CYCLE_COUNTEVENT_TYPE_0_RETIRED_COUNTEVENT_TYPE_0_INTEGER_LOADEVENT_TYPE_0_INTEGER_STOREEVENT_TYPE_0_ATOMIC_MEMORY_OPERATIONEVENT_TYPE_0_SYSTEMEVENT_TYPE_0_INTEGER_COMPUTATIONALEVENT_TYPE_0_CONDITIONAL_BRANCHEVENT_TYPE_0_TAKEN_CONDITIONAL_BRANCHEVENT_TYPE_0_JALEVENT_TYPE_0_JALREVENT_TYPE_0_RETURNEVENT_TYPE_0_CONTROL_TRANSFEREVENT_TYPE_0_FENCE_INSTRUCTIONEVENT_TYPE_0_INTEGER_MULTIPLICATIONEVENT_TYPE_0_INTEGER_DIVISION_REMAINDEREVENT_TYPE_0_FLOATING_POINT_LOADEVENT_TYPE_0_FLOATING_POINT_STOREEVENT_TYPE_0_FLOATING_POINT_ADDITION_SUBTRACTIONEVENT_TYPE_0_FLOATING_POINT_MULTIPLICATIONEVENT_TYPE_0_FLOATING_POINT_FUSED_MULTIPLY_ADD_SUBEVENT_TYPE_0_FLOATING_POINT_DIVISION_OR_SQUARE_ROOTEVENT_TYPE_0_OTHER_FLOATING_POINT_INSTRUCTIONEVENT_TYPE_0_CONDITIONAL_BRANCH_PREDICTION_FAILEVENT_TYPE_0_JALR_PREDICTION_FAILEVENT_TYPE_0_POP_PREDICTION_FAILEVENT_TYPE_0_FENCEI_INSTRUCTIONEVENT_TYPE_0_SFENCE_INSTRUCTIONEVENT_TYPE_0_ECALL_INSTRUCTIONEVENT_TYPE_0_EXCEPTION_INSTRUCTIONEVENT_TYPE_0_INTERRUPT_INSTRUCTIONEVENT_TYPE_1_ICACHE_READ_MISSEVENT_TYPE_1_DCACHE_RW_MISSEVENT_TYPE_1_ITLB_READ_MISSEVENT_TYPE_1_DTLB_RW_MISSEVENT_TYPE_1_MAIN_TLB_MISSEVENT_TYPE_1_L2_CACHE_ACCESSEVENT_TYPE_1_L2_CACHE_MISSEVENT_TYPE_1_MEMORY_BUS_REQUESTEVENT_TYPE_1_IFU_STALL_CYCLEEVENT_TYPE_1_EXU_STALL_CYCLEEVENT_TYPE_1_TIMEREVENT_TYPE_2_BRANCH_INSTRUCTION_COMMITEVENT_TYPE_2_BRANCH_PREDICT_FAIL_COMMITEVENT_TYPE_3_DCACHE_READEVENT_TYPE_3_DCACHE_READ_MISSEVENT_TYPE_3_DCACHE_WRITEEVENT_TYPE_3_DCACHE_WRITE_MISSEVENT_TYPE_3_DCACHE_PREFETCHEVENT_TYPE_3_DCACHE_PREFETCH_MISSEVENT_TYPE_3_ICACHE_READEVENT_TYPE_3_ICACHE_PREFETCHEVENT_TYPE_3_ICACHE_PREFETCH_MISSEVENT_TYPE_3_L2_CACHE_READ_HITEVENT_TYPE_3_L2_CACHE_READ_MISSEVENT_TYPE_3_L2_CACHE_WRITE_HITEVENT_TYPE_3_L2_CACHE_WRITE_MISSEVENT_TYPE_3_L2_CACHE_PREFETCH_HITEVENT_TYPE_3_L2_CACHE_PREFETCH_MISSEVENT_TYPE_3_DTLB_READEVENT_TYPE_3_DTLB_READ_MISSEVENT_TYPE_3_DTLB_WRITEEVENT_TYPE_3_DTLB_WRITE_MISSEVENT_TYPE_3_ITLB_READEVENT_TYPE_3_BTB_READEVENT_TYPE_3_BTB_READ_MISSEVENT_TYPE_3_BTB_WRITEEVENT_TYPE_3_BTB_WRITE_MISSMSU_EVENT_ENABLEMEVENT_ENSEVENT_ENUEVENT_ENREAD_HPM_COUNTERHPM_DECLARE_VARHPM_SEL_ENABLEHPM_SEL_EVENTHPM_EVENTHPM_INITHPM_RESETHPM_STARTHPM_SAMPLEHPM_ENDHPM_STOPHPM_STATHPM_GET_USECYCHPM_GET_SUMCYCHPM_GET_LPCNTNMSIS_TEST_PASSNMSIS_TEST_FAIL