Register Define and Type Definitions

group NMSIS_Core_Registers

Type definitions and defines for core registers.

Defines

__RISCV_XLEN 32

Refer to the width of an integer register in bits(either 32 or 64)

Typedefs

typedef uint32_t rv_csr_t

Type of Control and Status Register(CSR), depends on the XLEN defined in RISC-V.

Core

group NMSIS_Core_Base_Registers

Type definitions and defines for base core registers.

union CSR_MISA_Type
#include <core_feature_base.h>

Union type to access MISA register.

Public Members

rv_csr_t a

bit: 0 Atomic extension

rv_csr_t b

bit: 1 Tentatively reserved for Bit-Manipulation extension

rv_csr_t c

bit: 2 Compressed extension

rv_csr_t d

bit: 3 Double-precision floating-point extension

Type used for csr data access.

rv_csr_t e

bit: 4 RV32E base ISA

rv_csr_t f

bit: 5 Single-precision floating-point extension

rv_csr_t g

bit: 6 Additional standard extensions present

rv_csr_t h

bit: 7 Hypervisor extension

rv_csr_t i

bit: 8 RV32I/64I/128I base ISA

rv_csr_t j

bit: 9 Tentatively reserved for Dynamically Translated Languages extension

rv_csr_t _reserved1

bit: 10 Reserved

rv_csr_t l

bit: 11 Tentatively reserved for Decimal Floating-Point extension

rv_csr_t m

bit: 12 Integer Multiply/Divide extension

rv_csr_t n

bit: 13 User-level interrupts supported

rv_csr_t _reserved2

bit: 14 Reserved

rv_csr_t p

bit: 15 Tentatively reserved for Packed-SIMD extension

rv_csr_t q

bit: 16 Quad-precision floating-point extension

rv_csr_t _resreved3

bit: 17 Reserved

rv_csr_t s

bit: 18 Supervisor mode implemented

rv_csr_t t

bit: 19 Tentatively reserved for Transactional Memory extension

rv_csr_t u

bit: 20 User mode implemented

rv_csr_t v

bit: 21 Tentatively reserved for Vector extension

rv_csr_t _reserved4

bit: 22 Reserved

rv_csr_t x

bit: 23 Non-standard extensions present

rv_csr_t _reserved5

bit: 24..29 Reserved

rv_csr_t mxl

bit: 30..31 Machine XLEN

struct CSR_MISA_Type::[anonymous] b

Structure used for bit access.

union CSR_MSTATUS_Type
#include <core_feature_base.h>

Union type to access MSTATUS configure register.

Public Members

rv_csr_t _reserved0

bit: 0 Reserved

rv_csr_t sie

bit: 1 supervisor interrupt enable flag

rv_csr_t _reserved1

bit: 2 Reserved

rv_csr_t mie

bit: 3 Machine mode interrupt enable flag

rv_csr_t _reserved2

bit: 4 Reserved

rv_csr_t spie

bit: 3 Supervisor Privilede mode interrupt enable flag

rv_csr_t _reserved3

bit: Reserved

rv_csr_t mpie

bit: mirror of MIE flag

rv_csr_t _reserved4

bit: Reserved

rv_csr_t mpp

bit: mirror of Privilege Mode

rv_csr_t fs

bit: FS status flag

rv_csr_t xs

bit: XS status flag

rv_csr_t mprv

bit: Machine mode PMP

rv_csr_t sum

bit: Supervisor Mode load and store protection

rv_csr_t _reserved6

bit: 19..30 Reserved

rv_csr_t sd

bit: Dirty status for XS or FS

struct CSR_MSTATUS_Type::[anonymous] b

Structure used for bit access.

rv_csr_t d

Type used for csr data access.

union CSR_MTVEC_Type
#include <core_feature_base.h>

Union type to access MTVEC configure register.

Public Members

rv_csr_t mode

bit: 0..5 interrupt mode control

rv_csr_t addr

bit: 6..31 mtvec address

struct CSR_MTVEC_Type::[anonymous] b

Structure used for bit access.

rv_csr_t d

Type used for csr data access.

union CSR_MCAUSE_Type
#include <core_feature_base.h>

Union type to access MCAUSE configure register.

Public Members

rv_csr_t exccode

bit: 11..0 exception or interrupt code

rv_csr_t _reserved0

bit: 15..12 Reserved

rv_csr_t mpil

bit: 23..16 Previous interrupt level

rv_csr_t _reserved1

bit: 26..24 Reserved

rv_csr_t mpie

bit: 27 Interrupt enable flag before enter interrupt

rv_csr_t mpp

bit: 29..28 Privilede mode flag before enter interrupt

rv_csr_t minhv

bit: 30 Machine interrupt vector table

rv_csr_t interrupt

bit: 31 trap type.

0 means exception and 1 means interrupt

struct CSR_MCAUSE_Type::[anonymous] b

Structure used for bit access.

rv_csr_t d

Type used for csr data access.

union CSR_MCOUNTINHIBIT_Type
#include <core_feature_base.h>

Union type to access MCOUNTINHIBIT configure register.

Public Members

rv_csr_t cy

bit: 0 1 means disable mcycle counter

rv_csr_t _reserved0

bit: 1 Reserved

rv_csr_t ir

bit: 2 1 means disable minstret counter

rv_csr_t _reserved1

bit: 3..31 Reserved

struct CSR_MCOUNTINHIBIT_Type::[anonymous] b

Structure used for bit access.

rv_csr_t d

Type used for csr data access.

union CSR_MSUBM_Type
#include <core_feature_base.h>

Union type to access msubm configure register.

Public Members

rv_csr_t _reserved0

bit: 0..5 Reserved

rv_csr_t typ

bit: 6..7 current trap type

rv_csr_t ptyp

bit: 8..9 previous trap type

rv_csr_t _reserved1

bit: 10..31 Reserved

struct CSR_MSUBM_Type::[anonymous] b

Structure used for bit access.

rv_csr_t d

Type used for csr data access.

union CSR_MMISCCTRL_Type
#include <core_feature_base.h>

Union type to access MMISC_CTRL configure register.

Public Members

rv_csr_t _reserved0

bit: 0..2 Reserved

rv_csr_t bpu

bit: 3 dynamic prediction enable flag

rv_csr_t _reserved1

bit: 4..5 Reserved

rv_csr_t misalign

bit: 6 misaligned access support flag

rv_csr_t _reserved2

bit: 7..8 Reserved

rv_csr_t nmi_cause

bit: 9 mnvec control and nmi mcase exccode

rv_csr_t _reserved3

bit: 10..31 Reserved

struct CSR_MMISCCTRL_Type::[anonymous] b

Structure used for bit access.

rv_csr_t d

Type used for csr data access.

union CSR_MSAVESTATUS_Type
#include <core_feature_base.h>

Union type to access MSAVESTATUS configure register.

Public Members

rv_csr_t mpie1

bit: 0 interrupt enable flag of fisrt level NMI/exception nestting

rv_csr_t mpp1

bit: 1..2 privilede mode of fisrt level NMI/exception nestting

rv_csr_t _reserved0

bit: 3..5 Reserved

rv_csr_t ptyp1

bit: 6..7 NMI/exception type of before first nestting

rv_csr_t mpie2

bit: 8 interrupt enable flag of second level NMI/exception nestting

rv_csr_t mpp2

bit: 9..10 privilede mode of second level NMI/exception nestting

rv_csr_t _reserved1

bit: 11..13 Reserved

rv_csr_t ptyp2

bit: 14..15 NMI/exception type of before second nestting

rv_csr_t _reserved2

bit: 16..31 Reserved

struct CSR_MSAVESTATUS_Type::[anonymous] b

Structure used for bit access.

rv_csr_t w

Type used for csr data access.

ECLIC

group NMSIS_Core_ECLIC_Registers

Type definitions and defines for eclic registers.

Defines

CLIC_CLICCFG_NLBIT_Pos 1U

CLIC CLICCFG: NLBIT Position.

CLIC_CLICCFG_NLBIT_Msk (0xFUL << CLIC_CLICCFG_NLBIT_Pos)

CLIC CLICCFG: NLBIT Mask.

CLIC_CLICINFO_CTLBIT_Pos 21U

CLIC INTINFO: __ECLIC_GetInfoCtlbits() Position.

CLIC_CLICINFO_CTLBIT_Msk (0xFUL << CLIC_CLICINFO_CTLBIT_Pos)

CLIC INTINFO: __ECLIC_GetInfoCtlbits() Mask.

CLIC_CLICINFO_VER_Pos 13U

CLIC CLICINFO: VERSION Position.

CLIC_CLICINFO_VER_Msk (0xFFUL << CLIC_CLICCFG_NLBIT_Pos)

CLIC CLICINFO: VERSION Mask.

CLIC_CLICINFO_NUM_Pos 0U

CLIC CLICINFO: NUM Position.

CLIC_CLICINFO_NUM_Msk (0xFFFUL << CLIC_CLICINFO_NUM_Pos)

CLIC CLICINFO: NUM Mask.

CLIC_INTIP_IP_Pos 0U

CLIC INTIP: IP Position.

CLIC_INTIP_IP_Msk (0x1UL << CLIC_INTIP_IP_Pos)

CLIC INTIP: IP Mask.

CLIC_INTIE_IE_Pos 0U

CLIC INTIE: IE Position.

CLIC_INTIE_IE_Msk (0x1UL << CLIC_INTIE_IE_Pos)

CLIC INTIE: IE Mask.

CLIC_INTATTR_TRIG_Pos 1U

CLIC INTATTR: TRIG Position.

CLIC_INTATTR_TRIG_Msk (0x3UL << CLIC_INTATTR_TRIG_Pos)

CLIC INTATTR: TRIG Mask.

CLIC_INTATTR_SHV_Pos 0U

CLIC INTATTR: SHV Position.

CLIC_INTATTR_SHV_Msk (0x1UL << CLIC_INTATTR_SHV_Pos)

CLIC INTATTR: SHV Mask.

ECLIC_MAX_NLBITS 8U

Max nlbit of the CLICINTCTLBITS.

ECLIC_MODE_MTVEC_Msk 3U

ECLIC Mode mask for MTVT CSR Register.

ECLIC_NON_VECTOR_INTERRUPT 0x0

Non-Vector Interrupt Mode of ECLIC.

ECLIC_VECTOR_INTERRUPT 0x1

Vector Interrupt Mode of ECLIC.

ECLIC_BASE __ECLIC_BASEADDR

ECLIC Base Address.

ECLIC ((CLIC_Type *) ECLIC_BASE)

CLIC configuration struct.

Enums

enum ECLIC_TRIGGER_Type

ECLIC Trigger Enum for different Trigger Type.

Values:

ECLIC_LEVEL_TRIGGER = 0x0

Level Triggerred, trig[0] = 0.

ECLIC_POSTIVE_EDGE_TRIGGER = 0x1

Postive/Rising Edge Triggered, trig[1] = 1, trig[0] = 0.

ECLIC_NEGTIVE_EDGE_TRIGGER = 0x3

Negtive/Falling Edge Triggered, trig[1] = 1, trig[0] = 0.

ECLIC_MAX_TRIGGER = 0x3

MAX Supported Trigger Mode.

union CLICCFG_Type
#include <core_feature_eclic.h>

Union type to access CLICFG configure register.

Public Members

uint8_t _reserved0

bit: 0 Overflow condition code flag

uint8_t nlbits

bit: 29 Carry condition code flag

uint8_t _reserved1

bit: 30 Zero condition code flag

uint8_t _reserved2

bit: 31 Negative condition code flag

struct CLICCFG_Type::[anonymous] b

Structure used for bit access.

uint8_t w

Type used for byte access.

union CLICINFO_Type
#include <core_feature_eclic.h>

Union type to access CLICINFO information register.

Public Members

uint32_t numint

bit: 0..12 number of maximum interrupt inputs supported

uint32_t version

bit: 13..20 20:17 for architecture version,16:13 for implementation version

uint32_t intctlbits

bit: 21..24 specifies how many hardware bits are actually implemented in the clicintctl registers

uint32_t _reserved0

bit: 25..31 Reserved

struct CLICINFO_Type::[anonymous] b

Structure used for bit access.

uint32_t w

Type used for word access.

struct CLIC_CTRL_Type
#include <core_feature_eclic.h>

Access to the structure of a vector interrupt controller.

SysTimer

group NMSIS_Core_SysTimer_Registers

Type definitions and defines for system timer registers.

Defines

SysTimer_MTIMECTL_TIMESTOP_Pos 0U

SysTick Timer MTIMECTL: TIMESTOP bit Position.

SysTimer_MTIMECTL_TIMESTOP_Msk (1UL << SysTimer_MTIMECTL_TIMESTOP_Pos)

SysTick Timer MTIMECTL: TIMESTOP Mask.

SysTimer_MTIMECTL_CMPCLREN_Pos 1U

SysTick Timer MTIMECTL: CMPCLREN bit Position.

SysTimer_MTIMECTL_CMPCLREN_Msk (1UL << SysTimer_MTIMECTL_CMPCLREN_Pos)

SysTick Timer MTIMECTL: CMPCLREN Mask.

SysTimer_MTIMECTL_CLKSRC_Pos 2U

SysTick Timer MTIMECTL: CLKSRC bit Position.

SysTimer_MTIMECTL_CLKSRC_Msk (1UL << SysTimer_MTIMECTL_CLKSRC_Pos)

SysTick Timer MTIMECTL: CLKSRC Mask.

SysTimer_MSIP_MSIP_Pos 0U

SysTick Timer MSIP: MSIP bit Position.

SysTimer_MSIP_MSIP_Msk (1UL << SysTimer_MSIP_MSIP_Pos)

SysTick Timer MSIP: MSIP Mask.

SysTimer_MTIMER_Msk (0xFFFFFFFFFFFFFFFFULL)

SysTick Timer MTIMER value Mask.

SysTimer_MTIMERCMP_Msk (0xFFFFFFFFFFFFFFFFULL)

SysTick Timer MTIMERCMP value Mask.

SysTimer_MTIMECTL_Msk (0xFFFFFFFFUL)

SysTick Timer MTIMECTL/MSTOP value Mask.

SysTimer_MSIP_Msk (0xFFFFFFFFUL)

SysTick Timer MSIP value Mask.

SysTimer_MSFTRST_Msk (0xFFFFFFFFUL)

SysTick Timer MSFTRST value Mask.

SysTimer_MSFRST_KEY (0x80000A5FUL)

SysTick Timer Software Reset Request Key.

SysTimer_BASE __SYSTIMER_BASEADDR

SysTick Base Address.

SysTimer ((SysTimer_Type *) SysTimer_BASE)

SysTick configuration struct.

struct SysTimer_Type
#include <core_feature_timer.h>

Structure type to access the System Timer (SysTimer).

Structure definition to access the system timer(SysTimer).

Remark

  • MSFTRST register is introduced in Nuclei N Core version 1.3(__NUCLEI_N_REV >= 0x0103)

  • MSTOP register is renamed to MTIMECTL register in Nuclei N Core version 1.4(__NUCLEI_N_REV >= 0x0104)

  • CMPCLREN and CLKSRC bit in MTIMECTL register is introduced in Nuclei N Core version 1.4(__NUCLEI_N_REV >= 0x0104)