Register Define and Type Definitions

group Register Define and Type Definitions

Type definitions and defines for core registers.

Defines

__RISCV_XLEN 32: Refer to the width of an integer register in bits(either 32 or 64)

Typedefs

typedef unsigned long rv_csr_t: Type of Control and Status Register(CSR), depends on the XLEN defined in RISC-V.

Core

group Base Register Define and Type Definitions

Type definitions and defines for base core registers.

Typedefs

typedef CSR_MMISCCTRL_Type CSR_MMISCCTL_Type

typedef CSR_MMISCCTRL_Type CSR_MMISC_CTL_Type

typedef CSR_MCACHECTL_Type CSR_MCACHE_CTL_Type

typedef CSR_MILMCTL_Type CSR_MILM_CTL_Type

typedef CSR_MDLMCTL_Type CSR_DILM_CTL_Type

typedef CSR_MCFGINFO_Type CSR_MCFG_INFO_Type

typedef CSR_MICFGINFO_Type CSR_MICFG_INFO_Type

typedef CSR_MDCFGINFO_Type CSR_MDCFG_INFO_Type

typedef CSR_MTLBCFGINFO_Type CSR_MTLBCFG_INFO_Type

typedef CSR_MPPICFGINFO_Type CSR_MPPICFG_INFO_Type

typedef CSR_MFIOCFGINFO_Type CSR_MFIOCFG_INFO_Type

typedef CSR_MECCLOCK_Type CSR_MECC_LOCK_Type

typedef CSR_MECCCODE_Type CSR_MECC_CODE_Type

union CSR_MISA_Type

#include <core_feature_base.h>

Union type to access MISA CSR register.

Public Members

rv_csr_t a: bit: 0 Atomic extension

rv_csr_t b: bit: 1 B extension

rv_csr_t c: bit: 2 Compressed extension

rv_csr_t d

bit: 3 Double-precision floating-point extension

Type used for csr data access.

rv_csr_t e: bit: 4 RV32E/64E base ISA

rv_csr_t f: bit: 5 Single-precision floating-point extension

rv_csr_t g: bit: 6 Reserved

rv_csr_t h: bit: 7 Hypervisor extension

rv_csr_t i: bit: 8 RV32I/64I/128I base ISA

rv_csr_t j: bit: 9 Reserved

rv_csr_t k: bit: 10 Reserved

rv_csr_t l: bit: 11 Reserved

rv_csr_t m: bit: 12 Integer Multiply/Divide extension

rv_csr_t n: bit: 13 Tentatively reserved for User-Level Interrupts extension

rv_csr_t o: bit: 14 Reserved

rv_csr_t p: bit: 15 Tentatively reserved for Packed-SIMD extension

rv_csr_t q: bit: 16 Quad-precision floating-point extension

rv_csr_t r: bit: 17 Reserved

rv_csr_t s: bit: 18 Supervisor mode implemented

rv_csr_t t: bit: 19 Reserved

rv_csr_t u: bit: 20 User mode implemented

rv_csr_t v: bit: 21 Vector extension

rv_csr_t w: bit: 22 Reserved

rv_csr_t x: bit: 23 Non-standard extensions present

rv_csr_t y: bit: 24 Reserved

rv_csr_t z: bit: 25 Reserved

rv_csr_t _reserved0: bit: 26..XLEN-3 Reserved

rv_csr_t mxl: bit: XLEN-2..XLEN-1 Machine XLEN

struct CSR_MISA_Type::[anonymous] b: Structure used for bit access.

union CSR_MSTATUS_Type

#include <core_feature_base.h>

Union type to access MSTATUS CSR register.

Public Members

rv_csr_t _reserved0: bit: 0 Reserved

rv_csr_t sie: bit: 1 supervisor interrupt enable flag

rv_csr_t _reserved1: bit: 2 Reserved

rv_csr_t mie: bit: 3 machine mode interrupt enable flag

rv_csr_t _reserved2: bit: 4 Reserved

rv_csr_t spie: bit: 5 supervisor mode interrupt enable flag

rv_csr_t ube: bit: 6 U-mode non-instruction-fetch memory accesse big-endian enable flag

rv_csr_t mpie: bit: 7 machine mode previous interrupt enable flag

rv_csr_t spp: bit: 8 supervisor previous privilede mode

rv_csr_t vs: bit: 9..10 vector status flag

rv_csr_t mpp: bit: 11..12 machine previous privilede mode

rv_csr_t fs: bit: 13..14 FS status flag

rv_csr_t xs: bit: 15..16 XS status flag

rv_csr_t mprv: bit: 17 Modify PRiVilege

rv_csr_t sum: bit: 18 Supervisor Mode load and store protection

rv_csr_t mxr: bit: 19 Make eXecutable Readable

rv_csr_t tvm: bit: 20 Trap Virtual Memory

rv_csr_t tw: bit: 21 Timeout Wait

rv_csr_t tsr: bit: 22 Trap SRET

rv_csr_t spelp: bit: 23 Supervisor mode Previous Expected Landing Pad (ELP) State

rv_csr_t sdt: bit: 24 S-mode-disable-trap

rv_csr_t _reserved3: bit: 25..30 Reserved

rv_csr_t sd: bit: 31 Dirty status for XS or FS

struct CSR_MSTATUS_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MSTATUSH_Type

#include <core_feature_base.h>

Union type to access MSTATUSH CSR register.

Public Members

rv_csr_t _reserved0: bit: 0..3 Reserved

rv_csr_t sbe: bit: 4 S-mode non-instruction-fetch memory accesse big-endian enable flag

rv_csr_t mbe: bit: 5 M-mode non-instruction-fetch memory accesse big-endian enable flag

rv_csr_t gva: bit: 6 Guest Virtual Address

rv_csr_t mpv: bit: 7 Machine Previous Virtualization Mode

rv_csr_t _reserved1: bit: 8 Reserved

rv_csr_t mpelp: bit: 9 Machine mode Previous Expected Landing Pad (ELP) State

rv_csr_t mdt: bit: 10 M-mode-disable-trap

rv_csr_t _reserved5: bit: 11..31 Reserved

struct CSR_MSTATUSH_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MTVEC_Type

#include <core_feature_base.h>

Union type to access MTVEC CSR register.

Public Members

rv_csr_t mode: bit: 0..5 interrupt mode control

rv_csr_t addr: bit: 6..XLEN-1 mtvec address

struct CSR_MTVEC_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MCAUSE_Type

#include <core_feature_base.h>

Union type to access MCAUSE CSR register.

Public Members

rv_csr_t exccode: bit: 0..11 exception or interrupt code

rv_csr_t _reserved0: bit: 12..15 Reserved

rv_csr_t mpil: bit: 16..23 Previous interrupt level

rv_csr_t _reserved1: bit: 24..26 Reserved

rv_csr_t mpie: bit: 27 Interrupt enable flag before enter interrupt

rv_csr_t mpp: bit: 28..29 Privilede mode flag before enter interrupt

rv_csr_t minhv: bit: 30 Machine interrupt vector table

rv_csr_t interrupt

bit: XLEN-1 trap type.

0 means exception and 1 means interrupt

struct CSR_MCAUSE_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MCOUNTINHIBIT_Type

#include <core_feature_base.h>

Union type to access MCOUNTINHIBIT CSR register.

Public Members

rv_csr_t cy: bit: 0 1 means disable mcycle counter

rv_csr_t _reserved0: bit: 1 Reserved

rv_csr_t ir: bit: 2 1 means disable minstret counter

rv_csr_t _reserved1: bit: 3..XLEN-1 Reserved

struct CSR_MCOUNTINHIBIT_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MSUBM_Type

#include <core_feature_base.h>

Union type to access MSUBM CSR register.

Public Members

rv_csr_t _reserved0: bit: 0..5 Reserved

rv_csr_t typ: bit: 6..7 current trap type

rv_csr_t ptyp: bit: 8..9 previous trap type

rv_csr_t _reserved1: bit: 10..XLEN-1 Reserved

struct CSR_MSUBM_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MDCAUSE_Type

#include <core_feature_base.h>

Union type to access MDCAUSE CSR register.

Public Members

rv_csr_t mdcause: bit: 0..2 More detailed exception information as MCAUSE supplement

rv_csr_t _reserved0: bit: 3..XLEN-1 Reserved

struct CSR_MDCAUSE_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MMISCCTRL_Type

#include <core_feature_base.h>

Union type to access MMISC_CTRL CSR register.

Public Members

rv_csr_t _reserved0: bit: 0 Reserved

rv_csr_t zclsd_en: bit: 1 Control the Zclsd will uses the Zcf extension encoding or not

rv_csr_t _reserved1: bit: 2 Reserved

rv_csr_t bpu: bit: 3 dynamic prediction enable flag

rv_csr_t _reserved2: bit: 4..5 Reserved

rv_csr_t misalign: bit: 6 misaligned access support flag

rv_csr_t zcmt_zcmp: bit: 7 Zc Ext uses the cfdsp of D Ext’s encoding or not

rv_csr_t core_buserr: bit: 8 core bus error exception or interrupt

rv_csr_t nmi_cause: bit: 9 mnvec control and nmi mcase exccode

rv_csr_t imreturn_en: bit: 10 IMRETURN mode of trace

rv_csr_t sijump_en: bit: 11 SIJUMP mode of trace

rv_csr_t ldspec_en: bit: 12 enable load speculative goes to mem interface

rv_csr_t _reserved3: bit: 13 Reserved

rv_csr_t dbg_sec: bit: 14 debug access mode, removed in latest releases

rv_csr_t _reserved4: bit: 15..16 Reserved

rv_csr_t csr_excl_enable: bit: 17 Exclusive instruction(lr,sc) on Non-cacheable/Device memory can send exclusive flag in memory bus

rv_csr_t _reserved5: bit: 18..XLEN-1 Reserved

struct CSR_MMISCCTRL_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MCACHECTL_Type

#include <core_feature_base.h>

Union type to access MCACHE_CTL CSR register.

Public Members

rv_csr_t ic_en: bit: 0 I-Cache enable

rv_csr_t ic_scpd_mod: bit: 1 Scratchpad mode, 0: Scratchpad as ICache Data RAM, 1: Scratchpad as ILM SRAM

rv_csr_t ic_ecc_en: bit: 2 I-Cache ECC enable

rv_csr_t ic_ecc_excp_en: bit: 3 I-Cache 2bit ECC error exception enable

rv_csr_t ic_rwtecc: bit: 4 Control I-Cache Tag Ram ECC code injection

rv_csr_t ic_rwdecc: bit: 5 Control I-Cache Data Ram ECC code injection

rv_csr_t ic_pf_en: bit: 6 I-Cache prefetch enable

rv_csr_t ic_cancel_en: bit: 7 I-Cache change flow canceling enable control

rv_csr_t ic_ecc_chk_en: bit: 8 I-Cache check ECC codes enable

rv_csr_t ic_prefetch_en: bit: 9 I-Cache CMO prefetch enable control

rv_csr_t ic_burst_type: bit: 10 I-Cache Burst type control

rv_csr_t _reserved0: bit: 11..15 Reserved

rv_csr_t dc_en: bit: 16 DCache enable

rv_csr_t dc_ecc_en: bit: 17 D-Cache ECC enable

rv_csr_t dc_ecc_excp_en: bit: 18 D-Cache 2bit ECC error exception enable

rv_csr_t dc_rwtecc: bit: 19 Control D-Cache Tag Ram ECC code injection

rv_csr_t dc_rwdecc: bit: 20 Control D-Cache Data Ram ECC code injection

rv_csr_t dc_ecc_chk_en: bit: 21 D-Cache check ECC codes enable

rv_csr_t dc_prefetch_en: bit: 22 D-Cache CMO prefetch enable control

rv_csr_t dc_burst_type: bit: 23 D-Cache Burst type control

rv_csr_t _reserved1: bit: 24..XLEN-1 Reserved

struct CSR_MCACHECTL_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MSAVESTATUS_Type

#include <core_feature_base.h>

Union type to access MSAVESTATUS CSR register.

Public Members

rv_csr_t mpie1: bit: 0 interrupt enable flag of fisrt level NMI/exception nestting

rv_csr_t mpp1: bit: 1..2 privilede mode of fisrt level NMI/exception nestting

rv_csr_t _reserved0: bit: 3..5 Reserved

rv_csr_t ptyp1: bit: 6..7 NMI/exception type of before first nestting

rv_csr_t mpie2: bit: 8 interrupt enable flag of second level NMI/exception nestting

rv_csr_t mpp2: bit: 9..10 privilede mode of second level NMI/exception nestting

rv_csr_t _reserved1: bit: 11..13 Reserved

rv_csr_t ptyp2: bit: 14..15 NMI/exception type of before second nestting

rv_csr_t _reserved2: bit: 16..XLEN-1 Reserved

struct CSR_MSAVESTATUS_Type::[anonymous] b: Structure used for bit access.

rv_csr_t w: Type used for csr data access.

union CSR_MILMCTL_Type

#include <core_feature_base.h>

Union type to access MILM_CTL CSR register.

Public Members

rv_csr_t ilm_en: bit: 0 ILM enable

rv_csr_t ilm_ecc_en: bit: 1 ILM ECC eanble

rv_csr_t ilm_ecc_excp_en: bit: 2 ILM ECC exception enable

rv_csr_t ilm_rwecc: bit: 3 Control mecc_code write to ilm, simulate error injection

rv_csr_t ilm_ecc_chk_en: bit: 4 ILM check ECC codes enable

rv_csr_t ilm_va_en: bit: 5 Using virtual address to judge ILM access

rv_csr_t _reserved0: bit: 6..9 Reserved

rv_csr_t ilm_bpa: bit: 10..XLEN-1 ILM base address

struct CSR_MILMCTL_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MDLMCTL_Type

#include <core_feature_base.h>

Union type to access MDLM_CTL CSR register.

Public Members

rv_csr_t dlm_en: bit: 0 DLM enable

rv_csr_t dlm_ecc_en: bit: 1 DLM ECC eanble

rv_csr_t dlm_ecc_excp_en: bit: 2 DLM ECC exception enable

rv_csr_t dlm_rwecc: bit: 3 Control mecc_code write to dlm, simulate error injection

rv_csr_t dlm_ecc_chk_en: bit: 4 DLM check ECC codes enable

rv_csr_t _reserved0: bit: 5..9 Reserved

rv_csr_t dlm_bpa: bit: 10..XLEN-1 DLM base address

struct CSR_MDLMCTL_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MCFGINFO_Type

#include <core_feature_base.h>

Union type to access MCFG_INFO CSR register.

Public Members

rv_csr_t tee: bit: 0 TEE present

rv_csr_t ecc: bit: 1 ECC present

rv_csr_t clic: bit: 2 CLIC present

rv_csr_t plic: bit: 3 PLIC present

rv_csr_t fio: bit: 4 FIO present

rv_csr_t ppi: bit: 5 PPI present

rv_csr_t nice: bit: 6 NICE present

rv_csr_t ilm: bit: 7 ILM present

rv_csr_t dlm: bit: 8 DLM present

rv_csr_t icache: bit: 9 ICache present

rv_csr_t dcache: bit: 10 DCache present

rv_csr_t smp: bit: 11 SMP present

rv_csr_t dsp_n1: bit: 12 DSP N1 present

rv_csr_t dsp_n2: bit: 13 DSP N2 present

rv_csr_t dsp_n3: bit: 14 DSP N3 present

rv_csr_t zc_xlcz: bit: 15 Zc and xlcz extension present

rv_csr_t iregion: bit: 16 IREGION present

rv_csr_t vpu_degree: bit: 17..18 Indicate the VPU degree of parallel

rv_csr_t sec_mode: bit: 19 Smwg extension present

rv_csr_t etrace: bit: 20 Etrace present

rv_csr_t safety_mecha: bit: 21..22 Indicate Core’s safety mechanism

rv_csr_t vnice: bit: 23 VNICE present

rv_csr_t xlcz: bit: 24 XLCZ extension present

rv_csr_t zilsd: bit: 25 Zilsd/Zclsd extension present

rv_csr_t sstc: bit: 26 SSTC extension present

rv_csr_t _reserved1: bit: 27..XLEN-1 Reserved

struct CSR_MCFGINFO_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MICFGINFO_Type

#include <core_feature_base.h>

Union type to access MICFG_INFO CSR register.

Public Members

rv_csr_t set: bit: 0..3 I-Cache sets per way

rv_csr_t way: bit: 4..6 I-Cache way

rv_csr_t lsize: bit: 7..9 I-Cache line size

rv_csr_t ecc: bit: 10 I-Cache ECC support

rv_csr_t _reserved0: bit: 11..15 Reserved

rv_csr_t lm_size: bit: 16..20 ILM size, need to be 2^n size

rv_csr_t lm_xonly: bit: 21 ILM Execute only permission or Reserved

rv_csr_t lm_ecc: bit: 22 ILM ECC support

rv_csr_t _reserved1: bit: 23..XLEN-1 Reserved

struct CSR_MICFGINFO_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MDCFGINFO_Type

#include <core_feature_base.h>

Union type to access MDCFG_INFO CSR register.

Public Members

rv_csr_t set: bit: 0..3 D-Cache sets per way

rv_csr_t way: bit: 4..6 D-Cache way

rv_csr_t lsize: bit: 7..9 D-Cache line size

rv_csr_t ecc: bit: 10 D-Cache ECC support

rv_csr_t _reserved0: bit: 11..15 Reserved

rv_csr_t lm_size: bit: 16..20 DLM size, need to be 2^n size

rv_csr_t lm_ecc: bit: 21 DLM ECC present

rv_csr_t _reserved1: bit: 22..XLEN-1 Reserved

struct CSR_MDCFGINFO_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MTLBCFGINFO_Type

#include <core_feature_base.h>

Union type to access MTLBCFG_INFO CSR register.

Public Members

rv_csr_t set: bit: 0..3 Main TLB entry per way

rv_csr_t way: bit: 4..6 Main TLB ways

rv_csr_t lsize: bit: 7..9 Main TLB line size or Reserved

rv_csr_t ecc: bit: 10 Main TLB supports ECC or not

rv_csr_t napot: bit: 11 TLB supports Svnapot or not

rv_csr_t _reserved1: bit: 12..15 Reserved 0

rv_csr_t i_size: bit: 16..18 ITLB size

rv_csr_t d_size: bit: 19..21 DTLB size

rv_csr_t _reserved2: bit: 22..XLEN-1 Reserved 0

struct CSR_MTLBCFGINFO_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MPPICFGINFO_Type

#include <core_feature_base.h>

Union type to access MPPICFG_INFO CSR register.

Public Members

rv_csr_t _reserved0: bit: 0 Reserved 1

rv_csr_t ppi_size: bit: 1..5 PPI size, need to be 2^n size

rv_csr_t _reserved1: bit: 6..8 Reserved 0

rv_csr_t ppi_en

bit: 9 PPI Enable.

Software can write this bit to control PPI

rv_csr_t ppi_bpa: bit: 10..XLEN-1 PPI base address

struct CSR_MPPICFGINFO_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MFIOCFGINFO_Type

#include <core_feature_base.h>

Union type to access MFIOCFG_INFO CSR register.

Public Members

rv_csr_t _reserved0: bit: 0 Reserved

rv_csr_t fio_size: bit: 1..5 FIO size, need to be 2^n size

rv_csr_t _reserved1: bit: 6..9 Reserved

rv_csr_t fio_bpa: bit: 10..XLEN-1 FIO base address

struct CSR_MFIOCFGINFO_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MECCLOCK_Type

#include <core_feature_base.h>

Union type to access MECC_LOCK CSR register.

Public Members

rv_csr_t ecc_lock: bit: 0 RW permission, ECC Lock configure

rv_csr_t _reserved0: bit: 1..XLEN-1 Reserved

struct CSR_MECCLOCK_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MECCCODE_Type

#include <core_feature_base.h>

Union type to access MECC_CODE CSR register.

Public Members

rv_csr_t code: bit: 0..8 Used to inject ECC check code

rv_csr_t _reserved0: bit: 9..15 Reserved 0

rv_csr_t ramid: bit: 16..20 The ID of RAM that has 2bit ECC error, software can clear these bits

rv_csr_t _reserved1: bit: 21..23 Reserved 0

rv_csr_t sramid: bit: 24..28 The ID of RAM that has 1bit ECC error, software can clear these bits

rv_csr_t _reserved2: bit: 29..XLEN-1 Reserved 0

struct CSR_MECCCODE_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MECC_CTL_Type

#include <core_feature_base.h>

Union type to access MECC_CTL CSR register.

Public Members

rv_csr_t ilm_fch_msk: bit: 0 Write 1 to disable aggregate ILM fetch ECC fatal error to safety_error output

rv_csr_t ilm_acc_msk: bit: 1 Write 1 to disable aggregate ILM load/store access ECC fatal error to safety_error output

rv_csr_t dlm_acc_msk: bit: 2 Write 1 to disable aggregate DLM access ECC fatal error to safety_error output

rv_csr_t ic_fch_msk: bit: 3 Write 1 to disable aggregate ICache fetch ECC fatal error to safety_error output

rv_csr_t dc_acc_msk: bit: 4 Write 1 to disable aggregate DCache access ECC fatal error to safety_error output

rv_csr_t ilm_ext_msk: bit: 5 Write 1 to disable aggregate ILM external access ECC fatal error to safety_error output

rv_csr_t dlm_ext_msk: bit: 6 Write 1 to disable aggregate DLM external access ECC fatal error to safety_error output

rv_csr_t ic_ccm_msk: bit: 7 Write 1 to disable aggregate ICache CCM ECC fatal error to safety_error output

rv_csr_t dc_ccm_msk: bit: 8 Write 1 to disable aggregate DCache CCM ECC fatal error to safety_error output

rv_csr_t dc_cpbk_msk: bit: 9 Write 1 to disable aggregate DCache CPBK ECC fatal error to safety_error output

rv_csr_t _reserved0: bit: 10..XLEN-1 Reserved 0

struct CSR_MECC_CTL_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MECC_STATUS_Type

#include <core_feature_base.h>

Union type to access MECC_STATUS CSR register.

Public Members

rv_csr_t ilm_fch_err: bit: 0 ILM fetch ECC fatal error has occurred

rv_csr_t ilm_acc_err: bit: 1 ILM load/store access ECC fatal error has occurred

rv_csr_t dlm_acc_err: bit: 2 DLM access ECC fatal error has occurred

rv_csr_t ic_fch_err: bit: 3 ICache fetch ECC fatal error has occurred

rv_csr_t dc_acc_err: bit: 4 DCache access ECC fatal error has occurred

rv_csr_t ilm_ext_err: bit: 5 ILM external access ECC fatal error has occurred

rv_csr_t dlm_ext_err: bit: 6 DLM external access ECC fatal error has occurred

rv_csr_t ic_ccm_err: bit: 7 ICache CCM ECC fatal error has occurred

rv_csr_t dc_ccm_err: bit: 8 DCache CCM ECC fatal error has occurred

rv_csr_t dc_cpbk_err: bit: 9 DCache CPBK ECC fatal error has occurred

rv_csr_t _reserved0: bit: 10..XLEN-1 Reserved 0

struct CSR_MECC_STATUS_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MIRGB_INFO_Type

#include <core_feature_base.h>

Union type to access MIRGB_INFO CSR register.

Public Members

rv_csr_t _reserved0: bit: 0 Reserved

rv_csr_t iregion_size: bit: 1..5 Indicates the size of IREGION and it should be power of 2

rv_csr_t _reserved1: bit: 6..9 Reserved

rv_csr_t iregion_base: bit: 10..PA_SIZE IREGION Base Address

struct CSR_MIRGB_INFO_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MSTACK_CTL_Type

#include <core_feature_base.h>

Union type to access MSTACK_CTL CSR register.

Public Members

rv_csr_t ovf_track_en: bit: 0 Stack overflow check or track enable

rv_csr_t udf_en: bit: 1 Stack underflow check enable

rv_csr_t mode: bit: 2 Mode of stack checking

rv_csr_t _reserved0: bit: 3..XLEN-1 Reserved

struct CSR_MSTACK_CTL_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

union CSR_MTLB_CTL_Type

#include <core_feature_base.h>

Union type to access MTLB_CTL CSR register.

Public Members

rv_csr_t tlb_ecc_en: bit: 0 MTLB ECC eanble

rv_csr_t tlb_ecc_excp_en: bit: 1 MTLB double bit ECC exception enable control

rv_csr_t tlb_tram_ecc_inj_en: bit: 2 Controls to inject the ECC Code in CSR mecc_code to MTLB tag rams

rv_csr_t tlb_dram_ecc_inj_en: bit: 3 Controls to inject the ECC Code in CSR mecc_code to MTLB data rams

rv_csr_t _reserved0: bit: 4..5 Reserved

rv_csr_t tlb_ecc_chk_en: bit: 6 Controls to check the ECC when core access to MTLB

rv_csr_t napot_en: bit: 7 NAPOT page enable

rv_csr_t _reserved1: bit: 8..XLEN-1 Reserved

struct CSR_MTLB_CTL_Type::[anonymous] b: Structure used for bit access.

rv_csr_t d: Type used for csr data access.

ECLIC

group Register Define and Type Definitions Of ECLIC

Type definitions and defines for eclic registers.

Defines

CLIC_CLICCFG_NLBIT_Pos 1U: CLIC CLICCFG: NLBIT Position.

CLIC_CLICCFG_NLBIT_Msk (0xFUL << CLIC_CLICCFG_NLBIT_Pos): CLIC CLICCFG: NLBIT Mask.

CLIC_CLICINFO_CTLBIT_Pos 21U: CLIC INTINFO: CLICINTCTLBITS Position.

CLIC_CLICINFO_CTLBIT_Msk (0xFUL << CLIC_CLICINFO_CTLBIT_Pos): CLIC INTINFO: CLICINTCTLBITS Mask.

CLIC_CLICINFO_VER_Pos 13U: CLIC CLICINFO: VERSION Position.

CLIC_CLICINFO_VER_Msk (0xFFUL << CLIC_CLICINFO_VER_Pos): CLIC CLICINFO: VERSION Mask.

CLIC_CLICINFO_NUM_Pos 0U: CLIC CLICINFO: NUM Position.

CLIC_CLICINFO_NUM_Msk (0x1FFFUL << CLIC_CLICINFO_NUM_Pos): CLIC CLICINFO: NUM Mask.

CLIC_INTIP_IP_Pos 0U: CLIC INTIP: IP Position.

CLIC_INTIP_IP_Msk (0x1UL << CLIC_INTIP_IP_Pos): CLIC INTIP: IP Mask.

CLIC_INTIE_IE_Pos 0U: CLIC INTIE: IE Position.

CLIC_INTIE_IE_Msk (0x1UL << CLIC_INTIE_IE_Pos): CLIC INTIE: IE Mask.

CLIC_INTATTR_MODE_Pos 6U: CLIC INTATTA: Mode Position.

CLIC_INTATTR_MODE_Msk (0x3U << CLIC_INTATTR_MODE_Pos): CLIC INTATTA: Mode Mask.

CLIC_INTATTR_TRIG_Pos 1U: CLIC INTATTR: TRIG Position.

CLIC_INTATTR_TRIG_Msk (0x3UL << CLIC_INTATTR_TRIG_Pos): CLIC INTATTR: TRIG Mask.

CLIC_INTATTR_SHV_Pos 0U: CLIC INTATTR: SHV Position.

CLIC_INTATTR_SHV_Msk (0x1UL << CLIC_INTATTR_SHV_Pos): CLIC INTATTR: SHV Mask.

ECLIC_MAX_NLBITS 8U: Max nlbit of the CLICINTCTLBITS.

ECLIC_MODE_MTVEC_Msk 3U: ECLIC Mode mask for MTVT CSR Register.

ECLIC_NON_VECTOR_INTERRUPT 0x0: Non-Vector Interrupt Mode of ECLIC.

ECLIC_VECTOR_INTERRUPT 0x1: Vector Interrupt Mode of ECLIC.

ECLIC_BASE __ECLIC_BASEADDR: ECLIC Base Address.

ECLIC ((CLIC_Type *) ECLIC_BASE): CLIC configuration struct.

Enums

enum ECLIC_TRIGGER_Type

ECLIC Trigger Enum for different Trigger Type.

Values:

enumerator ECLIC_LEVEL_TRIGGER: Level Triggerred, trig[0] = 0.

enumerator ECLIC_POSTIVE_EDGE_TRIGGER: Postive/Rising Edge Triggered, trig[0] = 1, trig[1] = 0.

enumerator ECLIC_NEGTIVE_EDGE_TRIGGER: Negtive/Falling Edge Triggered, trig[0] = 1, trig[1] = 1.

enumerator ECLIC_MAX_TRIGGER: MAX Supported Trigger Mode.

union CLICCFG_Type

#include <core_feature_eclic.h>

Union type to access CLICFG configure register.

Public Members

__IM uint8_t _reserved0

__IOM uint8_t nlbits: bit: 1..4 specified the bit-width of level and priority in the register clicintctl[i]

__IM uint8_t nmbits: bit: 5..6 ties to 1 if supervisor-level interrupt supported, or else it’s reserved

__IM uint8_t _reserved1

struct CLICCFG_Type::[anonymous] b: Structure used for bit access.

uint8_t w: Type used for byte access.

union CLICINFO_Type

#include <core_feature_eclic.h>

Union type to access CLICINFO information register.

Public Members

__IM uint32_t numint: bit: 0..12 number of maximum interrupt inputs supported

__IM uint32_t version: bit: 13..20 20:17 for architecture version,16:13 for implementation version

__IM uint32_t intctlbits: bit: 21..24 specifies how many hardware bits are actually implemented in the clicintctl registers

__IM uint32_t _reserved0: bit: 25..31 Reserved

struct CLICINFO_Type::[anonymous] b: Structure used for bit access.

__IM uint32_t w: Type used for word access.

struct CLIC_CTRL_Type: #include <core_feature_eclic.h>

Access to the machine mode register structure of INTIP, INTIE, INTATTR, INTCTL.

struct CLIC_Type: #include <core_feature_eclic.h>

Access to the structure of ECLIC Memory Map, which is compatible with TEE.

PLIC

group Register Define and Type Definitions Of PLIC

Type definitions and defines for plic registers.

Defines

PLIC_PRIORITY_OFFSET _AC(0x0000,UL): PLIC Priority register offset.

PLIC_PRIORITY_SHIFT_PER_SOURCE 2: PLIC Priority register offset shift per source.

PLIC_PENDING_OFFSET _AC(0x1000,UL): PLIC Pending register offset.

PLIC_PENDING_SHIFT_PER_SOURCE 0: PLIC Pending register offset shift per source.

PLIC_ENABLE_OFFSET _AC(0x2000,UL): PLIC Enable register offset.

PLIC_ENABLE_SHIFT_PER_CONTEXT 7: PLIC Enable register offset shift per context.

PLIC_THRESHOLD_OFFSET _AC(0x200000,UL): PLIC Threshold register offset.

PLIC_CLAIM_OFFSET _AC(0x200004,UL): PLIC Claim register offset.

PLIC_THRESHOLD_SHIFT_PER_CONTEXT 12: PLIC Threshold register offset shift per context.

PLIC_CLAIM_SHIFT_PER_CONTEXT 12: PLIC Claim register offset shift per context.

PLIC_BASE __PLIC_BASEADDR: PLIC Base Address.

PLIC_GetHartID() (__get_hart_index())

PLIC_GetHartID() is used to get plic hartid which might not be the same as cpu hart id, for example, cpu hartid may be 1, but plic hartid may be 0, then plic hartid offset is 1.

If defined __PLIC_HARTID, it will use __PLIC_HARTID as plic hartid, otherwise, it will use __get_hart_index(). The cpu hartid is get by using __get_hart_id function

PLIC_GetHartID_S() (__get_hart_index_s())

PLIC_GetHartMContextID() (PLIC_GetHartID() << 1)

PLIC_GetHartSContextID() ((PLIC_GetHartID_S() << 1) + 1)

PLIC_PRIORITY_REGADDR(source) ((PLIC_BASE) + (PLIC_PRIORITY_OFFSET) + ((source) << PLIC_PRIORITY_SHIFT_PER_SOURCE))

PLIC_PENDING_REGADDR(source) ((PLIC_BASE) + (PLIC_PENDING_OFFSET) + (((source) >> 5) * 4))

PLIC_ENABLE_REGADDR(ctxid, source) ((PLIC_BASE) + (PLIC_ENABLE_OFFSET) + ((ctxid) << PLIC_ENABLE_SHIFT_PER_CONTEXT) + ((source) >> 5) * 4)

PLIC_THRESHOLD_REGADDR(ctxid) ((PLIC_BASE) + (PLIC_THRESHOLD_OFFSET) + ((ctxid) << PLIC_THRESHOLD_SHIFT_PER_CONTEXT))

PLIC_CLAIM_REGADDR(ctxid) ((PLIC_BASE) + (PLIC_CLAIM_OFFSET) + ((ctxid) << PLIC_CLAIM_SHIFT_PER_CONTEXT))

PLIC_COMPLETE_REGADDR(ctxid) (PLIC_CLAIM_REGADDR(ctxid))

SysTimer

group Register Define and Type Definitions Of System Timer

Type definitions and defines for system timer registers.

Defines

SysTimer_MTIMECTL_TIMESTOP_Pos 0U: SysTick Timer MTIMECTL: TIMESTOP bit Position.

SysTimer_MTIMECTL_TIMESTOP_Msk (1UL << SysTimer_MTIMECTL_TIMESTOP_Pos): SysTick Timer MTIMECTL: TIMESTOP Mask.

SysTimer_MTIMECTL_CMPCLREN_Pos 1U: SysTick Timer MTIMECTL: CMPCLREN bit Position.

SysTimer_MTIMECTL_CMPCLREN_Msk (1UL << SysTimer_MTIMECTL_CMPCLREN_Pos): SysTick Timer MTIMECTL: CMPCLREN Mask.

SysTimer_MTIMECTL_CLKSRC_Pos 2U: SysTick Timer MTIMECTL: CLKSRC bit Position.

SysTimer_MTIMECTL_CLKSRC_Msk (1UL << SysTimer_MTIMECTL_CLKSRC_Pos): SysTick Timer MTIMECTL: CLKSRC Mask.

SysTimer_MTIMECTL_HDBG_Pos 4U: SysTick Timer MTIMECTL: HDBG bit Position.

SysTimer_MTIMECTL_HDBG_Msk (1UL << SysTimer_MTIMECTL_HDBG_Pos): SysTick Timer MTIMECTL: HDBG Mask.

SysTimer_MSIP_MSIP_Pos 0U: SysTick Timer MSIP: MSIP bit Position.

SysTimer_MSIP_MSIP_Msk (1UL << SysTimer_MSIP_MSIP_Pos): SysTick Timer MSIP: MSIP Mask.

SysTimer_SSIP_SSIP_Pos 0U: SysTick Timer SSIP: SSIP bit Position.

SysTimer_SSIP_SSIP_Msk (1UL << SysTimer_SSIP_SSIP_Pos): SysTick Timer SSIP: SSIP Mask.

SysTimer_MTIMER_Msk (0xFFFFFFFFFFFFFFFFULL): SysTick Timer MTIMER value Mask.

SysTimer_MTIMERCMP_Msk (0xFFFFFFFFFFFFFFFFULL): SysTick Timer MTIMERCMP value Mask.

SysTimer_MTIMECTL_Msk (0xFFFFFFFFUL): SysTick Timer MTIMECTL/MSTOP value Mask.

SysTimer_MSIP_Msk (0xFFFFFFFFUL): SysTick Timer MSIP value Mask.

SysTimer_MSFTRST_Msk (0xFFFFFFFFUL): SysTick Timer MSFTRST value Mask.

SysTimer_MSFRST_KEY (0x80000A5FUL): SysTick Timer Software Reset Request Key.

SysTimer_CLINT_MSIP_OFS (0x1000UL): Machine Mode Software interrupt register offset of clint mode in SysTick Timer.

SysTimer_CLINT_MTIMECMP_OFS (0x5000UL): MTIMECMP register offset of clint mode in SysTick Timer.

SysTimer_CLINT_MTIME_OFS (0xCFF8UL): MTIME register offset of clint mode in SysTick Timer.

SysTimer_CLINT_SSIP_OFS (0xD000UL): Supervisor Mode Software interrupt register offset of clint mode in SysTick Timer.

SysTimer_BASE __SYSTIMER_BASEADDR: SysTick Base Address.

SysTimer ((SysTimer_Type *) SysTimer_BASE): SysTick configuration struct.

SysTimer_CLINT_MSIP_BASE(hartid) (unsigned long)((SysTimer_BASE) + (SysTimer_CLINT_MSIP_OFS) + ((hartid) << 2))

SysTimer_CLINT_MTIMECMP_BASE(hartid) (unsigned long)((SysTimer_BASE) + (SysTimer_CLINT_MTIMECMP_OFS) + ((hartid) << 3))

SysTimer_CLINT_MTIME_BASE (unsigned long)((SysTimer_BASE) + (SysTimer_CLINT_MTIME_OFS))

SysTimer_CLINT_SSIP_BASE(hartid) (unsigned long)((SysTimer_BASE) + (SysTimer_CLINT_SSIP_OFS) + ((hartid) << 2))

struct SysTimer_Type

#include <core_feature_timer.h>

Structure type to access the System Timer (SysTimer).

Structure definition to access the system timer(SysTimer).

Remark

MSFTRST register is introduced in Nuclei N Core version 1.3(__NUCLEI_N_REV >= 0x0103)
MSTOP register is renamed to MTIMECTL register in Nuclei N Core version 1.4(__NUCLEI_N_REV >= 0x0104)
CMPCLREN and CLKSRC bit in MTIMECTL register is introduced in Nuclei N Core version 1.4(__NUCLEI_N_REV >= 0x0104)