Core CSR Encoding

Click Nuclei Core CSR to learn about Core CSR in Nuclei ISA Spec.

Core CSR Register Definitions

group Core CSR Registers

NMSIS Core CSR Register Definitions.

The following macros are used for CSR Register Defintions.

Defines

CSR_USTATUS 0x0

CSR_FFLAGS 0x1

CSR_FRM 0x2

CSR_FCSR 0x3

CSR_VSTART 0x8

CSR_VXSAT 0x9

CSR_VXRM 0xa

CSR_VCSR 0xf

CSR_SEED 0x15

CSR_JVT 0x17

CSR_CYCLE 0xc00

CSR_TIME 0xc01

CSR_INSTRET 0xc02

CSR_HPMCOUNTER3 0xc03

CSR_HPMCOUNTER4 0xc04

CSR_HPMCOUNTER5 0xc05

CSR_HPMCOUNTER6 0xc06

CSR_HPMCOUNTER7 0xc07

CSR_HPMCOUNTER8 0xc08

CSR_HPMCOUNTER9 0xc09

CSR_HPMCOUNTER10 0xc0a

CSR_HPMCOUNTER11 0xc0b

CSR_HPMCOUNTER12 0xc0c

CSR_HPMCOUNTER13 0xc0d

CSR_HPMCOUNTER14 0xc0e

CSR_HPMCOUNTER15 0xc0f

CSR_HPMCOUNTER16 0xc10

CSR_HPMCOUNTER17 0xc11

CSR_HPMCOUNTER18 0xc12

CSR_HPMCOUNTER19 0xc13

CSR_HPMCOUNTER20 0xc14

CSR_HPMCOUNTER21 0xc15

CSR_HPMCOUNTER22 0xc16

CSR_HPMCOUNTER23 0xc17

CSR_HPMCOUNTER24 0xc18

CSR_HPMCOUNTER25 0xc19

CSR_HPMCOUNTER26 0xc1a

CSR_HPMCOUNTER27 0xc1b

CSR_HPMCOUNTER28 0xc1c

CSR_HPMCOUNTER29 0xc1d

CSR_HPMCOUNTER30 0xc1e

CSR_HPMCOUNTER31 0xc1f

CSR_VL 0xc20

CSR_VTYPE 0xc21

CSR_VLENB 0xc22

CSR_TIMEH 0xc81

CSR_TIMEH 0xc81

CSR_SSTATUS 0x100

CSR_SEDELEG 0x102

CSR_SIDELEG 0x103

CSR_SIE 0x104

CSR_STVEC 0x105

CSR_STVT 0x107

CSR_STVT 0x107

CSR_SCOUNTEREN 0x106

CSR_SENVCFG 0x10a

CSR_SSTATEEN0 0x10c

CSR_SSTATEEN1 0x10d

CSR_SSTATEEN2 0x10e

CSR_SSTATEEN3 0x10f

CSR_SSCRATCH 0x140

CSR_SEPC 0x141

CSR_SCAUSE 0x142

CSR_STVAL 0x143

CSR_SIP 0x144

CSR_STIMECMP 0x14d

CSR_STIMECMPH 0x15d

CSR_STIMECMPH 0x15d

CSR_SATP 0x180

CSR_SCONTEXT 0x5a8

CSR_VSSTATUS 0x200

CSR_VSIE 0x204

CSR_VSTVEC 0x205

CSR_VSSCRATCH 0x240

CSR_VSEPC 0x241

CSR_VSCAUSE 0x242

CSR_VSTVAL 0x243

CSR_VSIP 0x244

CSR_VSTIMECMP 0x24d

CSR_VSATP 0x280

CSR_HSTATUS 0x600

CSR_HEDELEG 0x602

CSR_HIDELEG 0x603

CSR_HIE 0x604

CSR_HTIMEDELTA 0x605

CSR_HCOUNTEREN 0x606

CSR_HGEIE 0x607

CSR_HENVCFG 0x60a

CSR_HSTATEEN0 0x60c

CSR_HSTATEEN1 0x60d

CSR_HSTATEEN2 0x60e

CSR_HSTATEEN3 0x60f

CSR_HTVAL 0x643

CSR_HIP 0x644

CSR_HVIP 0x645

CSR_HTINST 0x64a

CSR_HGATP 0x680

CSR_HCONTEXT 0x6a8

CSR_HGEIP 0xe12

CSR_SCOUNTOVF 0xda0

CSR_UTVT 0x7

CSR_UNXTI 0x45

CSR_UINTSTATUS 0x46

CSR_USCRATCHCSW 0x48

CSR_USCRATCHCSWL 0x49

CSR_SNXTI 0x145

CSR_SINTSTATUS 0x146

CSR_SSCRATCHCSW 0x148

CSR_SSCRATCHCSWL 0x149

CSR_MTVT 0x307

CSR_MTVT 0x307

CSR_MNXTI 0x345

CSR_MNXTI 0x345

CSR_MINTSTATUS 0x346

CSR_MINTSTATUS 0x346

CSR_MSCRATCHCSW 0x348

CSR_MSCRATCHCSW 0x348

CSR_MSCRATCHCSWL 0x349

CSR_MSCRATCHCSWL 0x349

CSR_MSTATUS 0x300

CSR_MISA 0x301

CSR_MEDELEG 0x302

CSR_MIDELEG 0x303

CSR_MIE 0x304

CSR_MTVEC 0x305

CSR_MCOUNTEREN 0x306

CSR_MENVCFG 0x30a

CSR_MENVCFGH 0x31a

CSR_MENVCFGH 0x31a

CSR_MSTATEEN0 0x30c

CSR_MSTATEEN1 0x30d

CSR_MSTATEEN2 0x30e

CSR_MSTATEEN3 0x30f

CSR_MCOUNTINHIBIT 0x320

CSR_MSCRATCH 0x340

CSR_MEPC 0x341

CSR_MCAUSE 0x342

CSR_MTVAL 0x343

CSR_MBADADDR 0x343

CSR_MIP 0x344

CSR_MTINST 0x34a

CSR_MTVAL2 0x34b

CSR_PMPCFG0 0x3a0

CSR_PMPCFG1 0x3a1

CSR_PMPCFG2 0x3a2

CSR_PMPCFG3 0x3a3

CSR_PMPCFG4 0x3a4

CSR_PMPCFG5 0x3a5

CSR_PMPCFG6 0x3a6

CSR_PMPCFG7 0x3a7

CSR_PMPCFG8 0x3a8

CSR_PMPCFG9 0x3a9

CSR_PMPCFG10 0x3aa

CSR_PMPCFG11 0x3ab

CSR_PMPCFG12 0x3ac

CSR_PMPCFG13 0x3ad

CSR_PMPCFG14 0x3ae

CSR_PMPCFG15 0x3af

CSR_PMPADDR0 0x3b0

CSR_PMPADDR1 0x3b1

CSR_PMPADDR2 0x3b2

CSR_PMPADDR3 0x3b3

CSR_PMPADDR4 0x3b4

CSR_PMPADDR5 0x3b5

CSR_PMPADDR6 0x3b6

CSR_PMPADDR7 0x3b7

CSR_PMPADDR8 0x3b8

CSR_PMPADDR9 0x3b9

CSR_PMPADDR10 0x3ba

CSR_PMPADDR11 0x3bb

CSR_PMPADDR12 0x3bc

CSR_PMPADDR13 0x3bd

CSR_PMPADDR14 0x3be

CSR_PMPADDR15 0x3bf

CSR_PMPADDR16 0x3c0

CSR_PMPADDR17 0x3c1

CSR_PMPADDR18 0x3c2

CSR_PMPADDR19 0x3c3

CSR_PMPADDR20 0x3c4

CSR_PMPADDR21 0x3c5

CSR_PMPADDR22 0x3c6

CSR_PMPADDR23 0x3c7

CSR_PMPADDR24 0x3c8

CSR_PMPADDR25 0x3c9

CSR_PMPADDR26 0x3ca

CSR_PMPADDR27 0x3cb

CSR_PMPADDR28 0x3cc

CSR_PMPADDR29 0x3cd

CSR_PMPADDR30 0x3ce

CSR_PMPADDR31 0x3cf

CSR_PMPADDR32 0x3d0

CSR_PMPADDR33 0x3d1

CSR_PMPADDR34 0x3d2

CSR_PMPADDR35 0x3d3

CSR_PMPADDR36 0x3d4

CSR_PMPADDR37 0x3d5

CSR_PMPADDR38 0x3d6

CSR_PMPADDR39 0x3d7

CSR_PMPADDR40 0x3d8

CSR_PMPADDR41 0x3d9

CSR_PMPADDR42 0x3da

CSR_PMPADDR43 0x3db

CSR_PMPADDR44 0x3dc

CSR_PMPADDR45 0x3dd

CSR_PMPADDR46 0x3de

CSR_PMPADDR47 0x3df

CSR_PMPADDR48 0x3e0

CSR_PMPADDR49 0x3e1

CSR_PMPADDR50 0x3e2

CSR_PMPADDR51 0x3e3

CSR_PMPADDR52 0x3e4

CSR_PMPADDR53 0x3e5

CSR_PMPADDR54 0x3e6

CSR_PMPADDR55 0x3e7

CSR_PMPADDR56 0x3e8

CSR_PMPADDR57 0x3e9

CSR_PMPADDR58 0x3ea

CSR_PMPADDR59 0x3eb

CSR_PMPADDR60 0x3ec

CSR_PMPADDR61 0x3ed

CSR_PMPADDR62 0x3ee

CSR_PMPADDR63 0x3ef

CSR_MSECCFG 0x747

CSR_TSELECT 0x7a0

CSR_TDATA1 0x7a1

CSR_TDATA2 0x7a2

CSR_TDATA3 0x7a3

CSR_TINFO 0x7a4

CSR_TCONTROL 0x7a5

CSR_MCONTEXT 0x7a8

CSR_MSCONTEXT 0x7aa

CSR_DCSR 0x7b0

CSR_DPC 0x7b1

CSR_DSCRATCH0 0x7b2

CSR_DSCRATCH1 0x7b3

CSR_MCYCLE 0xb00

CSR_MINSTRET 0xb02

CSR_MHPMCOUNTER3 0xb03

CSR_MHPMCOUNTER4 0xb04

CSR_MHPMCOUNTER5 0xb05

CSR_MHPMCOUNTER6 0xb06

CSR_MHPMCOUNTER7 0xb07

CSR_MHPMCOUNTER8 0xb08

CSR_MHPMCOUNTER9 0xb09

CSR_MHPMCOUNTER10 0xb0a

CSR_MHPMCOUNTER11 0xb0b

CSR_MHPMCOUNTER12 0xb0c

CSR_MHPMCOUNTER13 0xb0d

CSR_MHPMCOUNTER14 0xb0e

CSR_MHPMCOUNTER15 0xb0f

CSR_MHPMCOUNTER16 0xb10

CSR_MHPMCOUNTER17 0xb11

CSR_MHPMCOUNTER18 0xb12

CSR_MHPMCOUNTER19 0xb13

CSR_MHPMCOUNTER20 0xb14

CSR_MHPMCOUNTER21 0xb15

CSR_MHPMCOUNTER22 0xb16

CSR_MHPMCOUNTER23 0xb17

CSR_MHPMCOUNTER24 0xb18

CSR_MHPMCOUNTER25 0xb19

CSR_MHPMCOUNTER26 0xb1a

CSR_MHPMCOUNTER27 0xb1b

CSR_MHPMCOUNTER28 0xb1c

CSR_MHPMCOUNTER29 0xb1d

CSR_MHPMCOUNTER30 0xb1e

CSR_MHPMCOUNTER31 0xb1f

CSR_MHPMEVENT3 0x323

CSR_MHPMEVENT4 0x324

CSR_MHPMEVENT5 0x325

CSR_MHPMEVENT6 0x326

CSR_MHPMEVENT7 0x327

CSR_MHPMEVENT8 0x328

CSR_MHPMEVENT9 0x329

CSR_MHPMEVENT10 0x32a

CSR_MHPMEVENT11 0x32b

CSR_MHPMEVENT12 0x32c

CSR_MHPMEVENT13 0x32d

CSR_MHPMEVENT14 0x32e

CSR_MHPMEVENT15 0x32f

CSR_MHPMEVENT16 0x330

CSR_MHPMEVENT17 0x331

CSR_MHPMEVENT18 0x332

CSR_MHPMEVENT19 0x333

CSR_MHPMEVENT20 0x334

CSR_MHPMEVENT21 0x335

CSR_MHPMEVENT22 0x336

CSR_MHPMEVENT23 0x337

CSR_MHPMEVENT24 0x338

CSR_MHPMEVENT25 0x339

CSR_MHPMEVENT26 0x33a

CSR_MHPMEVENT27 0x33b

CSR_MHPMEVENT28 0x33c

CSR_MHPMEVENT29 0x33d

CSR_MHPMEVENT30 0x33e

CSR_MHPMEVENT31 0x33f

CSR_MVENDORID 0xf11

CSR_MARCHID 0xf12

CSR_MIMPID 0xf13

CSR_MHARTID 0xf14

CSR_MCONFIGPTR 0xf15

CSR_VSTIMECMPH 0x25d

CSR_HTIMEDELTAH 0x615

CSR_HENVCFGH 0x61a

CSR_HSTATEEN0H 0x61c

CSR_HSTATEEN1H 0x61d

CSR_HSTATEEN2H 0x61e

CSR_HSTATEEN3H 0x61f

CSR_CYCLEH 0xc80

CSR_INSTRETH 0xc82

CSR_HPMCOUNTER3H 0xc83

CSR_HPMCOUNTER4H 0xc84

CSR_HPMCOUNTER5H 0xc85

CSR_HPMCOUNTER6H 0xc86

CSR_HPMCOUNTER7H 0xc87

CSR_HPMCOUNTER8H 0xc88

CSR_HPMCOUNTER9H 0xc89

CSR_HPMCOUNTER10H 0xc8a

CSR_HPMCOUNTER11H 0xc8b

CSR_HPMCOUNTER12H 0xc8c

CSR_HPMCOUNTER13H 0xc8d

CSR_HPMCOUNTER14H 0xc8e

CSR_HPMCOUNTER15H 0xc8f

CSR_HPMCOUNTER16H 0xc90

CSR_HPMCOUNTER17H 0xc91

CSR_HPMCOUNTER18H 0xc92

CSR_HPMCOUNTER19H 0xc93

CSR_HPMCOUNTER20H 0xc94

CSR_HPMCOUNTER21H 0xc95

CSR_HPMCOUNTER22H 0xc96

CSR_HPMCOUNTER23H 0xc97

CSR_HPMCOUNTER24H 0xc98

CSR_HPMCOUNTER25H 0xc99

CSR_HPMCOUNTER26H 0xc9a

CSR_HPMCOUNTER27H 0xc9b

CSR_HPMCOUNTER28H 0xc9c

CSR_HPMCOUNTER29H 0xc9d

CSR_HPMCOUNTER30H 0xc9e

CSR_HPMCOUNTER31H 0xc9f

CSR_MSTATUSH 0x310

CSR_MSTATEEN0H 0x31c

CSR_MSTATEEN1H 0x31d

CSR_MSTATEEN2H 0x31e

CSR_MSTATEEN3H 0x31f

CSR_MHPMEVENT3H 0x723

CSR_MHPMEVENT4H 0x724

CSR_MHPMEVENT5H 0x725

CSR_MHPMEVENT6H 0x726

CSR_MHPMEVENT7H 0x727

CSR_MHPMEVENT8H 0x728

CSR_MHPMEVENT9H 0x729

CSR_MHPMEVENT10H 0x72a

CSR_MHPMEVENT11H 0x72b

CSR_MHPMEVENT12H 0x72c

CSR_MHPMEVENT13H 0x72d

CSR_MHPMEVENT14H 0x72e

CSR_MHPMEVENT15H 0x72f

CSR_MHPMEVENT16H 0x730

CSR_MHPMEVENT17H 0x731

CSR_MHPMEVENT18H 0x732

CSR_MHPMEVENT19H 0x733

CSR_MHPMEVENT20H 0x734

CSR_MHPMEVENT21H 0x735

CSR_MHPMEVENT22H 0x736

CSR_MHPMEVENT23H 0x737

CSR_MHPMEVENT24H 0x738

CSR_MHPMEVENT25H 0x739

CSR_MHPMEVENT26H 0x73a

CSR_MHPMEVENT27H 0x73b

CSR_MHPMEVENT28H 0x73c

CSR_MHPMEVENT29H 0x73d

CSR_MHPMEVENT30H 0x73e

CSR_MHPMEVENT31H 0x73f

CSR_MSECCFGH 0x757

CSR_MCYCLEH 0xb80

CSR_MINSTRETH 0xb82

CSR_MHPMCOUNTER3H 0xb83

CSR_MHPMCOUNTER4H 0xb84

CSR_MHPMCOUNTER5H 0xb85

CSR_MHPMCOUNTER6H 0xb86

CSR_MHPMCOUNTER7H 0xb87

CSR_MHPMCOUNTER8H 0xb88

CSR_MHPMCOUNTER9H 0xb89

CSR_MHPMCOUNTER10H 0xb8a

CSR_MHPMCOUNTER11H 0xb8b

CSR_MHPMCOUNTER12H 0xb8c

CSR_MHPMCOUNTER13H 0xb8d

CSR_MHPMCOUNTER14H 0xb8e

CSR_MHPMCOUNTER15H 0xb8f

CSR_MHPMCOUNTER16H 0xb90

CSR_MHPMCOUNTER17H 0xb91

CSR_MHPMCOUNTER18H 0xb92

CSR_MHPMCOUNTER19H 0xb93

CSR_MHPMCOUNTER20H 0xb94

CSR_MHPMCOUNTER21H 0xb95

CSR_MHPMCOUNTER22H 0xb96

CSR_MHPMCOUNTER23H 0xb97

CSR_MHPMCOUNTER24H 0xb98

CSR_MHPMCOUNTER25H 0xb99

CSR_MHPMCOUNTER26H 0xb9a

CSR_MHPMCOUNTER27H 0xb9b

CSR_MHPMCOUNTER28H 0xb9c

CSR_MHPMCOUNTER29H 0xb9d

CSR_MHPMCOUNTER30H 0xb9e

CSR_MHPMCOUNTER31H 0xb9f

CSR_SPMPCFG0 0x1A0

CSR_SPMPCFG1 0x1A1

CSR_SPMPCFG2 0x1A2

CSR_SPMPCFG3 0x1A3

CSR_SPMPADDR0 0x1B0

CSR_SPMPADDR1 0x1B1

CSR_SPMPADDR2 0x1B2

CSR_SPMPADDR3 0x1B3

CSR_SPMPADDR4 0x1B4

CSR_SPMPADDR5 0x1B5

CSR_SPMPADDR6 0x1B6

CSR_SPMPADDR7 0x1B7

CSR_SPMPADDR8 0x1B8

CSR_SPMPADDR9 0x1B9

CSR_SPMPADDR10 0x1BA

CSR_SPMPADDR11 0x1BB

CSR_SPMPADDR12 0x1BC

CSR_SPMPADDR13 0x1BD

CSR_SPMPADDR14 0x1BE

CSR_SPMPADDR15 0x1BF

CSR_SMPUCFG0 0x1A0

CSR_SMPUCFG1 0x1A1

CSR_SMPUCFG2 0x1A2

CSR_SMPUCFG3 0x1A3

CSR_SMPUADDR0 0x1B0

CSR_SMPUADDR1 0x1B1

CSR_SMPUADDR2 0x1B2

CSR_SMPUADDR3 0x1B3

CSR_SMPUADDR4 0x1B4

CSR_SMPUADDR5 0x1B5

CSR_SMPUADDR6 0x1B6

CSR_SMPUADDR7 0x1B7

CSR_SMPUADDR8 0x1B8

CSR_SMPUADDR9 0x1B9

CSR_SMPUADDR10 0x1BA

CSR_SMPUADDR11 0x1BB

CSR_SMPUADDR12 0x1BC

CSR_SMPUADDR13 0x1BD

CSR_SMPUADDR14 0x1BE

CSR_SMPUADDR15 0x1BF

CSR_SMPUSWITCH0 0x170

CSR_SMPUSWITCH1 0x171

CSR_MCLICBASE 0x350

CSR_UCODE 0x801

CSR_MILM_CTL 0x7C0

CSR_MDLM_CTL 0x7C1

CSR_MECC_CODE 0x7C2

CSR_MNVEC 0x7C3

CSR_MSUBM 0x7C4

CSR_MDCAUSE 0x7C9

CSR_MCACHE_CTL 0x7CA

CSR_MMISC_CTL 0x7D0

CSR_MSAVESTATUS 0x7D6

CSR_MSAVEEPC1 0x7D7

CSR_MSAVECAUSE1 0x7D8

CSR_MSAVEEPC2 0x7D9

CSR_MSAVECAUSE2 0x7DA

CSR_MSAVEDCAUSE1 0x7DB

CSR_MSAVEDCAUSE2 0x7DC

CSR_MTLB_CTL 0x7DD

CSR_MECC_LOCK 0x7DE

CSR_MFP16MODE 0x7E2

CSR_MMISC_CTL1 0x7E2

CSR_LSTEPFORC 0x7E9

CSR_PUSHMSUBM 0x7EB

CSR_MTVT2 0x7EC

CSR_JALMNXTI 0x7ED

CSR_PUSHMCAUSE 0x7EE

CSR_PUSHMEPC 0x7EF

CSR_MPPICFG_INFO 0x7F0

CSR_MFIOCFG_INFO 0x7F1

CSR_MDEVB 0x7F3

CSR_MDEVM 0x7F4

CSR_MNOCB 0x7F5

CSR_MNOCM 0x7F6

CSR_MMACRO_DEV_EN 0xBC8

CSR_MMACRO_NOC_EN 0xBC9

CSR_MMACRO_CA_EN 0xBCA

CSR_MATTRI0_BASE 0x7F3

CSR_MATTRI0_MASK 0x7F4

CSR_MATTRI1_BASE 0x7F5

CSR_MATTRI1_MASK 0x7F6

CSR_MATTRI2_BASE 0x7F9

CSR_MATTRI2_MASK 0x7FA

CSR_MATTRI3_BASE 0x7FB

CSR_MATTRI3_MASK 0x7FC

CSR_MATTRI4_BASE 0x7FD

CSR_MATTRI4_MASK 0x7FE

CSR_MATTRI5_BASE 0xBE0

CSR_MATTRI5_MASK 0xBE1

CSR_MATTRI6_BASE 0xBE2

CSR_MATTRI6_MASK 0xBE3

CSR_MATTRI7_BASE 0xBE4

CSR_MATTRI7_MASK 0xBE5

CSR_SATTRI0_BASE 0x5F0

CSR_SATTRI0_MASK 0x5F1

CSR_SATTRI1_BASE 0x5F2

CSR_SATTRI1_MASK 0x5F3

CSR_SATTRI2_BASE 0x5F4

CSR_SATTRI2_MASK 0x5F5

CSR_SATTRI3_BASE 0x5F6

CSR_SATTRI3_MASK 0x5F7

CSR_SATTRI4_BASE 0x5F8

CSR_SATTRI4_MASK 0x5F9

CSR_SATTRI5_BASE 0x5FA

CSR_SATTRI5_MASK 0x5FB

CSR_SATTRI6_BASE 0x5FC

CSR_SATTRI6_MASK 0x5FD

CSR_SATTRI7_BASE 0x5FE

CSR_SATTRI7_MASK 0x5FF

CSR_MSMPCFG_INFO 0x7F7

CSR_MIRGB_INFO 0x7F7

CSR_SLEEPVALUE 0x811

CSR_TXEVT 0x812

CSR_WFE 0x810

CSR_JALSNXTI 0x947

CSR_STVT2 0x948

CSR_PUSHSCAUSE 0x949

CSR_PUSHSEPC 0x94A

CSR_SDCAUSE 0x9C0

CSR_MICFG_INFO 0xFC0

CSR_MDCFG_INFO 0xFC1

CSR_MCFG_INFO 0xFC2

CSR_MTLBCFG_INFO 0xFC3

CSR_MECC_CTL 0xBC0

CSR_MECC_STATUS 0xBC4

CSR_SAFETY_CRC_CTL 0x813

CSR_SAFETY_STL_STATUS 0x814

CSR_MSTACK_CTRL 0x7C6

CSR_MSTACK_CTL 0x7C6

CSR_MSTACK_BOUND 0x7C7

CSR_MSTACK_BASE 0x7C8

CSR_CCM_MBEGINADDR 0x7CB

CSR_CCM_MCOMMAND 0x7CC

CSR_CCM_MDATA 0x7CD

CSR_CCM_SUEN 0x7CE

CSR_CCM_SBEGINADDR 0x5CB

CSR_CCM_SCOMMAND 0x5CC

CSR_CCM_SDATA 0x5CD

CSR_CCM_UBEGINADDR 0x4CB

CSR_CCM_UCOMMAND 0x4CC

CSR_CCM_UDATA 0x4CD

CSR_CCM_FPIPE 0x4CF

CSR_SHARTID 0xDC0

CSR_MLWID 0x390

CSR_MWIDDELEG 0x738

CSR_SLWID 0x190

Other Core Related Macros

group Core CSR Encodings

NMSIS Core CSR Encodings.

The following macros are used for CSR encodings

Defines

MSTATUS_UIE 0x00000001

MSTATUS_SIE 0x00000002

MSTATUS_HIE 0x00000004

MSTATUS_MIE 0x00000008

MSTATUS_UPIE 0x00000010

MSTATUS_SPIE 0x00000020

MSTATUS_UBE 0x00000040

MSTATUS_MPIE 0x00000080

MSTATUS_SPP 0x00000100

MSTATUS_VS 0x00000600

MSTATUS_MPP 0x00001800

MSTATUS_FS 0x00006000

MSTATUS_XS 0x00018000

MSTATUS_MPRV 0x00020000

MSTATUS_SUM 0x00040000

MSTATUS_MXR 0x00080000

MSTATUS_TVM 0x00100000

MSTATUS_TW 0x00200000

MSTATUS_TSR 0x00400000

MSTATUS32_SD 0x80000000

MSTATUS_UXL 0x0000000300000000

MSTATUS_SXL 0x0000000C00000000

MSTATUS_SBE 0x0000001000000000

MSTATUS_MBE 0x0000002000000000

MSTATUS_GVA 0x0000004000000000

MSTATUS_MPV 0x0000008000000000

MSTATUS64_SD 0x8000000000000000

MSTATUS_FS_INITIAL 0x00002000

MSTATUS_FS_CLEAN 0x00004000

MSTATUS_FS_DIRTY 0x00006000

MSTATUS_VS_INITIAL 0x00000200

MSTATUS_VS_CLEAN 0x00000400

MSTATUS_VS_DIRTY 0x00000600

MSTATUSH_SBE 0x00000010

MSTATUSH_MBE 0x00000020

MSTATUSH_GVA 0x00000040

MSTATUSH_MPV 0x00000080

SSTATUS_UIE 0x00000001

SSTATUS_SIE 0x00000002

SSTATUS_UPIE 0x00000010

SSTATUS_SPIE 0x00000020

SSTATUS_UBE 0x00000040

SSTATUS_SPP 0x00000100

SSTATUS_VS 0x00000600

SSTATUS_FS 0x00006000

SSTATUS_XS 0x00018000

SSTATUS_SUM 0x00040000

SSTATUS_MXR 0x00080000

SSTATUS32_SD 0x80000000

SSTATUS_UXL 0x0000000300000000

SSTATUS64_SD 0x8000000000000000

USTATUS_UIE 0x00000001

USTATUS_UPIE 0x00000010

DCSR_XDEBUGVER (3U<<30)

DCSR_NDRESET (1<<29)

DCSR_FULLRESET (1<<28)

DCSR_EBREAKM (1<<15)

DCSR_EBREAKH (1<<14)

DCSR_EBREAKS (1<<13)

DCSR_EBREAKU (1<<12)

DCSR_STOPCYCLE (1<<10)

DCSR_STOPTIME (1<<9)

DCSR_CAUSE (7<<6)

DCSR_DEBUGINT (1<<5)

DCSR_HALT (1<<3)

DCSR_STEP (1<<2)

DCSR_PRV (3<<0)

DCSR_CAUSE_NONE 0

DCSR_CAUSE_SWBP 1

DCSR_CAUSE_HWBP 2

DCSR_CAUSE_DEBUGINT 3

DCSR_CAUSE_STEP 4

DCSR_CAUSE_HALT 5

MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))

MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))

MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))

MCONTROL_SELECT (1<<19)

MCONTROL_TIMING (1<<18)

MCONTROL_ACTION (0x3f<<12)

MCONTROL_CHAIN (1<<11)

MCONTROL_MATCH (0xf<<7)

MCONTROL_M (1<<6)

MCONTROL_H (1<<5)

MCONTROL_S (1<<4)

MCONTROL_U (1<<3)

MCONTROL_EXECUTE (1<<2)

MCONTROL_STORE (1<<1)

MCONTROL_LOAD (1<<0)

MCONTROL_TYPE_NONE 0

MCONTROL_TYPE_MATCH 2

MCONTROL_ACTION_DEBUG_EXCEPTION 0

MCONTROL_ACTION_DEBUG_MODE 1

MCONTROL_ACTION_TRACE_START 2

MCONTROL_ACTION_TRACE_STOP 3

MCONTROL_ACTION_TRACE_EMIT 4

MCONTROL_MATCH_EQUAL 0

MCONTROL_MATCH_NAPOT 1

MCONTROL_MATCH_GE 2

MCONTROL_MATCH_LT 3

MCONTROL_MATCH_MASK_LOW 4

MCONTROL_MATCH_MASK_HIGH 5

MIP_SSIP (1 << IRQ_S_SOFT)

MIP_HSIP (1 << IRQ_H_SOFT)

MIP_MSIP (1 << IRQ_M_SOFT)

MIP_STIP (1 << IRQ_S_TIMER)

MIP_HTIP (1 << IRQ_H_TIMER)

MIP_MTIP (1 << IRQ_M_TIMER)

MIP_SEIP (1 << IRQ_S_EXT)

MIP_HEIP (1 << IRQ_H_EXT)

MIP_MEIP (1 << IRQ_M_EXT)

MIE_SSIE MIP_SSIP 

MIE_HSIE MIP_HSIP 

MIE_MSIE MIP_MSIP 

MIE_STIE MIP_STIP 

MIE_HTIE MIP_HTIP 

MIE_MTIE MIP_MTIP 

MIE_SEIE MIP_SEIP 

MIE_HEIE MIP_HEIP 

MIE_MEIE MIP_MEIP 

SIP_SSIP MIP_SSIP 

SIP_SSIP MIP_SSIP

SIP_STIP MIP_STIP 

SIP_STIP MIP_STIP

SIP_SEIP MIP_SEIP 

SIE_SSIE MIP_SSIP 

SIE_STIE MIP_STIP 

SIE_SEIE MIP_SEIP 

MCAUSE_INTR (1ULL << (__riscv_xlen - 1))

MCAUSE_CAUSE 0x00000FFFUL

SCAUSE_INTR MCAUSE_INTR 

SCAUSE_CAUSE 0x000003FFUL

MENVCFG_CBIE_EN (0x11 << 4)

MENVCFG_CBIE_FLUSH (0x01 << 4)

MENVCFG_CBIE_INVAL (0x11 << 4)

SENVCFG_CBIE_EN (0x11 << 4)

SENVCFG_CBIE_FLUSH (0x01 << 4)

SENVCFG_CBIE_INVAL (0x11 << 4)

MENVCFG_FIOM 0x00000001

MENVCFG_LPE 0x00000004

MENVCFG_SSE 0x00000008

MENVCFG_CBIE 0x00000030

MENVCFG_CBCFE 0x00000040

MENVCFG_CBZE 0x00000080

MENVCFG_PMM 0x0000000300000000

MENVCFG_DTE 0x0800000000000000

MENVCFG_ADUE 0x2000000000000000

MENVCFG_PBMTE 0x4000000000000000

MENVCFG_STCE 0x8000000000000000

MENVCFGH_DTE 0x08000000

MENVCFGH_ADUE 0x20000000

MENVCFGH_PBMTE 0x40000000

MENVCFGH_STCE 0x80000000

SENVCFG_FIOM 0x00000001

SENVCFG_LPE 0x00000004

SENVCFG_SSE 0x00000008

SENVCFG_CBIE 0x00000030

SENVCFG_CBCFE 0x00000040

SENVCFG_CBZE 0x00000080

SENVCFG_PMM 0x0000000300000000

UCODE_OV (0x1)

CSR_MCACHE_CTL_IE 0x00000001

CSR_MCACHE_CTL_DE 0x00010000

WFE_WFE (0x1)

TXEVT_TXEVT (0x1)

SLEEPVALUE_SLEEPVALUE (0x1)

MCOUNTEREN_CY_SHIFT 0

MCOUNTEREN_TIME_SHIFT 1

MCOUNTEREN_IR_SHIFT 2

MCOUNTEREN_CY (1U << MCOUNTEREN_CY_SHIFT)

MCOUNTEREN_TIME (1U << MCOUNTEREN_TIME_SHIFT)

MCOUNTEREN_IR (1U << MCOUNTEREN_IR_SHIFT)

MCOUNTINHIBIT_CY MCOUNTEREN_CY 

MCOUNTINHIBIT_IR MCOUNTEREN_IR 

MILM_CTL_ILM_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10)

MILM_CTL_ILM_ECC_CHK_EN (1<<4)

MILM_CTL_ILM_RWECC (1<<3)

MILM_CTL_ILM_ECC_INJ_EN (1<<3)

MILM_CTL_ILM_ECC_EXCP_EN (1<<2)

MILM_CTL_ILM_ECC_EN (1<<1)

MILM_CTL_ILM_EN (1<<0)

MDLM_CTL_DLM_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10)

MDLM_CTL_DLM_ECC_CHK_EN (1<<4)

MDLM_CTL_DLM_RWECC (1<<3)

MDLM_CTL_DLM_ECC_INJ_EN (1<<3)

MDLM_CTL_DLM_ECC_EXCP_EN (1<<2)

MDLM_CTL_DLM_ECC_EN (1<<1)

MDLM_CTL_DLM_EN (1<<0)

MSUBM_PTYP (0x3<<8)

MSUBM_TYP (0x3<<6)

MDCAUSE_MDCAUSE (0x7)

MMISC_CTL_LDSPEC_ENABLE (1<<12)

MMISC_CTL_SIJUMP_ENABLE (1<<11)

MMISC_CTL_IMRETURN_ENABLE (1<<10)

MMISC_CTL_NMI_CAUSE_FFF (1<<9)

MMISC_CTL_CODE_BUS_ERR (1<<8)

MMISC_CTL_MISALIGN (1<<6)

MMISC_CTL_ZC (1<<7)

MMISC_CTL_BPU (1<<3)

MCACHE_CTL_IC_EN (1<<0)

MCACHE_CTL_IC_SCPD_MOD (1<<1)

MCACHE_CTL_IC_ECC_EN (1<<2)

MCACHE_CTL_IC_ECC_EXCP_EN (1<<3)

MCACHE_CTL_IC_TRAM_ECC_INJ_EN (1<<4)

MCACHE_CTL_IC_RWTECC (1<<4)

MCACHE_CTL_IC_RWDECC (1<<5)

MCACHE_CTL_IC_DRAM_ECC_INJ_EN (1<<5)

MCACHE_CTL_IC_PF_EN (1<<6)

MCACHE_CTL_IC_CANCEL_EN (1<<7)

MCACHE_CTL_IC_ECC_CHK_EN (1<<8)

MCACHE_CTL_DC_EN (1<<16)

MCACHE_CTL_DC_ECC_EN (1<<17)

MCACHE_CTL_DC_ECC_EXCP_EN (1<<18)

MCACHE_CTL_DC_TRAM_ECC_INJ_EN (1<<19)

MCACHE_CTL_DC_RWTECC (1<<19)

MCACHE_CTL_DC_RWDECC (1<<20)

MCACHE_CTL_DC_DRAM_ECC_INJ_EN (1<<20)

MCACHE_CTL_DC_ECC_CHK_EN (1<<21)

MTVT2_MTVT2EN (1<<0)

MTVT2_COMMON_CODE_ENTRY (((1ULL<<((__riscv_xlen)-2))-1)<<2)

MCFG_INFO_TEE (1<<0)

MCFG_INFO_ECC (1<<1)

MCFG_INFO_CLIC (1<<2)

MCFG_INFO_PLIC (1<<3)

MCFG_INFO_FIO (1<<4)

MCFG_INFO_PPI (1<<5)

MCFG_INFO_NICE (1<<6)

MCFG_INFO_ILM (1<<7)

MCFG_INFO_DLM (1<<8)

MCFG_INFO_ICACHE (1<<9)

MCFG_INFO_DCACHE (1<<10)

MCFG_INFO_SMP (1<<11)

MCFG_INFO_DSP_N1 (1<<12)

MCFG_INFO_DSP_N2 (1<<13)

MCFG_INFO_DSP_N3 (1<<14)

MCFG_INFO_IREGION_EXIST (1<<16)

MCFG_INFO_VP (0x3<<17)

MICFG_IC_SET (0xF<<0)

MICFG_IC_WAY (0x7<<4)

MICFG_IC_LSIZE (0x7<<7)

MICFG_IC_ECC (0x1<<10)

MICFG_ILM_SIZE (0x1F<<16)

MICFG_ILM_XONLY (0x1<<21)

MICFG_ILM_ECC (0x1<<22)

MDCFG_DC_SET (0xF<<0)

MDCFG_DC_WAY (0x7<<4)

MDCFG_DC_LSIZE (0x7<<7)

MDCFG_DC_ECC (0x1<<10)

MDCFG_DLM_SIZE (0x1F<<16)

MDCFG_DLM_ECC (0x1<<21)

MIRGB_INFO_IRG_BASE_ADDR_BOFS (10)

MIRGB_INFO_IREGION_SIZE_BOFS (1)

MPPICFG_INFO_PPI_SIZE (0x1F<<1)

MPPICFG_INFO_PPI_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10)

MFIOCFG_INFO_FIO_SIZE (0x1F<<1)

MFIOCFG_INFO_FIO_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10)

MECC_LOCK_ECC_LOCK (0x1)

MECC_CODE_CODE (0x1FF)

MECC_CODE_RAMID (0x1F<<16)

MECC_CODE_SRAMID (0x1F<<24)

CCM_SUEN_SUEN (0x1<<0)

CCM_DATA_DATA (0x7<<0)

CCM_COMMAND_COMMAND (0x1F<<0)

IREGION_IINFO_OFS (0x0)

IREGION_DEBUG_OFS (0x10000)

IREGION_ECLIC_OFS (0x20000)

IREGION_TIMER_OFS (0x30000)

IREGION_SMP_OFS (0x40000)

IREGION_IDU_OFS (0x50000)

IREGION_PL2_OFS (0x60000)

IREGION_DPREFETCH_OFS (0x70000)

IREGION_PLIC_OFS (0x4000000)

MSTACK_CTRL_MODE (0x1<<2)

MSTACK_CTRL_UDF_EN (0x1<<1)

MSTACK_CTRL_OVF_TRACK_EN (0x1)

PRV_U 0

PRV_S 1

PRV_H 2

PRV_M 3

VM_MBARE 0

VM_MBB 1

VM_MBBID 2

VM_SV32 8

VM_SV39 9

VM_SV48 10

SATP32_MODE 0x80000000

SATP32_ASID 0x7FC00000

SATP32_PPN 0x003FFFFF

SATP64_MODE 0xF000000000000000

SATP64_ASID 0x0FFFF00000000000

SATP64_PPN 0x00000FFFFFFFFFFF

SATP_MODE_OFF 0

SATP_MODE_SV32 1

SATP_MODE_SV39 8

SATP_MODE_SV48 9

SATP_MODE_SV57 10

SATP_MODE_SV64 11

IRQ_S_SOFT 1

IRQ_H_SOFT 2

IRQ_M_SOFT 3

IRQ_S_TIMER 5

IRQ_H_TIMER 6

IRQ_M_TIMER 7

IRQ_S_EXT 9

IRQ_H_EXT 10

IRQ_M_EXT 11

IRQ_COP 12

IRQ_HOST 13

FRM_RNDMODE_RNE 0x0: FPU Round to Nearest, ties to Even.

FRM_RNDMODE_RTZ 0x1: FPU Round Towards Zero.

FRM_RNDMODE_RDN 0x2: FPU Round Down (towards -inf)

FRM_RNDMODE_RUP 0x3: FPU Round Up (towards +inf)

FRM_RNDMODE_RMM 0x4: FPU Round to nearest, ties to Max Magnitude.

FRM_RNDMODE_DYN 0x7

In instruction’s rm, selects dynamic rounding mode.

In Rounding Mode register, Invalid

FFLAGS_AE_NX (1<<0): FPU Inexact.

FFLAGS_AE_UF (1<<1): FPU Underflow.

FFLAGS_AE_OF (1<<2): FPU Overflow.

FFLAGS_AE_DZ (1<<3): FPU Divide by Zero.

FFLAGS_AE_NV (1<<4): FPU Invalid Operation.

FREG(idx) f##idx

Floating Point Register f0-f31, eg.

PMP_R 0x01

PMP_W 0x02

PMP_X 0x04

PMP_A 0x18

PMP_A_TOR 0x08

PMP_A_NA4 0x10

PMP_A_NAPOT 0x18

PMP_L 0x80

PMP_SHIFT 2

PMP_COUNT 16

SPMP_R PMP_R 

SPMP_W PMP_W 

SPMP_X PMP_X 

SPMP_A PMP_A 

SPMP_A_TOR PMP_A_TOR 

SPMP_A_NA4 PMP_A_NA4 

SPMP_A_NAPOT PMP_A_NAPOT 

SPMP_U 0x40

SPMP_L PMP_L 

SPMP_SHIFT PMP_SHIFT 

SPMP_COUNT 16

SMPU_R SPMP_R 

SMPU_W SPMP_W 

SMPU_X SPMP_X 

SMPU_A SPMP_A 

SMPU_A_TOR SPMP_A_TOR 

SMPU_A_NA4 SPMP_A_NA4 

SMPU_A_NAPOT SPMP_A_NAPOT 

SMPU_S 0x80

SMPU_SHIFT PMP_SHIFT 

PTE_V 0x001

PTE_R 0x002

PTE_W 0x004

PTE_X 0x008

PTE_U 0x010

PTE_G 0x020

PTE_A 0x040

PTE_D 0x080

PTE_SOFT 0x300

PTE_PPN_SHIFT 10

PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)

CAUSE_MISALIGNED_FETCH 0x0: End of Doxygen Group NMSIS_Core_CSR_Registers.

CAUSE_FAULT_FETCH 0x1

CAUSE_ILLEGAL_INSTRUCTION 0x2

CAUSE_BREAKPOINT 0x3

CAUSE_MISALIGNED_LOAD 0x4

CAUSE_FAULT_LOAD 0x5

CAUSE_MISALIGNED_STORE 0x6

CAUSE_FAULT_STORE 0x7

CAUSE_USER_ECALL 0x8

CAUSE_SUPERVISOR_ECALL 0x9

CAUSE_HYPERVISOR_ECALL 0xa

CAUSE_MACHINE_ECALL 0xb

CAUSE_FETCH_PAGE_FAULT 0xc

CAUSE_LOAD_PAGE_FAULT 0xd

CAUSE_STORE_PAGE_FAULT 0xf

MISALIGNED_FETCH (1 << CAUSE_MISALIGNED_FETCH)

FAULT_FETCH (1 << CAUSE_FAULT_FETCH)

ILLEGAL_INSTRUCTION (1 << CAUSE_ILLEGAL_INSTRUCTION)

BREAKPOINT (1 << CAUSE_BREAKPOINT)

MISALIGNED_LOAD (1 << CAUSE_MISALIGNED_LOAD)

FAULT_LOAD (1 << CAUSE_FAULT_LOAD)

MISALIGNED_STORE (1 << CAUSE_MISALIGNED_STORE)

FAULT_STORE (1 << CAUSE_FAULT_STORE)

USER_ECALL (1 << CAUSE_USER_ECALL)

FETCH_PAGE_FAULT (1 << CAUSE_FETCH_PAGE_FAULT)

LOAD_PAGE_FAULT (1 << CAUSE_LOAD_PAGE_FAULT)

STORE_PAGE_FAULT (1 << CAUSE_STORE_PAGE_FAULT)

DCAUSE_FAULT_FETCH_PMP 0x1

DCAUSE_FAULT_FETCH_INST 0x2

DCAUSE_FAULT_LOAD_PMP 0x1

DCAUSE_FAULT_LOAD_INST 0x2

DCAUSE_FAULT_LOAD_NICE 0x3

DCAUSE_FAULT_STORE_PMP 0x1

DCAUSE_FAULT_STORE_INST 0x2

CSR_XSTATUS CSR_MSTATUS 

CSR_XTVEC CSR_MTVEC 

CSR_XCOUNTEREN CSR_MCOUNTEREN 

CSR_XIE CSR_MIE 

CSR_XIP CSR_MIP 

CSR_XSCRATCH CSR_MSCRATCH 

CSR_XEPC CSR_MEPC 

CSR_XCAUSE CSR_MCAUSE 

CSR_XSUBM CSR_MSUBM 

CSR_XTVAL CSR_MTVAL 

CSR_XENVCFG CSR_MENVCFG 

CSR_XTVT CSR_MTVT

CSR_XTVT2 CSR_MTVT2 

CSR_XSCRATCHCSWL CSR_MSCRATCHCSWL

CSR_XSCRATCHCSW CSR_MSCRATCHCSW

CSR_XDCAUSE CSR_MDCAUSE 

CSR_JALXNXTI CSR_JALMNXTI 

CSR_XINTSTATUS CSR_MINTSTATUS

CSR_XNXTI CSR_MNXTI

CSR_PUSHXEPC CSR_PUSHMEPC 

CSR_PUSHXCAUSE CSR_PUSHMCAUSE 

XRET mret

eclic_xsip_handler eclic_msip_handler

eclic_xtip_handler eclic_mtip_handler

XSTATUS_XIE MSTATUS_MIE 

x_exc_entry exc_entry 

x_irq_entry irq_entry 