Core CSR Encoding¶

Click Nuclei Core CSR to learn about Core CSR in Nuclei ISA Spec.

Core CSR Register Definitions¶

group NMSIS_Core_CSR_Registers

NMSIS Core CSR Register Definitions.

The following macros are used for CSR Register Defintions.

Defines

CSR_USTATUS 0x0¶

CSR_FFLAGS 0x1¶

CSR_FRM 0x2¶

CSR_FCSR 0x3¶

CSR_CYCLE 0xc00¶

CSR_TIME 0xc01¶

CSR_INSTRET 0xc02¶

CSR_HPMCOUNTER3 0xc03¶

CSR_HPMCOUNTER4 0xc04¶

CSR_HPMCOUNTER5 0xc05¶

CSR_HPMCOUNTER6 0xc06¶

CSR_HPMCOUNTER7 0xc07¶

CSR_HPMCOUNTER8 0xc08¶

CSR_HPMCOUNTER9 0xc09¶

CSR_HPMCOUNTER10 0xc0a¶

CSR_HPMCOUNTER11 0xc0b¶

CSR_HPMCOUNTER12 0xc0c¶

CSR_HPMCOUNTER13 0xc0d¶

CSR_HPMCOUNTER14 0xc0e¶

CSR_HPMCOUNTER15 0xc0f¶

CSR_HPMCOUNTER16 0xc10¶

CSR_HPMCOUNTER17 0xc11¶

CSR_HPMCOUNTER18 0xc12¶

CSR_HPMCOUNTER19 0xc13¶

CSR_HPMCOUNTER20 0xc14¶

CSR_HPMCOUNTER21 0xc15¶

CSR_HPMCOUNTER22 0xc16¶

CSR_HPMCOUNTER23 0xc17¶

CSR_HPMCOUNTER24 0xc18¶

CSR_HPMCOUNTER25 0xc19¶

CSR_HPMCOUNTER26 0xc1a¶

CSR_HPMCOUNTER27 0xc1b¶

CSR_HPMCOUNTER28 0xc1c¶

CSR_HPMCOUNTER29 0xc1d¶

CSR_HPMCOUNTER30 0xc1e¶

CSR_HPMCOUNTER31 0xc1f¶

CSR_SSTATUS 0x100¶

CSR_SIE 0x104¶

CSR_STVEC 0x105¶

CSR_SSCRATCH 0x140¶

CSR_SEPC 0x141¶

CSR_SCAUSE 0x142¶

CSR_SBADADDR 0x143¶

CSR_SIP 0x144¶

CSR_SPTBR 0x180¶

CSR_MSTATUS 0x300¶

CSR_MISA 0x301¶

CSR_MEDELEG 0x302¶

CSR_MIDELEG 0x303¶

CSR_MIE 0x304¶

CSR_MTVEC 0x305¶

CSR_MCOUNTEREN 0x306¶

CSR_MSCRATCH 0x340¶

CSR_MEPC 0x341¶

CSR_MCAUSE 0x342¶

CSR_MBADADDR 0x343¶

CSR_MTVAL 0x343¶

CSR_MIP 0x344¶

CSR_PMPCFG0 0x3a0¶

CSR_PMPCFG1 0x3a1¶

CSR_PMPCFG2 0x3a2¶

CSR_PMPCFG3 0x3a3¶

CSR_PMPADDR0 0x3b0¶

CSR_PMPADDR1 0x3b1¶

CSR_PMPADDR2 0x3b2¶

CSR_PMPADDR3 0x3b3¶

CSR_PMPADDR4 0x3b4¶

CSR_PMPADDR5 0x3b5¶

CSR_PMPADDR6 0x3b6¶

CSR_PMPADDR7 0x3b7¶

CSR_PMPADDR8 0x3b8¶

CSR_PMPADDR9 0x3b9¶

CSR_PMPADDR10 0x3ba¶

CSR_PMPADDR11 0x3bb¶

CSR_PMPADDR12 0x3bc¶

CSR_PMPADDR13 0x3bd¶

CSR_PMPADDR14 0x3be¶

CSR_PMPADDR15 0x3bf¶

CSR_TSELECT 0x7a0¶

CSR_TDATA1 0x7a1¶

CSR_TDATA2 0x7a2¶

CSR_TDATA3 0x7a3¶

CSR_DCSR 0x7b0¶

CSR_DPC 0x7b1¶

CSR_DSCRATCH 0x7b2¶

CSR_MCYCLE 0xb00¶

CSR_MINSTRET 0xb02¶

CSR_MHPMCOUNTER3 0xb03¶

CSR_MHPMCOUNTER4 0xb04¶

CSR_MHPMCOUNTER5 0xb05¶

CSR_MHPMCOUNTER6 0xb06¶

CSR_MHPMCOUNTER7 0xb07¶

CSR_MHPMCOUNTER8 0xb08¶

CSR_MHPMCOUNTER9 0xb09¶

CSR_MHPMCOUNTER10 0xb0a¶

CSR_MHPMCOUNTER11 0xb0b¶

CSR_MHPMCOUNTER12 0xb0c¶

CSR_MHPMCOUNTER13 0xb0d¶

CSR_MHPMCOUNTER14 0xb0e¶

CSR_MHPMCOUNTER15 0xb0f¶

CSR_MHPMCOUNTER16 0xb10¶

CSR_MHPMCOUNTER17 0xb11¶

CSR_MHPMCOUNTER18 0xb12¶

CSR_MHPMCOUNTER19 0xb13¶

CSR_MHPMCOUNTER20 0xb14¶

CSR_MHPMCOUNTER21 0xb15¶

CSR_MHPMCOUNTER22 0xb16¶

CSR_MHPMCOUNTER23 0xb17¶

CSR_MHPMCOUNTER24 0xb18¶

CSR_MHPMCOUNTER25 0xb19¶

CSR_MHPMCOUNTER26 0xb1a¶

CSR_MHPMCOUNTER27 0xb1b¶

CSR_MHPMCOUNTER28 0xb1c¶

CSR_MHPMCOUNTER29 0xb1d¶

CSR_MHPMCOUNTER30 0xb1e¶

CSR_MHPMCOUNTER31 0xb1f¶

CSR_MUCOUNTEREN 0x320¶

CSR_MSCOUNTEREN 0x321¶

CSR_MHPMEVENT3 0x323¶

CSR_MHPMEVENT4 0x324¶

CSR_MHPMEVENT5 0x325¶

CSR_MHPMEVENT6 0x326¶

CSR_MHPMEVENT7 0x327¶

CSR_MHPMEVENT8 0x328¶

CSR_MHPMEVENT9 0x329¶

CSR_MHPMEVENT10 0x32a¶

CSR_MHPMEVENT11 0x32b¶

CSR_MHPMEVENT12 0x32c¶

CSR_MHPMEVENT13 0x32d¶

CSR_MHPMEVENT14 0x32e¶

CSR_MHPMEVENT15 0x32f¶

CSR_MHPMEVENT16 0x330¶

CSR_MHPMEVENT17 0x331¶

CSR_MHPMEVENT18 0x332¶

CSR_MHPMEVENT19 0x333¶

CSR_MHPMEVENT20 0x334¶

CSR_MHPMEVENT21 0x335¶

CSR_MHPMEVENT22 0x336¶

CSR_MHPMEVENT23 0x337¶

CSR_MHPMEVENT24 0x338¶

CSR_MHPMEVENT25 0x339¶

CSR_MHPMEVENT26 0x33a¶

CSR_MHPMEVENT27 0x33b¶

CSR_MHPMEVENT28 0x33c¶

CSR_MHPMEVENT29 0x33d¶

CSR_MHPMEVENT30 0x33e¶

CSR_MHPMEVENT31 0x33f¶

CSR_MVENDORID 0xf11¶

CSR_MARCHID 0xf12¶

CSR_MIMPID 0xf13¶

CSR_MHARTID 0xf14¶

CSR_CYCLEH 0xc80¶

CSR_TIMEH 0xc81¶

CSR_INSTRETH 0xc82¶

CSR_HPMCOUNTER3H 0xc83¶

CSR_HPMCOUNTER4H 0xc84¶

CSR_HPMCOUNTER5H 0xc85¶

CSR_HPMCOUNTER6H 0xc86¶

CSR_HPMCOUNTER7H 0xc87¶

CSR_HPMCOUNTER8H 0xc88¶

CSR_HPMCOUNTER9H 0xc89¶

CSR_HPMCOUNTER10H 0xc8a¶

CSR_HPMCOUNTER11H 0xc8b¶

CSR_HPMCOUNTER12H 0xc8c¶

CSR_HPMCOUNTER13H 0xc8d¶

CSR_HPMCOUNTER14H 0xc8e¶

CSR_HPMCOUNTER15H 0xc8f¶

CSR_HPMCOUNTER16H 0xc90¶

CSR_HPMCOUNTER17H 0xc91¶

CSR_HPMCOUNTER18H 0xc92¶

CSR_HPMCOUNTER19H 0xc93¶

CSR_HPMCOUNTER20H 0xc94¶

CSR_HPMCOUNTER21H 0xc95¶

CSR_HPMCOUNTER22H 0xc96¶

CSR_HPMCOUNTER23H 0xc97¶

CSR_HPMCOUNTER24H 0xc98¶

CSR_HPMCOUNTER25H 0xc99¶

CSR_HPMCOUNTER26H 0xc9a¶

CSR_HPMCOUNTER27H 0xc9b¶

CSR_HPMCOUNTER28H 0xc9c¶

CSR_HPMCOUNTER29H 0xc9d¶

CSR_HPMCOUNTER30H 0xc9e¶

CSR_HPMCOUNTER31H 0xc9f¶

CSR_MCYCLEH 0xb80¶

CSR_MINSTRETH 0xb82¶

CSR_MHPMCOUNTER3H 0xb83¶

CSR_MHPMCOUNTER4H 0xb84¶

CSR_MHPMCOUNTER5H 0xb85¶

CSR_MHPMCOUNTER6H 0xb86¶

CSR_MHPMCOUNTER7H 0xb87¶

CSR_MHPMCOUNTER8H 0xb88¶

CSR_MHPMCOUNTER9H 0xb89¶

CSR_MHPMCOUNTER10H 0xb8a¶

CSR_MHPMCOUNTER11H 0xb8b¶

CSR_MHPMCOUNTER12H 0xb8c¶

CSR_MHPMCOUNTER13H 0xb8d¶

CSR_MHPMCOUNTER14H 0xb8e¶

CSR_MHPMCOUNTER15H 0xb8f¶

CSR_MHPMCOUNTER16H 0xb90¶

CSR_MHPMCOUNTER17H 0xb91¶

CSR_MHPMCOUNTER18H 0xb92¶

CSR_MHPMCOUNTER19H 0xb93¶

CSR_MHPMCOUNTER20H 0xb94¶

CSR_MHPMCOUNTER21H 0xb95¶

CSR_MHPMCOUNTER22H 0xb96¶

CSR_MHPMCOUNTER23H 0xb97¶

CSR_MHPMCOUNTER24H 0xb98¶

CSR_MHPMCOUNTER25H 0xb99¶

CSR_MHPMCOUNTER26H 0xb9a¶

CSR_MHPMCOUNTER27H 0xb9b¶

CSR_MHPMCOUNTER28H 0xb9c¶

CSR_MHPMCOUNTER29H 0xb9d¶

CSR_MHPMCOUNTER30H 0xb9e¶

CSR_MHPMCOUNTER31H 0xb9f¶

CSR_MTVT 0x307¶

CSR_MNXTI 0x345¶

CSR_MINTSTATUS 0x346¶

CSR_MSCRATCHCSW 0x348¶

CSR_MSCRATCHCSWL 0x349¶

CSR_MCLICBASE 0x350¶

CSR_MCOUNTINHIBIT 0x320¶

CSR_MILM_CTL 0x7C0¶

CSR_MDLM_CTL 0x7C1¶

CSR_MNVEC 0x7C3¶

CSR_MSUBM 0x7C4¶

CSR_MDCAUSE 0x7C9¶

CSR_MCACHE_CTL 0x7CA¶

CSR_MMISC_CTL 0x7D0¶

CSR_MSAVESTATUS 0x7D6¶

CSR_MSAVEEPC1 0x7D7¶

CSR_MSAVECAUSE1 0x7D8¶

CSR_MSAVEEPC2 0x7D9¶

CSR_MSAVECAUSE2 0x7DA¶

CSR_MSAVEDCAUSE1 0x7DB¶

CSR_MSAVEDCAUSE2 0x7DC¶

CSR_PUSHMSUBM 0x7EB¶

CSR_MTVT2 0x7EC¶

CSR_JALMNXTI 0x7ED¶

CSR_PUSHMCAUSE 0x7EE¶

CSR_PUSHMEPC 0x7EF¶

CSR_MPPICFG_INFO 0x7F0¶

CSR_MFIOCFG_INFO 0x7F1¶

CSR_SLEEPVALUE 0x811¶

CSR_TXEVT 0x812¶

CSR_WFE 0x810¶

CSR_MICFG_INFO 0xFC0¶

CSR_MDCFG_INFO 0xFC1¶

CSR_MCFG_INFO 0xFC2¶

Other Core Related Macros¶

group NMSIS_Core_CSR_Encoding

NMSIS Core CSR Encodings.

The following macros are used for CSR encodings

Defines

MSTATUS_UIE 0x00000001¶

MSTATUS_SIE 0x00000002¶

MSTATUS_HIE 0x00000004¶

MSTATUS_MIE 0x00000008¶

MSTATUS_UPIE 0x00000010¶

MSTATUS_SPIE 0x00000020¶

MSTATUS_HPIE 0x00000040¶

MSTATUS_MPIE 0x00000080¶

MSTATUS_SPP 0x00000100¶

MSTATUS_MPP 0x00001800¶

MSTATUS_FS 0x00006000¶

MSTATUS_XS 0x00018000¶

MSTATUS_MPRV 0x00020000¶

MSTATUS_PUM 0x00040000¶

MSTATUS_MXR 0x00080000¶

MSTATUS_VM 0x1F000000¶

MSTATUS32_SD 0x80000000¶

MSTATUS64_SD 0x8000000000000000¶

MSTATUS_FS_INITIAL 0x00002000¶

MSTATUS_FS_CLEAN 0x00004000¶

MSTATUS_FS_DIRTY 0x00006000¶

SSTATUS_UIE 0x00000001¶

SSTATUS_SIE 0x00000002¶

SSTATUS_UPIE 0x00000010¶

SSTATUS_SPIE 0x00000020¶

SSTATUS_SPP 0x00000100¶

SSTATUS_FS 0x00006000¶

SSTATUS_XS 0x00018000¶

SSTATUS_PUM 0x00040000¶

SSTATUS32_SD 0x80000000¶

SSTATUS64_SD 0x8000000000000000¶

CSR_MCACHE_CTL_IE 0x00000001¶

CSR_MCACHE_CTL_DE 0x00010000¶

DCSR_XDEBUGVER (3U<<30)¶

DCSR_NDRESET (1<<29)¶

DCSR_FULLRESET (1<<28)¶

DCSR_EBREAKM (1<<15)¶

DCSR_EBREAKH (1<<14)¶

DCSR_EBREAKS (1<<13)¶

DCSR_EBREAKU (1<<12)¶

DCSR_STOPCYCLE (1<<10)¶

DCSR_STOPTIME (1<<9)¶

DCSR_CAUSE (7<<6)¶

DCSR_DEBUGINT (1<<5)¶

DCSR_HALT (1<<3)¶

DCSR_STEP (1<<2)¶

DCSR_PRV (3<<0)¶

DCSR_CAUSE_NONE 0¶

DCSR_CAUSE_SWBP 1¶

DCSR_CAUSE_HWBP 2¶

DCSR_CAUSE_DEBUGINT 3¶

DCSR_CAUSE_STEP 4¶

DCSR_CAUSE_HALT 5¶

MCONTROL_TYPE(xlen) (0xfULL<<((xlen)-4))¶

MCONTROL_DMODE(xlen) (1ULL<<((xlen)-5))¶

MCONTROL_MASKMAX(xlen) (0x3fULL<<((xlen)-11))¶

MCONTROL_SELECT (1<<19)¶

MCONTROL_TIMING (1<<18)¶

MCONTROL_ACTION (0x3f<<12)¶

MCONTROL_CHAIN (1<<11)¶

MCONTROL_MATCH (0xf<<7)¶

MCONTROL_M (1<<6)¶

MCONTROL_H (1<<5)¶

MCONTROL_S (1<<4)¶

MCONTROL_U (1<<3)¶

MCONTROL_EXECUTE (1<<2)¶

MCONTROL_STORE (1<<1)¶

MCONTROL_LOAD (1<<0)¶

MCONTROL_TYPE_NONE 0¶

MCONTROL_TYPE_MATCH 2¶

MCONTROL_ACTION_DEBUG_EXCEPTION 0¶

MCONTROL_ACTION_DEBUG_MODE 1¶

MCONTROL_ACTION_TRACE_START 2¶

MCONTROL_ACTION_TRACE_STOP 3¶

MCONTROL_ACTION_TRACE_EMIT 4¶

MCONTROL_MATCH_EQUAL 0¶

MCONTROL_MATCH_NAPOT 1¶

MCONTROL_MATCH_GE 2¶

MCONTROL_MATCH_LT 3¶

MCONTROL_MATCH_MASK_LOW 4¶

MCONTROL_MATCH_MASK_HIGH 5¶

MIP_SSIP (1 << IRQ_S_SOFT)¶

MIP_HSIP (1 << IRQ_H_SOFT)¶

MIP_MSIP (1 << IRQ_M_SOFT)¶

MIP_STIP (1 << IRQ_S_TIMER)¶

MIP_HTIP (1 << IRQ_H_TIMER)¶

MIP_MTIP (1 << IRQ_M_TIMER)¶

MIP_SEIP (1 << IRQ_S_EXT)¶

MIP_HEIP (1 << IRQ_H_EXT)¶

MIP_MEIP (1 << IRQ_M_EXT)¶

MIE_SSIE MIP_SSIP ¶

MIE_HSIE MIP_HSIP ¶

MIE_MSIE MIP_MSIP ¶

MIE_STIE MIP_STIP ¶

MIE_HTIE MIP_HTIP ¶

MIE_MTIE MIP_MTIP ¶

MIE_SEIE MIP_SEIP ¶

MIE_HEIE MIP_HEIP ¶

MIE_MEIE MIP_MEIP ¶

WFE_WFE (0x1)¶

TXEVT_TXEVT (0x1)¶

SLEEPVALUE_SLEEPVALUE (0x1)¶

MCOUNTINHIBIT_IR (1<<2)¶

MCOUNTINHIBIT_CY (1<<0)¶

MILM_CTL_ILM_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10)¶

MILM_CTL_ILM_EN (1<<0)¶

MDLM_CTL_DLM_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10)¶

MDLM_CTL_DLM_EN (1<<0)¶

MSUBM_PTYP (0x3<<8)¶

MSUBM_TYP (0x3<<6)¶

MDCAUSE_MDCAUSE (0x3)¶

MMISC_CTL_NMI_CAUSE_FFF (1<<9)¶

MMISC_CTL_MISALIGN (1<<6)¶

MMISC_CTL_BPU (1<<3)¶

MCACHE_CTL_IC_EN (1<<0)¶

MCACHE_CTL_IC_SCPD_MOD (1<<1)¶

MCACHE_CTL_DC_EN (1<<16)¶

MTVT2_MTVT2EN (1<<0)¶

MTVT2_COMMON_CODE_ENTRY (((1ULL<<((__riscv_xlen)-2))-1)<<2)¶

MCFG_INFO_TEE (1<<0)¶

MCFG_INFO_ECC (1<<1)¶

MCFG_INFO_CLIC (1<<2)¶

MCFG_INFO_PLIC (1<<3)¶

MCFG_INFO_FIO (1<<4)¶

MCFG_INFO_PPI (1<<5)¶

MCFG_INFO_NICE (1<<6)¶

MCFG_INFO_ILM (1<<7)¶

MCFG_INFO_DLM (1<<8)¶

MCFG_INFO_ICACHE (1<<9)¶

MCFG_INFO_DCACHE (1<<10)¶

MICFG_IC_SET (0xF<<0)¶

MICFG_IC_WAY (0x7<<4)¶

MICFG_IC_LSIZE (0x7<<7)¶

MICFG_ILM_SIZE (0x1F<<16)¶

MICFG_ILM_XONLY (1<<21)¶

MDCFG_DC_SET (0xF<<0)¶

MDCFG_DC_WAY (0x7<<4)¶

MDCFG_DC_LSIZE (0x7<<7)¶

MDCFG_DLM_SIZE (0x1F<<16)¶

MPPICFG_INFO_PPI_SIZE (0x1F<<1)¶

MPPICFG_INFO_PPI_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10)¶

MFIOCFG_INFO_FIO_SIZE (0x1F<<1)¶

MFIOCFG_INFO_FIO_BPA (((1ULL<<((__riscv_xlen)-10))-1)<<10)¶

SIP_SSIP MIP_SSIP ¶

SIP_STIP MIP_STIP ¶

PRV_U 0¶

PRV_S 1¶

PRV_H 2¶

PRV_M 3¶

VM_MBARE 0¶

VM_MBB 1¶

VM_MBBID 2¶

VM_SV32 8¶

VM_SV39 9¶

VM_SV48 10¶

IRQ_S_SOFT 1¶

IRQ_H_SOFT 2¶

IRQ_M_SOFT 3¶

IRQ_S_TIMER 5¶

IRQ_H_TIMER 6¶

IRQ_M_TIMER 7¶

IRQ_S_EXT 9¶

IRQ_H_EXT 10¶

IRQ_M_EXT 11¶

IRQ_COP 12¶

IRQ_HOST 13¶

DEFAULT_RSTVEC 0x00001000¶

DEFAULT_NMIVEC 0x00001004¶

DEFAULT_MTVEC 0x00001010¶

CONFIG_STRING_ADDR 0x0000100C¶

EXT_IO_BASE 0x40000000¶

DRAM_BASE 0x80000000¶

FRM_RNDMODE_RNE 0x0¶: FPU Round to Nearest, ties to Even.

FRM_RNDMODE_RTZ 0x1¶: FPU Round Towards Zero.

FRM_RNDMODE_RDN 0x2¶: FPU Round Down (towards -inf)

FRM_RNDMODE_RUP 0x3¶: FPU Round Up (towards +inf)

FRM_RNDMODE_RMM 0x4¶: FPU Round to nearest, ties to Max Magnitude.

FRM_RNDMODE_DYN 0x7¶

In instruction’s rm, selects dynamic rounding mode.

In Rounding Mode register, Invalid

FFLAGS_AE_NX (1<<0)¶: FPU Inexact.

FFLAGS_AE_UF (1<<1)¶: FPU Underflow.

FFLAGS_AE_OF (1<<2)¶: FPU Overflow.

FFLAGS_AE_DZ (1<<3)¶: FPU Divide by Zero.

FFLAGS_AE_NV (1<<4)¶: FPU Invalid Operation.

FREG(idx) f##idx¶

Floating Point Register f0-f31, eg.

PMP_R 0x01¶

PMP_W 0x02¶

PMP_X 0x04¶

PMP_A 0x18¶

PMP_A_TOR 0x08¶

PMP_A_NA4 0x10¶

PMP_A_NAPOT 0x18¶

PMP_L 0x80¶

PMP_SHIFT 2¶

PMP_COUNT 16¶

PTE_V 0x001¶

PTE_R 0x002¶

PTE_W 0x004¶

PTE_X 0x008¶

PTE_U 0x010¶

PTE_G 0x020¶

PTE_A 0x040¶

PTE_D 0x080¶

PTE_SOFT 0x300¶

PTE_PPN_SHIFT 10¶

PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V)¶

DOWNLOAD_MODE_FLASHXIP 0¶

DOWNLOAD_MODE_FLASH 1¶

DOWNLOAD_MODE_ILM 2¶

DOWNLOAD_MODE_DDR 3¶

CAUSE_MISALIGNED_FETCH 0x0¶: End of Doxygen Group NMSIS_Core_CSR_Registers.

CAUSE_FAULT_FETCH 0x1¶

CAUSE_ILLEGAL_INSTRUCTION 0x2¶

CAUSE_BREAKPOINT 0x3¶

CAUSE_MISALIGNED_LOAD 0x4¶

CAUSE_FAULT_LOAD 0x5¶

CAUSE_MISALIGNED_STORE 0x6¶

CAUSE_FAULT_STORE 0x7¶

CAUSE_USER_ECALL 0x8¶

CAUSE_SUPERVISOR_ECALL 0x9¶

CAUSE_HYPERVISOR_ECALL 0xa¶

CAUSE_MACHINE_ECALL 0xb¶

DCAUSE_FAULT_FETCH_PMP 0x1¶

DCAUSE_FAULT_FETCH_INST 0x2¶

DCAUSE_FAULT_LOAD_PMP 0x1¶

DCAUSE_FAULT_LOAD_INST 0x2¶

DCAUSE_FAULT_LOAD_NICE 0x3¶

DCAUSE_FAULT_STORE_PMP 0x1¶

DCAUSE_FAULT_STORE_INST 0x2¶