Overview

Introduction

NMSIS-Core implements the basic run-time system for a Nuclei N/NX Class Processors based device and gives the user access to the processor core and the device peripherals. In detail it defines:

Hardware Abstraction Layer (HAL) for Nuclei processor registers with standardized definitions for the CSR Registers, TIMER, ECLIC, PMP Registers, DSP Registers, FPU registers, and Core Access Functions.
Standard core exception/interrupt names to interface to system exceptions or interrupts without having compatibility issues.
Methods to organize header files that makes it easy to learn new Nuclei micro-controller products and improve software portability. This includes naming conventions for device-specific interrupts.
Methods for system initialization to be used by each Device vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
A variable SystemCoreClock to determine the system clock frequency which simplifies the setup the timer.

The following sections provide details about the NMSIS-Core:

Using NMSIS in Embedded Applications describes the project setup and shows a simple program example
NMSIS-Core Device Templates describes the files of the NMSIS Core in detail and explains how to adapt template files provided by Nuclei to silicon vendor devices.
NMSIS Core API describe the features and functions of the Device Header File <Device.h> in detail.
Register Define and Type Definitions describe the data structures of the Device Header File <Device.h> in detail.

Processor Support

NMSIS have provided support for all the Nuclei N/NX Class Processors.

Nuclei ISA Spec:

Please contact with our sales about Nuclei Process Core Instruction Set Architecture Spec Nuclei_RISC-V_ISA_Spec.pdf.

Nuclei Processor Reference Manuals:

Toolchain Support

The NMSIS-Core Device Templates provided by Nuclei have been tested and verified using these toolchains:

GNU GCC/LLVM Clang Toolchain for RISC-V modified by Nuclei, see https://www.nucleisys.com/download.php#tools
IAR Compiler for RISC-V, see https://www.iar.com/riscv