Device Header File <Device.h>
- The Device Header File <Device.h> contains the following sections that are device specific:
Interrupt Number Definition provides interrupt numbers (IRQn) for all exceptions and interrupts of the device.
Configuration of the Processor and Core Peripherals reflect the features of the device.
Device Peripheral Access Layer provides definitions for the Peripheral Access to all device peripherals. It contains all data structures and the address mapping for device-specific peripherals.
Access Functions for Peripherals (optional) provide additional helper functions for peripherals that are useful for programming of these peripherals. Access Functions may be provided as inline functions or can be extern references to a device-specific library provided by the silicon vendor.
NMSIS Core API describes the standard features and functions of the Device Header File <Device.h> in detail.
Interrupt Number Definition
- Device Header File <Device.h> contains the enumeration
IRQn_Typethat defines all exceptions and interrupts of the device. Negative IRQn values represent processor core exceptions (internal interrupts).
Positive IRQn values represent device-specific exceptions (external interrupts). The first device-specific interrupt has the IRQn value 0. The IRQn values needs extension to reflect the device-specific interrupt vector table in the Startup File startup_<Device>.S.
The following example shows the extension of the interrupt vector table for the GD32VF103 device family.
1typedef enum IRQn {
2 /****** N200 Processor Exceptions Numbers *********************************************/
3 Reserved0_IRQn = 0, /*!< Internal reserved */
4 Reserved1_IRQn = 1, /*!< Internal reserved */
5 Reserved2_IRQn = 2, /*!< Internal reserved */
6 SysTimerSW_IRQn = 3, /*!< System Timer SW interrupt */
7 Reserved3_IRQn = 4, /*!< Internal reserved */
8 Reserved4_IRQn = 5, /*!< Internal reserved */
9 Reserved5_IRQn = 6, /*!< Internal reserved */
10 SysTimer_IRQn = 7, /*!< System Timer Interrupt */
11 Reserved6_IRQn = 8, /*!< Internal reserved */
12 Reserved7_IRQn = 9, /*!< Internal reserved */
13 Reserved8_IRQn = 10, /*!< Internal reserved */
14 Reserved9_IRQn = 11, /*!< Internal reserved */
15 Reserved10_IRQn = 12, /*!< Internal reserved */
16 Reserved11_IRQn = 13, /*!< Internal reserved */
17 Reserved12_IRQn = 14, /*!< Internal reserved */
18 Reserved13_IRQn = 15, /*!< Internal reserved */
19 Reserved14_IRQn = 16, /*!< Internal reserved */
20 HardFault_IRQn = 17, /*!< Hard Fault, storage access error */
21 Reserved15_IRQn = 18, /*!< Internal reserved */
22
23 /****** GD32VF103 Specific Interrupt Numbers ******************************************/
24 WWDGT_IRQn = 19, /*!< window watchDog timer interrupt */
25 LVD_IRQn = 20, /*!< LVD through EXTI line detect interrupt */
26 TAMPER_IRQn = 21, /*!< tamper through EXTI line detect */
27 : :
28 : :
29 CAN1_EWMC_IRQn = 85, /*!< CAN1 EWMC interrupt */
30 USBFS_IRQn = 86, /*!< USBFS global interrupt */
31 SOC_INT_MAX, /*!< Number of total Interrupts */
32} IRQn_Type;
Configuration of the Processor and Core Peripherals
The Device Header File <Device.h> configures the Nuclei N/NX Class Processors and the core peripherals with
#define that are set prior to including the file nmsis_core.h.
For recently released Nuclei 200/300/600/900 RISC-V CPU, the cpu private peripherals are also called internal regions(IREGION) and the address spaces are continuous with fixed size, cpu will be configured with only the base address of IREGION, such as ECLIC, TIMER, SMP, Cluster Cache, CIDU, PLIC unit, for more details, please check Nuclei ISA Spec and related CPU databook.
The following tables list the #define along with the possible values for N200, N300, N600, NX600.
If these #define are missing default values are used.
nmsis_core.h
Note
__NUCLEI_N_REVand__NUCLEI_NX_REVare deprecated since 1.2.0, please use__NUCLEI_CPU_REVand__NUCLEI_CPU_SERIESnow.__HARTID_OFFSETand__SYSTIMER_HARTIDis added since 1.2.0
#define |
Value Range |
Default |
Description |
__NUCLEI_N_REV OR
__NUCLEI_NX_REV
|
0x0100 |
0x0104
|
0x0100 |
|
__NUCLEI_CPU_REV |
Define Nuclei CPU Revision Number, such as 0x030A01 means v3.10.1. |
||
__NUCLEI_CPU_SERIES |
Define Nuclei CPU Series, such as 0x0200, 0x0300, 0x0600, 0x0900 for 200/300/600/900 series. |
||
__HARTID_OFFSET |
Define the offset of the first cpu hart’s hartid vs hart index, eg, cpu first hartid is 3, set it to 3. |
||
__SYSTIMER_PRESENT |
0 .. 1 |
1 |
Define whether Priviate System Timer is present or not. This SysTimer is a Memory Mapped Unit. |
__SYSTIMER_BASEADDR |
0x18030000 |
Base address of the System Timer Unit. |
|
__SYSTIMER_HARTID |
Optional, if you cpu system only has one hart, and the timer hartid is known, you can set it to known value |
||
__ECLIC_PRESENT |
0 .. 1 |
1 |
Define whether Enhanced Core Local Interrupt Controller (ECLIC) Unit is present or not |
__ECLIC_BASEADDR |
0x18020000 |
Base address of the ECLIC unit. |
|
__CIDU_PRESENT |
0 .. 1 |
0 |
Define whether Cluster Interrupt Distribution Unit (CIDU) is present or not |
__CIDU_BASEADDR |
0x18050000 |
Base address of the CIDU unit. |
|
__ECLIC_INTCTLBITS |
1 .. 8 |
1 |
Define the number of hardware bits are actually implemented in the clicintctl registers. |
__ECLIC_INTNUM |
1 .. 1024 |
1 |
Define the total interrupt number(including the internal core interrupts) of ECLIC Unit |
__PMP_PRESENT |
0 .. 1 |
0 |
Define whether Physical Memory Protection (PMP) Unit is present or not. |
__PMP_ENTRY_NUM |
8 or 16 |
8 |
Define the numbers of PMP entries. |
__SPMP_PRESENT |
0 .. 1 |
0 |
Define whether SMode Physical Memory Protection (sPMP) Unit is present or not. |
__SPMP_ENTRY_NUM |
8 or 16 |
8 |
Define the numbers of sPMP entries. |
__FPU_PRESENT |
0 .. 2 |
0 |
Define whether Floating Point Unit (FPU) is present or not.
|
__BITMANIP_PRESENT |
0 .. 1 |
0 |
Define whether Bitmainp Unit is present or not. |
__DSP_PRESENT |
0 .. 1 |
0 |
Define whether Digital Signal Processing Unit (DSP) is present or not. |
__VECTOR_PRESENT |
0 .. 1 |
0 |
Define whether Vector Unit is present or not. |
__ICACHE_PRESENT |
0 .. 1 |
0 |
Define whether I-Cache Unit is present or not. |
__DCACHE_PRESENT |
0 .. 1 |
0 |
Define whether D-Cache Unit is present or not. |
__CCM_PRESENT |
0 .. 1 |
0 |
Define whether Nuclei Cache Control and Mantainence Unit is present or not. |
__INC_INTRINSIC_API |
0 .. 1 |
0 |
Define whether toolchain provided intrinsic api headers are included or not. |
__Vendor_SysTickConfig |
0 .. 1 |
0 |
If __SYSTIMER_PRESENT is 1, then the __Vendor_SysTickConfig can be set to 0, otherwise it can only set to 1. If this define is set to 1, then the default SysTick_Config and SysTick_Reload function is excluded. In this case, the file Device.h must contain a vendor specific implementation of this function. |
NMSIS Version and Processor Information
The following shows the defines in the nmsis_core.h file that may be used in the NMSIS-Core Device Templates to verify a minimum version or ensure that the right Nuclei N/NX/U/UX class is used.
Device Peripheral Access Layer
- The Device Header File <Device.h> contains for each peripheral:
Register Layout Typedef
Base Address
Access Definitions
The section Peripheral Access shows examples for peripheral definitions.
Device.h Template File
Here we provided Device.h template file as below:
1/*
2 * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
3 * Copyright (c) 2019 Nuclei Limited. All rights reserved.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 *
7 * Licensed under the Apache License, Version 2.0 (the License); you may
8 * not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
15 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 */
19/******************************************************************************
20 * @file <Device>.h
21 * @brief NMSIS Nuclei N/NX Core Peripheral Access Layer Header File for
22 * Device <Device>
23 * @version V2.1.0
24 * @date 19. Dec 2023
25 ******************************************************************************/
26
27#ifndef __<Device>_H__ /* TODO: replace '<Device>' with your device name */
28#define __<Device>_H__
29
30#ifdef __cplusplus
31extern "C" {
32#endif
33
34/* TODO: replace '<Vendor>' with vendor name; add your doxygen comment */
35/** @addtogroup <Vendor>
36 * @{
37 */
38
39
40/* TODO: replace '<Device>' with device name; add your doxygen comment */
41/** @addtogroup <Device>
42 * @{
43 */
44
45
46/** @addtogroup Configuration_of_NMSIS
47 * @{
48 */
49
50/** \brief SoC Download mode definition */
51/* TODO: device vendor can extend more download modes */
52typedef enum {
53 DOWNLOAD_MODE_FLASHXIP = 0, /*!< Flashxip download mode */
54 DOWNLOAD_MODE_FLASH = 1, /*!< Flash download mode */
55 DOWNLOAD_MODE_ILM = 2, /*!< ilm download mode */
56 DOWNLOAD_MODE_DDR = 3, /*!< ddr download mode */
57 DOWNLOAD_MODE_SRAM = 4, /*!< sram download mode */
58 DOWNLOAD_MODE_MAX,
59} DownloadMode_Type;
60
61/** \brief CPU Internal Region Information */
62typedef struct IRegion_Info {
63 unsigned long iregion_base; /*!< Internal region base address */
64 unsigned long eclic_base; /*!< eclic base address */
65 unsigned long systimer_base; /*!< system timer base address */
66 unsigned long smp_base; /*!< smp base address */
67 unsigned long idu_base; /*!< idu base address */
68} IRegion_Info_Type;
69
70/* =========================================================================================================================== */
71/* ================ Interrupt Number Definition ================ */
72/* =========================================================================================================================== */
73
74typedef enum IRQn {
75/* ======================================== Nuclei N/NX Specific Interrupt Numbers ========================================= */
76
77/* TODO: use this N/NX interrupt numbers if your device is a Nuclei N/NX device */
78 Reserved0_IRQn = 0, /*!< Internal reserved */
79 Reserved1_IRQn = 1, /*!< Internal reserved */
80 Reserved2_IRQn = 2, /*!< Internal reserved */
81 SysTimerSW_IRQn = 3, /*!< System Timer SW interrupt for both M/S mode in ECLIC */
82 Reserved3_IRQn = 4, /*!< Internal reserved */
83 Reserved4_IRQn = 5, /*!< Internal reserved */
84 Reserved5_IRQn = 6, /*!< Internal reserved */
85 SysTimer_IRQn = 7, /*!< System Timer Interrupt for both M/S mode in ECLIC */
86 Reserved6_IRQn = 8, /*!< Internal reserved */
87 Reserved7_IRQn = 9, /*!< Internal reserved */
88 Reserved8_IRQn = 10, /*!< Internal reserved */
89 Reserved9_IRQn = 11, /*!< Internal reserved */
90 Reserved10_IRQn = 12, /*!< Internal reserved */
91 Reserved11_IRQn = 13, /*!< Internal reserved */
92 Reserved12_IRQn = 14, /*!< Internal reserved */
93 Reserved13_IRQn = 15, /*!< Internal reserved */
94 InterCore_IRQn = 16, /*!< CIDU Inter Core Interrupt */
95 Reserved15_IRQn = 17, /*!< Internal reserved */
96 Reserved16_IRQn = 18, /*!< Internal reserved */
97
98/* =========================================== <Device> Specific Interrupt Numbers ========================================= */
99/* TODO: add here your device specific external interrupt numbers. 19~1023 is reserved number for user. Maxmum interrupt supported
100 could get from clicinfo.NUM_INTERRUPT. According the interrupt handlers defined in startup_Device.s
101 eg.: Interrupt for Timer#1 eclic_tim0_handler -> TIM0_IRQn */
102 <DeviceInterrupt>_IRQn = 19, /*!< Device Interrupt */
103
104 SOC_INT_MAX, /* Max SoC interrupt Number */
105} IRQn_Type;
106
107/* =========================================================================================================================== */
108/* ================ Exception Code Definition ================ */
109/* =========================================================================================================================== */
110
111typedef enum EXCn {
112/* ======================================= Nuclei N/NX Specific Exception Code ======================================== */
113 InsUnalign_EXCn = 0, /*!< Instruction address misaligned */
114 InsAccFault_EXCn = 1, /*!< Instruction access fault */
115 IlleIns_EXCn = 2, /*!< Illegal instruction */
116 Break_EXCn = 3, /*!< Beakpoint */
117 LdAddrUnalign_EXCn = 4, /*!< Load address misaligned */
118 LdFault_EXCn = 5, /*!< Load access fault */
119 StAddrUnalign_EXCn = 6, /*!< Store or AMO address misaligned */
120 StAccessFault_EXCn = 7, /*!< Store or AMO access fault */
121 UmodeEcall_EXCn = 8, /*!< Environment call from User mode */
122 SmodeEcall_EXCn = 9, /*!< Environment call from S-mode */
123 MmodeEcall_EXCn = 11, /*!< Environment call from Machine mode */
124 InsPageFault_EXCn = 12, /*!< Instruction page fault */
125 LdPageFault_EXCn = 13, /*!< Load page fault */
126 StPageFault_EXCn = 15, /*!< Store or AMO page fault */
127 StackOverflow_EXCn = 24, /*!< Stack overflow fault */
128 StackUnderflow_EXCn = 25, /*!< Stack underflow fault */
129 NMI_EXCn = 0xfff, /*!< NMI interrupt */
130} EXCn_Type;
131
132/* =========================================================================================================================== */
133/* ================ Processor and Core Peripheral Section ================ */
134/* =========================================================================================================================== */
135extern volatile IRegion_Info_Type SystemIRegionInfo;
136/* =========================== Configuration of the Nuclei N/NX Processor and Core Peripherals =========================== */
137/* TODO: set the defines according your Device */
138/* TODO: define the correct core revision
139 * __NUCLEI_N_REV if your device is a Nuclei-N Class device, which is 32bit CPU
140 * __NUCLEI_NX_REV if your device is a Nuclei-NX Class device, which is 64bit CPU
141 */
142#define __NUCLEI_N#_REV 0x0100 /*!< Core Revision rXpY, version X.Y, change N# to N for Nuclei N class cores, change N# to NX for Nuclei NX cores */
143#define __NUCLEI_CPU_REV 0x030600 /*!< Nuclei CPU Core Revision, version X.Y.Z, this is for the CPU Core Version, you get from Nuclei, eg. N300 v3.10.1, it should be 0x030A01 */
144#define __NUCLEI_CPU_SERIES 0x0300 /*!< Nuclei CPU Series, such as 200/300/600/900, eg. 900 will be 0x0900 */
145/* TODO: define the correct core features for the <Device> */
146/**
147 * If your hart index is different to your hartid, you must define this __HARTID_OFFSET macro.
148 * For example, if your cpu has 4 harts, and hartid start from 3, so the __HARTID_OFFSET should set to 3.
149 * Which means hartid 3-6 means hart index 0-3, this is useful for the timer software interrupt and timer interrupt trigger register location
150 */
151#ifndef __HARTID_OFFSET
152#define __HARTID_OFFSET 0
153#endif
154#define __ECLIC_PRESENT 1 /*!< Set to 1 if ECLIC is present */
155#define __ECLIC_BASEADDR SystemIRegionInfo.eclic_base /*!< Set to ECLIC baseaddr of your device */
156#define __ECLIC_INTCTLBITS 8 /*!< Set to 1 - 8, the number of hardware bits are actually implemented in the clicintctl registers. */
157#define __ECLIC_INTNUM 64 /*!< Set to 1 - 1024, total interrupt number of ECLIC Unit */
158#define __SYSTIMER_PRESENT 1 /*!< Set to 1 if System Timer is present */
159#define __SYSTIMER_BASEADDR SystemIRegionInfo.systimer_base /*!< Set to SysTimer baseaddr of your device */
160//#define __SYSTIMER_HARTID 0 /*!< Set this timer hartid if you have only 1 hart in your cpu, and you know the timer hartid, just set it */
161#define __CIDU_PRESENT 0 /*!< Set to 1 if CIDU is present */
162#define __CIDU_BASEADDR SystemIRegionInfo.idu_base /*!< Set to cidu baseaddr of your device */
163#define __FPU_PRESENT 1 /*!< Set to 0, 1, or 2, 0 not present, 1 single floating point unit present, 2 double floating point unit present */
164#define __BITMANIP_PRESENT 1 /*!< Set to 1 if Bitmainpulation extension is present */
165#define __DSP_PRESENT 1 /*!< Set to 1 if DSP is present */
166#define __VECTOR_PRESENT 1 /*!< Set to 1 if Vector extension is present */
167#define __PMP_PRESENT 1 /*!< Set to 1 if PMP is present */
168#define __PMP_ENTRY_NUM 16 /*!< Set to 8 or 16, the number of PMP entries */
169#define __SPMP_PRESENT 1 /*!< Set to 1 if SPMP is present */
170#define __SPMP_ENTRY_NUM 16 /*!< Set to 8 or 16, the number of SPMP entries */
171#define __TEE_PRESENT 0 /*!< Set to 1 if TEE is present */
172#define __ICACHE_PRESENT 0 /*!< Set to 1 if I-Cache is present */
173#define __DCACHE_PRESENT 0 /*!< Set to 1 if D-Cache is present */
174#define __CCM_PRESENT 0 /*!< Set to 1 if Cache Control and Mantainence Unit is present */
175#define __INC_INTRINSIC_API 0 /*!< Set to 1 if intrinsic api header files need to be included */
176#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
177#define __Vendor_EXCEPTION 0 /*!< Set to 1 if vendor exception hander is present */
178
179/** @} */ /* End of group Configuration_of_NMSIS */
180
181
182#include <nmsis_core.h>
183/* TODO: include your system_<Device>.h file
184 replace '<Device>' with your device name */
185#include "system_<Device>.h" /*!< <Device> System */
186
187
188/* ======================================== Start of section using anonymous unions ======================================== */
189
190
191/* =========================================================================================================================== */
192/* ================ Device Specific Peripheral Section ================ */
193/* =========================================================================================================================== */
194/* Macros for memory access operations */
195#define _REG8P(p, i) ((volatile uint8_t *) ((uintptr_t)((p) + (i))))
196#define _REG16P(p, i) ((volatile uint16_t *) ((uintptr_t)((p) + (i))))
197#define _REG32P(p, i) ((volatile uint32_t *) ((uintptr_t)((p) + (i))))
198#define _REG64P(p, i) ((volatile uint64_t *) ((uintptr_t)((p) + (i))))
199#define _REG8(p, i) (*(_REG8P(p, i)))
200#define _REG16(p, i) (*(_REG16P(p, i)))
201#define _REG32(p, i) (*(_REG32P(p, i)))
202#define _REG64(p, i) (*(_REG64P(p, i)))
203#define REG8(addr) _REG8((addr), 0)
204#define REG16(addr) _REG16((addr), 0)
205#define REG32(addr) _REG32((addr), 0)
206#define REG64(addr) _REG64((addr), 0)
207
208/* Macros for address type convert and access operations */
209#define ADDR16(addr) ((uint16_t)(uintptr_t)(addr))
210#define ADDR32(addr) ((uint32_t)(uintptr_t)(addr))
211#define ADDR64(addr) ((uint64_t)(uintptr_t)(addr))
212#define ADDR8P(addr) ((uint8_t *)(uintptr_t)(addr))
213#define ADDR16P(addr) ((uint16_t *)(uintptr_t)(addr))
214#define ADDR32P(addr) ((uint32_t *)(uintptr_t)(addr))
215#define ADDR64P(addr) ((uint64_t *)(uintptr_t)(addr))
216
217/* Macros for Bit Operations */
218#if __riscv_xlen == 32
219#define BITMASK_MAX 0xFFFFFFFFUL
220#define BITOFS_MAX 31
221#else
222#define BITMASK_MAX 0xFFFFFFFFFFFFFFFFULL
223#define BITOFS_MAX 63
224#endif
225
226// BIT/BITS only support bit mask for __riscv_xlen
227// For RISC-V 32 bit, it support mask 32 bit wide
228// For RISC-V 64 bit, it support mask 64 bit wide
229#define BIT(ofs) (0x1UL << (ofs))
230#define BITS(start, end) ((BITMASK_MAX) << (start) & (BITMASK_MAX) >> (BITOFS_MAX - (end)))
231#define GET_BIT(regval, bitofs) (((regval) >> (bitofs)) & 0x1)
232#define SET_BIT(regval, bitofs) ((regval) |= BIT(bitofs))
233#define CLR_BIT(regval, bitofs) ((regval) &= (~BIT(bitofs)))
234#define FLIP_BIT(regval, bitofs) ((regval) ^= BIT(bitofs))
235#define WRITE_BIT(regval, bitofs, val) CLR_BIT(regval, bitofs); ((regval) |= ((val) << bitofs) & BIT(bitofs))
236#define CHECK_BIT(regval, bitofs) (!!((regval) & (0x1UL<<(bitofs))))
237#define GET_BITS(regval, start, end) (((regval) & BITS((start), (end))) >> (start))
238#define SET_BITS(regval, start, end) ((regval) |= BITS((start), (end)))
239#define CLR_BITS(regval, start, end) ((regval) &= (~BITS((start), (end))))
240#define FLIP_BITS(regval, start, end) ((regval) ^= BITS((start), (end)))
241#define WRITE_BITS(regval, start, end, val) CLR_BITS(regval, start, end); ((regval) |= ((val) << start) & BITS((start), (end)))
242#define CHECK_BITS_ALL(regval, start, end) (!((~(regval)) & BITS((start), (end))))
243#define CHECK_BITS_ANY(regval, start, end) ((regval) & BITS((start), (end)))
244
245#define BITMASK_SET(regval, mask) ((regval) |= (mask))
246#define BITMASK_CLR(regval, mask) ((regval) &= (~(mask)))
247#define BITMASK_FLIP(regval, mask) ((regval) ^= (mask))
248#define BITMASK_CHECK_ALL(regval, mask) (!((~(regval)) & (mask)))
249#define BITMASK_CHECK_ANY(regval, mask) ((regval) & (mask))
250
251/** @addtogroup Device_Peripheral_peripherals
252 * @{
253 */
254
255/* TODO: add here your device specific peripheral access structure typedefs
256 following is an example for UART */
257
258/* =========================================================================================================================== */
259/* ================ UART ================ */
260/* =========================================================================================================================== */
261
262/**
263 * @brief UART (UART)
264 */
265typedef struct { /*!< (@ 0x40000000) UART Structure */
266 __IOM uint32_t TXFIFO; /*!< (@ 0x00000000) UART TX FIFO */
267 __IM uint32_t RXFIFO; /*!< (@ 0x00000004) UART RX FIFO */
268 __IOM uint32_t TXCTRL; /*!< (@ 0x00000008) UART TX FIFO control */
269 __OM uint32_t RXCTRL; /*!< (@ 0x0000000C) UART RX FIFO control */
270 __IM uint32_t IE; /*!< (@ 0x00000010) UART Interrupt Enable flag */
271 __IM uint32_t IP; /*!< (@ 0x00000018) TART Interrupt Pending flag */
272 __IM uint32_t DIV; /*!< (@ 0x00000018) UART Baudrate Divider */
273} <DeviceAbbreviation>_UART_TypeDef;
274
275/*@}*/ /* end of group <Device>_Peripherals */
276
277
278/* ========================================= End of section using anonymous unions ========================================= */
279
280/* =========================================================================================================================== */
281/* ================ Device Specific Peripheral Address Map ================ */
282/* =========================================================================================================================== */
283
284
285/* TODO: add here your device peripherals base addresses
286 following is an example for timer */
287/** @addtogroup Device_Peripheral_peripheralAddr
288 * @{
289 */
290
291/* Peripheral and SRAM base address */
292#define <DeviceAbbreviation>_FLASH_BASE (0x00000000UL) /*!< (FLASH ) Base Address */
293#define <DeviceAbbreviation>_SRAM_BASE (0x20000000UL) /*!< (SRAM ) Base Address */
294#define <DeviceAbbreviation>_PERIPH_BASE (0x40000000UL) /*!< (Peripheral) Base Address */
295
296/* Peripheral memory map */
297#define <DeviceAbbreviation>UART0_BASE (<DeviceAbbreviation>_PERIPH_BASE) /*!< (UART 0 ) Base Address */
298#define <DeviceAbbreviation>I2C_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x0800) /*!< (I2C ) Base Address */
299#define <DeviceAbbreviation>GPIO_BASE (<DeviceAbbreviation>_PERIPH_BASE + 0x1000) /*!< (GPIO ) Base Address */
300
301/** @} */ /* End of group Device_Peripheral_peripheralAddr */
302
303
304/* =========================================================================================================================== */
305/* ================ Peripheral declaration ================ */
306/* =========================================================================================================================== */
307
308
309/* TODO: add here your device peripherals pointer definitions
310 following is an example for uart0 */
311/** @addtogroup Device_Peripheral_declaration
312 * @{
313 */
314#define <DeviceAbbreviation>_UART0 ((<DeviceAbbreviation>_TMR_TypeDef *) <DeviceAbbreviation>UART0_BASE)
315
316
317/** @} */ /* End of group <Device> */
318
319/** @} */ /* End of group <Vendor> */
320
321#ifdef __cplusplus
322}
323#endif
324
325#endif /* __<Device>_H__ */