System Configuration Files system_<Device>.c and system_<Device>.h
Caution
Please be informed that the NMSIS-Core Device Templates may not be updated in a timely manner and thus could become outdated. We suggest referring to the specific implementation of evalsoc in the Nuclei SDK for the latest reference template. This reference template may not be actively maintained in the future.
The System Configuration Files system_<device>.c and system_<device>.h provides as a minimum the functions described under System Device Configuration.
These functions are device specific and need adaptations. In addition, the file might have configuration settings for the device such as XTAL frequency or PLL prescaler settings, necessary system initialization, vendor customized interrupt, exception and nmi handling code, refer to System Device Configuration for more details.
For devices with external memory BUS the system_<Device>.c also configures the BUS system.
The silicon vendor might expose other functions (i.e. for power configuration) in the system_<Device>.c file.
In case of additional features the function prototypes need to be added to the system_<Device>.h header file.
system_Device.c Template File
Here we provided system_Device.c template file as below:
Please check file content in https://github.com/Nuclei-Software/NMSIS/blob/master/Device/_Template_Vendor/Vendor/Device/Source/system_Device.c
system_Device.h Template File
Here we provided system_Device.h template file as below:
1/*
2 * Copyright (c) 2009-2018 Arm Limited. All rights reserved.
3 * Copyright (c) 2019 Nuclei Limited. All rights reserved.
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 *
7 * Licensed under the Apache License, Version 2.0 (the License); you may
8 * not use this file except in compliance with the License.
9 * You may obtain a copy of the License at
10 *
11 * www.apache.org/licenses/LICENSE-2.0
12 *
13 * Unless required by applicable law or agreed to in writing, software
14 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
15 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
16 * See the License for the specific language governing permissions and
17 * limitations under the License.
18 */
19/*******************************************************************************
20 * @file system_<Device>.h
21 * @brief NMSIS Nuclei N/NX Device Peripheral Access Layer Header File for
22 * Device <Device>
23 * @version V1.00
24 * @date 17. Dec 2019
25 ******************************************************************************/
26
27#ifndef __SYSTEM_<Device>_H__ /* ToDo: replace '<Device>' with your device name */
28#define __SYSTEM_<Device>_H__
29
30// NOTE: Should never directly include this header, you should include <Device>.h
31
32#ifdef __cplusplus
33extern "C" {
34#endif
35
36#include <stdint.h>
37
38extern volatile uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
39
40typedef struct EXC_Frame {
41 unsigned long ra; /* ra: x1, return address for jump */
42 unsigned long tp; /* tp: x4, thread pointer */
43 unsigned long t0; /* t0: x5, temporary register 0 */
44 unsigned long t1; /* t1: x6, temporary register 1 */
45 unsigned long t2; /* t2: x7, temporary register 2 */
46 unsigned long a0; /* a0: x10, return value or function argument 0 */
47 unsigned long a1; /* a1: x11, return value or function argument 1 */
48 unsigned long a2; /* a2: x12, function argument 2 */
49 unsigned long a3; /* a3: x13, function argument 3 */
50 unsigned long a4; /* a4: x14, function argument 4 */
51 unsigned long a5; /* a5: x15, function argument 5 */
52 unsigned long cause; /* cause: machine/supervisor mode cause csr register */
53 unsigned long epc; /* epc: machine/ supervisor mode exception program counter csr register */
54 unsigned long msubm; /* msubm: machine sub-mode csr register, nuclei customized, exclusive to machine mode */
55#ifndef __riscv_32e
56 unsigned long a6; /* a6: x16, function argument 6 */
57 unsigned long a7; /* a7: x17, function argument 7 */
58 unsigned long t3; /* t3: x28, temporary register 3 */
59 unsigned long t4; /* t4: x29, temporary register 4 */
60 unsigned long t5; /* t5: x30, temporary register 5 */
61 unsigned long t6; /* t6: x31, temporary register 6 */
62#endif
63} EXC_Frame_Type;
64
65/**
66 * \brief Setup the microcontroller system.
67 * \details
68 * Initialize the System and update the SystemCoreClock variable.
69 */
70extern void SystemInit(void);
71
72/**
73 * \brief Update SystemCoreClock variable.
74 * \details
75 * Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
76 */
77extern void SystemCoreClockUpdate(void);
78
79/**
80 * \brief Dump Exception Frame
81 */
82void Exception_DumpFrame(unsigned long sp, uint8_t mode);
83
84/**
85 * \brief Register a m-mode exception handler for exception code EXCn
86 */
87extern void Exception_Register_EXC(uint32_t EXCn, unsigned long exc_handler);
88
89/**
90 * \brief Get current m-mode exception handler for exception code EXCn
91 */
92extern unsigned long Exception_Get_EXC(uint32_t EXCn);
93
94/**
95 * \brief Initialize Interrupt as Clint interrupt mode
96 */
97extern void CLINT_Interrupt_Init(void);
98
99/**
100 * \brief Initialize Interrupt
101 */
102extern void Interrupt_Init(void);
103
104#if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1)
105/**
106 * \brief Do ECLIC Interrupt configuration
107 */
108extern void ECLIC_Interrupt_Init(void);
109
110/**
111 * \brief Initialize a specific IRQ and register the handler
112 * \details
113 * This function set vector mode, trigger mode and polarity, interrupt level and priority,
114 * assign handler for specific IRQn.
115 */
116extern int32_t ECLIC_Register_IRQ(IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void* handler);
117
118#if defined(__TEE_PRESENT) && (__TEE_PRESENT == 1)
119/**
120 * \brief Initialize a specific IRQ and register the handler of supervisor mode
121 * \details
122 * This function set vector mode, trigger mode and polarity, interrupt level and priority,
123 * assign handler for specific IRQn.
124 */
125extern int32_t ECLIC_Register_IRQ_S(IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void* handler);
126#endif
127
128#endif
129
130/**
131 * \brief Register a m-mode core interrupt handler for clint/plic interrupt mode
132 */
133extern void Interrupt_Register_CoreIRQ(uint32_t irqn, unsigned long int_handler);
134
135/**
136 * \brief Register a m-mode plic external interrupt handler for clint/plic interrupt mode
137 */
138extern void Interrupt_Register_ExtIRQ(uint32_t irqn, unsigned long int_handler);
139
140/**
141 * \brief Get a m-mode core interrupt handler for core interrupt number
142 */
143extern unsigned long Interrupt_Get_CoreIRQ(uint32_t irqn);
144
145/**
146 * \brief Get a m-mode external interrupt handler for external interrupt number
147 */
148extern unsigned long Interrupt_Get_ExtIRQ(uint32_t irqn);
149
150/**
151 * \brief Register a m-mode riscv core interrupt and register the handler for clint/plic interrupt mode
152 */
153extern int32_t Core_Register_IRQ(uint32_t irqn, void *handler);
154
155#if defined(__PLIC_PRESENT) && (__PLIC_PRESENT == 1)
156/**
157 * \brief Do plic interrupt configuration for clint/plic interrupt mode
158 */
159extern void PLIC_Interrupt_Init(void);
160/**
161 * \brief Register a m-mode specific plic interrupt and register the handler
162 */
163extern int32_t PLIC_Register_IRQ(uint32_t source, uint8_t priority, void *handler);
164#if defined(__SMODE_PRESENT) && (__SMODE_PRESENT == 1)
165/**
166 * \brief Register a s-mode specific plic interrupt and register the handler
167 */
168extern int32_t PLIC_Register_IRQ_S(uint32_t source, uint8_t priority, void *handler);
169#endif
170#endif
171
172#if defined(__SMODE_PRESENT) && (__SMODE_PRESENT == 1)
173/**
174 * \brief Register a s-mode exception handler for exception code EXCn
175 */
176extern void Exception_Register_EXC_S(uint32_t EXCn, unsigned long exc_handler);
177
178/**
179 * \brief Get current s-mode exception handler for exception code EXCn
180 */
181extern unsigned long Exception_Get_EXC_S(uint32_t EXCn);
182
183/**
184 * \brief Register a s-mode core interrupt handler for clint/plic interrupt mode
185 */
186extern void Interrupt_Register_CoreIRQ_S(uint32_t irqn, unsigned long int_handler);
187
188/**
189 * \brief Register a s-mode plic external interrupt handler for clint/plic interrupt mode
190 */
191extern void Interrupt_Register_ExtIRQ_S(uint32_t irqn, unsigned long int_handler);
192
193/**
194 * \brief Get a s-mode core interrupt handler for core interrupt number
195 */
196extern unsigned long Interrupt_Get_CoreIRQ_S(uint32_t irqn);
197
198/**
199 * \brief Get a s-mode external interrupt handler for external interrupt number
200 */
201extern unsigned long Interrupt_Get_ExtIRQ_S(uint32_t irqn);
202
203/**
204 * \brief Register a s-mode riscv core interrupt and register the handler for clint/plic interrupt mode
205 */
206extern int32_t Core_Register_IRQ_S(uint32_t irqn, void *handler);
207#endif
208
209
210#ifdef __cplusplus
211}
212#endif
213
214#endif /* __SYSTEM_<Device>_H__ */