PMP Functions

Click Nuclei PMP Unit to learn about Core PMP Unit in Nuclei ISA Spec.

__STATIC_INLINE rv_csr_t __get_PMPCFGx (uint32_t csr_idx)
__STATIC_INLINE void __set_PMPCFGx (uint32_t csr_idx, rv_csr_t pmpcfg)
__STATIC_INLINE uint8_t __get_PMPxCFG (uint32_t entry_idx)
__STATIC_INLINE void __set_PMPxCFG (uint32_t entry_idx, uint8_t pmpxcfg)
__STATIC_INLINE rv_csr_t __get_PMPADDRx (uint32_t csr_idx)
__STATIC_INLINE void __set_PMPADDRx (uint32_t csr_idx, rv_csr_t pmpaddr)
__STATIC_INLINE void __set_PMPENTRYx (uint32_t entry_idx, const pmp_config *pmp_cfg)
__STATIC_INLINE int __get_PMPENTRYx (unsigned int entry_idx, pmp_config *pmp_cfg)
PMPCFG_LIST_RV32_0_7     X(0) X(1) X(2) X(3) X(4) X(5) X(6) X(7)
PMPCFG_LIST_RV32_8_15     X(8) X(9) X(10) X(11) X(12) X(13) X(14) X(15)
PMPCFG_LIST_RV64_0_6     X(0) X(2) X(4) X(6)
PMPCFG_LIST_RV64_8_14     X(8) X(10) X(12) X(14)
PMPCFG_LIST PMPCFG_LIST_RV32_0_7
PMPADDR_LIST_BASE     X(0) X(1) X(2) X(3) X(4) X(5) X(6) X(7)
PMPADDR_LIST_8_15     X(8) X(9) X(10) X(11) X(12) X(13) X(14) X(15)
PMPADDR_LIST_16_31
PMPADDR_LIST_32_63
PMPADDR_LIST PMPADDR_LIST_BASE PMPADDR_LIST_8_15
struct pmp_config
group PMP Functions

Functions that related to the RISCV Phyiscal Memory Protection.

Optional physical memory protection (PMP) unit provides per-hart machine-mode control registers to allow physical memory access privileges (read, write, execute) to be specified for each physical memory region.

The PMP can supports region access control settings as small as four bytes.

Defines

PMPCFG_LIST_RV32_0_7     X(0) X(1) X(2) X(3) X(4) X(5) X(6) X(7)

PMPCFG list for RV32 (indices 0-7)

For RV32, each PMPCFG register holds 4 PMP entries. This list covers the first 32 entries (registers 0-7).

PMPCFG_LIST_RV32_8_15     X(8) X(9) X(10) X(11) X(12) X(13) X(14) X(15)

PMPCFG list for RV32 (indices 8-15)

For RV32, each PMPCFG register holds 4 PMP entries. This list covers entries 33-64 (registers 8-15).

PMPCFG_LIST_RV64_0_6     X(0) X(2) X(4) X(6)

PMPCFG list for RV64 (even indices 0-6)

For RV64, each PMPCFG register holds 8 PMP entries. This list covers the first 32 entries (registers 0,2,4,6).

PMPCFG_LIST_RV64_8_14     X(8) X(10) X(12) X(14)

PMPCFG list for RV64 (even indices 8-14)

For RV64, each PMPCFG register holds 8 PMP entries. This list covers entries 33-64 (registers 8,10,12,14).

PMPCFG_LIST PMPCFG_LIST_RV32_0_7

Select appropriate PMPCFG list based on architecture and PMP entry count.

This macro defines the complete PMPCFG list according to:

  • RISC-V architecture (RV32/RV64)

  • Number of PMP entries (__PMP_ENTRY_NUM)

Note

Valid indices depend on configuration:

  • RV32:

    • <=32 entries: indices 0-7

    • <=64 entries: indices 0-15

  • RV64:

    • <=32 entries: indices 0,2,4,6

    • <=64 entries: indices 0,2,4,6,8,10,12,14

PMPADDR_LIST_BASE     X(0) X(1) X(2) X(3) X(4) X(5) X(6) X(7)

Base PMPADDR list (indices 0-7)

PMPADDR_LIST_8_15     X(8) X(9) X(10) X(11) X(12) X(13) X(14) X(15)

Extended PMPADDR list (indices 8-15)

PMPADDR_LIST_16_31

Extended PMPADDR list (indices 16-31)

PMPADDR_LIST_32_63

Extended PMPADDR list (indices 32-63)

PMPADDR_LIST PMPADDR_LIST_BASE PMPADDR_LIST_8_15

Select appropriate PMPADDR list based on PMP_ENTRY_NUM.

This macro defines the complete PMPADDR list by combining base and extended lists according to the configured number of PMP entries.

Note

The actual list is determined by the __PMP_ENTRY_NUM configuration:

  • <=8: Only base list (0-7)

  • <=16: Base + 8-15

  • <=32: Base + 8-15 + 16-31

  • <=64: Base + 8-15 + 16-31 + 32-63

Functions

__STATIC_INLINE rv_csr_t __get_PMPCFGx (uint32_t csr_idx)

Get PMPCFGx Register by CSR index.

Return the content of the PMPCFGx Register.

Remark

The function returns 0 for invalid indices to prevent illegal accesses.

Note

Architecture-specific behavior:

  • RV32:

    • Each register holds 4 PMP entries

    • Valid indices: 0 to ceil(__PMP_ENTRY_NUM/4)-1

    • 64 entries require indices 0-15

  • RV64:

    • Each register holds 8 PMP entries

    • Only even indices are valid

    • 64 entries require indices 0,2,4,6,8,10,12,14

Parameters:

csr_idx – [in] PMPCFG CSR index (0-15 for RV32, 0,2,4,6,8,10,12,14 for RV64)

Returns:

PMPCFGx Register value

__STATIC_INLINE void __set_PMPCFGx (uint32_t csr_idx, rv_csr_t pmpcfg)

Set PMPCFGx by CSR index.

Write the given value to the PMPCFGx Register.

Remark

The function does nothing for invalid indices to prevent illegal accesses.

Note

Architecture-specific behavior:

  • RV32:

    • Each register holds 4 PMP entries

    • Valid indices: 0 to ceil(__PMP_ENTRY_NUM/4)-1

    • 64 entries require indices 0-15

  • RV64:

    • Each register holds 8 PMP entries

    • Only even indices are valid

    • 64 entries require indices 0,2,4,6,8,10,12,14

Parameters:

  • csr_idx – [in] PMPCFG CSR index (0-15 for RV32, 0,2,4,6,8,10,12,14 for RV64)

  • pmpcfg – [in] PMPCFGx Register value to set

__STATIC_INLINE uint8_t __get_PMPxCFG (uint32_t entry_idx)

Get 8bit PMPxCFG Register by PMP entry index.

Return the content of the PMPxCFG Register.

Parameters:

entry_idx – [in] PMP region index(0-63)

Returns:

PMPxCFG Register value

__STATIC_INLINE void __set_PMPxCFG (uint32_t entry_idx, uint8_t pmpxcfg)

Set 8bit PMPxCFG by pmp entry index.

Set the given pmpxcfg value to the PMPxCFG Register.

Remark

  • For RV32, 4 pmpxcfgs are densely packed into one CSR in order For RV64, 8 pmpxcfgs are densely packed into one CSR in order

Parameters:

  • entry_idx – [in] PMPx region index(0-63)

  • pmpxcfg – [in] PMPxCFG register value to set

__STATIC_INLINE rv_csr_t __get_PMPADDRx (uint32_t csr_idx)

Get PMPADDRx Register by CSR index.

Return the content of the PMPADDRx Register.

Parameters:

csr_idx – [in] PMP region CSR index(0-63)

Returns:

PMPADDRx Register value

__STATIC_INLINE void __set_PMPADDRx (uint32_t csr_idx, rv_csr_t pmpaddr)

Set PMPADDRx by CSR index.

Write the given value to the PMPADDRx Register.

Parameters:

  • csr_idx – [in] PMP region CSR index(0-63)

  • pmpaddr – [in] PMPADDRx Register value to set

__STATIC_INLINE void __set_PMPENTRYx (uint32_t entry_idx, const pmp_config *pmp_cfg)

Set PMP entry by entry idx.

Write the given value to the PMPxCFG Register and PMPADDRx.

Remark

  • If the size of memory region is 2^12(4KB) range, pmp_cfg->order makes 12, and the like.

  • Suppose the size of memory region is 2^X bytes range, if X >=3, the NA4 mode is not selectable, NAPOT is selected.

  • TOR of A field in PMP configuration register is not considered here.

Parameters:

  • entry_idx – [in] PMP entry index(0-63)

  • pmp_cfg – [in] structure of L, X, W, R field of PMP configuration register, memory region base address and size of memory region as power of 2

__STATIC_INLINE int __get_PMPENTRYx (unsigned int entry_idx, pmp_config *pmp_cfg)

Get PMP entry by entry idx.

Write the given value to the PMPxCFG Register and PMPADDRx.

Remark

  • If the size of memory region is 2^12(4KB) range, pmp_cfg->order makes 12, and the like.

  • TOR of A field in PMP configuration register is not considered here.

Parameters:

  • entry_idx – [in] PMP entry index(0-63)

  • pmp_cfg – [out] structure of L, X, W, R, A field of PMP configuration register, memory region base address and size of memory region as power of 2

Returns:

-1 failure, else 0 success

struct pmp_config
#include <core_feature_pmp.h>