Signed 16-bit Multiply 64-bit Add/Subtract Instructions
- __STATIC_FORCEINLINE long long __RV_SMAL (long long a, unsigned long b)
- __STATIC_FORCEINLINE long long __RV_SMALBB (long long t, unsigned long a, unsigned long b)
- __STATIC_FORCEINLINE long long __RV_SMALBT (long long t, unsigned long a, unsigned long b)
- __STATIC_FORCEINLINE long long __RV_SMALTT (long long t, unsigned long a, unsigned long b)
- __STATIC_FORCEINLINE long long __RV_SMALDA (long long t, unsigned long a, unsigned long b)
- __STATIC_FORCEINLINE long long __RV_SMALXDA (long long t, unsigned long a, unsigned long b)
- __STATIC_FORCEINLINE long long __RV_SMALDS (long long t, unsigned long a, unsigned long b)
- __STATIC_FORCEINLINE long long __RV_SMALDRS (long long t, unsigned long a, unsigned long b)
- __STATIC_FORCEINLINE long long __RV_SMALXDS (long long t, unsigned long a, unsigned long b)
- __STATIC_FORCEINLINE long long __RV_SMSLDA (long long t, unsigned long a, unsigned long b)
- __STATIC_FORCEINLINE long long __RV_SMSLXDA (long long t, unsigned long a, unsigned long b)
- group NMSIS_Core_DSP_Intrinsic_SIGNED_16B_MULT_64B_ADDSUB
Signed 16-bit Multiply 64-bit Add/Subtract Instructions.
Signed 16-bit Multiply with 64-bit Add/Subtract Instructions.
there is Signed 16-bit Multiply 64-bit Add/Subtract Instructions
there are 10 Signed 16-bit Multiply with 64-bit Add/Subtract Instructions
Functions
- __STATIC_FORCEINLINE long long __RV_SMAL (long long a, unsigned long b)
SMAL (Signed Multiply Halfs & Add 64-bit)
Type: Partial-SIMD
Syntax:
SMAL Rd, Rs1, Rs2
Purpose
:
Multiply the signed bottom 16-bit content of the 32-bit elements of a register with the top 16-bit content of the same 32-bit elements of the same register, and add the results with a 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back to another even/odd pair of registers (RV32) or a register (RV64).
RV32 Description
:
This instruction multiplies the bottom 16-bit content of the lower 32-bit of Rs2 with the top 16-bit content of the lower 32-bit of Rs2 and adds the result with the 64-bit value of an even/odd pair of registers specified by Rs1(4,1). The 64-bit addition result is written back to an even/odd pair of registers specified by Rd(4,1). The 16-bit values of Rs2, and the 64-bit value of the Rs1(4,1) register- pair are treated as signed integers. Rx(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd
2d+1
register of the pair contains the high 32-bit of the operand and the even2d
register of the pair contains the low 32-bit of the operand.RV64 Description
:
This instruction multiplies the bottom 16-bit content of the 32-bit elements of Rs2 with the top 16-bit content of the same 32-bit elements of Rs2 and adds the results with the 64-bit value of Rs1. The 64- bit addition result is written back to Rd. The 16-bit values of Rs2, and the 64-bit value of Rs1 are treated as signed integers.
Operations:
RV32: Mres[31:0] = Rs2.H[1] * Rs2.H[0]; Idx0 = CONCAT(Rs1(4,1),1'b0); Idx1 = CONCAT(Rs1(4,1),1'b1); + Idx2 = CONCAT(Rd(4,1),1'b0); Idx3 = CONCAT(Rd(4,1),1'b1); R[Idx3].R[Idx2] = R[Idx1].R[Idx0] + SE64(Mres[31:0]); RV64: Mres[0][31:0] = Rs2.W[0].H[1] * Rs2.W[0].H[0]; Mres[1][31:0] = Rs2.W[1].H[1] * Rs2.W[1].H[0]; Rd = Rs1 + SE64(Mres[1][31:0]) + SE64(Mres[0][31:0]);
- Parameters
a – [in] long long type of value stored in a
b – [in] unsigned long type of value stored in b
- Returns
value stored in long long type
- __STATIC_FORCEINLINE long long __RV_SMALBB (long long t, unsigned long a, unsigned long b)
SMALBB (Signed Multiply Bottom Halfs & Add 64-bit)
Type: DSP (64-bit Profile)
Syntax:
SMALBB Rd, Rs1, Rs2 SMALBT Rd, Rs1, Rs2 SMALTT Rd, Rs1, Rs2
Purpose
:
Multiply the signed 16-bit content of the 32-bit elements of a register with the 16-bit content of the corresponding 32-bit elements of another register and add the results with a 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back to the register-pair (RV32) or the register (RV64).
SMALBB: rt pair + bottom*bottom (all 32-bit elements)
SMALBT rt pair + bottom*top (all 32-bit elements)
SMALTT rt pair + top*top (all 32-bit elements)
RV32 Description
:
For the
SMALBB
instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2. For theSMALBT
instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2. For theSMALTT
instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2. The multiplication result is added with the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers. Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd2d+1
register of the pair contains the high 32-bit of the operand and the even2d
register of the pair contains the low 32-bit of the operand.RV64 Description
:
For the
SMALBB
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. For theSMALBT
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. For theSMALTT
instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. The multiplication results are added with the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.Operations:
RV32: Mres[31:0] = Rs1.H[0] * Rs2.H[0]; // SMALBB Mres[31:0] = Rs1.H[0] * Rs2.H[1]; // SMALBT Mres[31:0] = Rs1.H[1] * Rs2.H[1]; // SMALTT Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]); RV64: // SMALBB Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[0]; Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[0]; // SMALBT Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[1]; Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[1]; // SMALTT Mres[0][31:0] = Rs1.W[0].H[1] * Rs2.W[0].H[1]; Mres[1][31:0] = Rs1.W[1].H[1] * Rs2.W[1].H[1]; Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]);
- Parameters
t – [in] long long type of value stored in t
a – [in] unsigned long type of value stored in a
b – [in] unsigned long type of value stored in b
- Returns
value stored in long long type
- __STATIC_FORCEINLINE long long __RV_SMALBT (long long t, unsigned long a, unsigned long b)
SMALBT (Signed Multiply Bottom Half & Top Half & Add 64-bit)
Type: DSP (64-bit Profile)
Syntax:
SMALBB Rd, Rs1, Rs2 SMALBT Rd, Rs1, Rs2 SMALTT Rd, Rs1, Rs2
Purpose
:
Multiply the signed 16-bit content of the 32-bit elements of a register with the 16-bit content of the corresponding 32-bit elements of another register and add the results with a 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back to the register-pair (RV32) or the register (RV64).
SMALBB: rt pair + bottom*bottom (all 32-bit elements)
SMALBT rt pair + bottom*top (all 32-bit elements)
SMALTT rt pair + top*top (all 32-bit elements)
RV32 Description
:
For the
SMALBB
instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2. For theSMALBT
instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2. For theSMALTT
instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2. The multiplication result is added with the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers. Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd2d+1
register of the pair contains the high 32-bit of the operand and the even2d
register of the pair contains the low 32-bit of the operand.RV64 Description
:
For the
SMALBB
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. For theSMALBT
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. For theSMALTT
instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. The multiplication results are added with the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.Operations:
RV32: Mres[31:0] = Rs1.H[0] * Rs2.H[0]; // SMALBB Mres[31:0] = Rs1.H[0] * Rs2.H[1]; // SMALBT Mres[31:0] = Rs1.H[1] * Rs2.H[1]; // SMALTT Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]); RV64: // SMALBB Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[0]; Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[0]; // SMALBT Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[1]; Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[1]; // SMALTT Mres[0][31:0] = Rs1.W[0].H[1] * Rs2.W[0].H[1]; Mres[1][31:0] = Rs1.W[1].H[1] * Rs2.W[1].H[1]; Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]);
- Parameters
t – [in] long long type of value stored in t
a – [in] unsigned long type of value stored in a
b – [in] unsigned long type of value stored in b
- Returns
value stored in long long type
- __STATIC_FORCEINLINE long long __RV_SMALTT (long long t, unsigned long a, unsigned long b)
SMALTT (Signed Multiply Top Halfs & Add 64-bit)
Type: DSP (64-bit Profile)
Syntax:
SMALBB Rd, Rs1, Rs2 SMALBT Rd, Rs1, Rs2 SMALTT Rd, Rs1, Rs2
Purpose
:
Multiply the signed 16-bit content of the 32-bit elements of a register with the 16-bit content of the corresponding 32-bit elements of another register and add the results with a 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back to the register-pair (RV32) or the register (RV64).
SMALBB: rt pair + bottom*bottom (all 32-bit elements)
SMALBT rt pair + bottom*top (all 32-bit elements)
SMALTT rt pair + top*top (all 32-bit elements)
RV32 Description
:
For the
SMALBB
instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2. For theSMALBT
instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2. For theSMALTT
instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2. The multiplication result is added with the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers. Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd2d+1
register of the pair contains the high 32-bit of the operand and the even2d
register of the pair contains the low 32-bit of the operand.RV64 Description
:
For the
SMALBB
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. For theSMALBT
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. For theSMALTT
instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. The multiplication results are added with the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.Operations:
RV32: Mres[31:0] = Rs1.H[0] * Rs2.H[0]; // SMALBB Mres[31:0] = Rs1.H[0] * Rs2.H[1]; // SMALBT Mres[31:0] = Rs1.H[1] * Rs2.H[1]; // SMALTT Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]); RV64: // SMALBB Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[0]; Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[0]; // SMALBT Mres[0][31:0] = Rs1.W[0].H[0] * Rs2.W[0].H[1]; Mres[1][31:0] = Rs1.W[1].H[0] * Rs2.W[1].H[1]; // SMALTT Mres[0][31:0] = Rs1.W[0].H[1] * Rs2.W[0].H[1]; Mres[1][31:0] = Rs1.W[1].H[1] * Rs2.W[1].H[1]; Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]);
- Parameters
t – [in] long long type of value stored in t
a – [in] unsigned long type of value stored in a
b – [in] unsigned long type of value stored in b
- Returns
value stored in long long type
- __STATIC_FORCEINLINE long long __RV_SMALDA (long long t, unsigned long a, unsigned long b)
SMALDA (Signed Multiply Two Halfs and Two Adds 64-bit)
Type: DSP (64-bit Profile)
Syntax:
SMALDA Rd, Rs1, Rs2 SMALXDA Rd, Rs1, Rs2
Purpose
:
Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then adds the two 32-bit results and the 64-bit value of an even/odd pair of registers together.
SMALDA: rt pair+ top*top + bottom*bottom (all 32-bit elements)
SMALXDA: rt pair+ top*bottom + bottom*top (all 32-bit elements)
RV32 Description
:
For the
SMALDA
instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2 and then adds the result to the result of multiplying the top 16-bit content of Rs1 with the top 16-bit content of Rs2 with unlimited precision. For theSMALXDA
instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit content of Rs2 and then adds the result to the result of multiplying the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2 with unlimited precision. The result is added to the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64- bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64- bit value of the register-pair are treated as signed integers. Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd2d+1
register of the pair contains the high 32-bit of the operand and the even2d
register of the pair contains the low 32-bit of the operand.RV64 Description
:
For the
SMALDA
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32- bit elements of Rs2 with unlimited precision. For theSMALXDA
instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2 with unlimited precision. The results are added to the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.Operations:
RV32: // SMALDA Mres0[31:0] = (Rs1.H[0] * Rs2.H[0]); Mres1[31:0] = (Rs1.H[1] * Rs2.H[1]); // SMALXDA Mres0[31:0] = (Rs1.H[0] * Rs2.H[1]); Mres1[31:0] = (Rs1.H[1] * Rs2.H[0]); Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres0[31:0]) + SE64(Mres1[31:0]); RV64: // SMALDA Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]); Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]); Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[0]); Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[1]); // SMALXDA Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[1]); Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]); Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[1]); Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[0]); Rd = Rd + SE64(Mres0[0][31:0]) + SE64(Mres1[0][31:0]) + SE64(Mres0[1][31:0]) + SE64(Mres1[1][31:0]);
- Parameters
t – [in] long long type of value stored in t
a – [in] unsigned long type of value stored in a
b – [in] unsigned long type of value stored in b
- Returns
value stored in long long type
- __STATIC_FORCEINLINE long long __RV_SMALXDA (long long t, unsigned long a, unsigned long b)
SMALXDA (Signed Crossed Multiply Two Halfs and Two Adds 64-bit)
Type: DSP (64-bit Profile)
Syntax:
SMALDA Rd, Rs1, Rs2 SMALXDA Rd, Rs1, Rs2
Purpose
:
Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then adds the two 32-bit results and the 64-bit value of an even/odd pair of registers together.
SMALDA: rt pair+ top*top + bottom*bottom (all 32-bit elements)
SMALXDA: rt pair+ top*bottom + bottom*top (all 32-bit elements)
RV32 Description
:
For the
SMALDA
instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2 and then adds the result to the result of multiplying the top 16-bit content of Rs1 with the top 16-bit content of Rs2 with unlimited precision. For theSMALXDA
instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit content of Rs2 and then adds the result to the result of multiplying the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2 with unlimited precision. The result is added to the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64- bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64- bit value of the register-pair are treated as signed integers. Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd2d+1
register of the pair contains the high 32-bit of the operand and the even2d
register of the pair contains the low 32-bit of the operand.RV64 Description
:
For the
SMALDA
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32- bit elements of Rs2 with unlimited precision. For theSMALXDA
instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2 with unlimited precision. The results are added to the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.Operations:
RV32: // SMALDA Mres0[31:0] = (Rs1.H[0] * Rs2.H[0]); Mres1[31:0] = (Rs1.H[1] * Rs2.H[1]); // SMALXDA Mres0[31:0] = (Rs1.H[0] * Rs2.H[1]); Mres1[31:0] = (Rs1.H[1] * Rs2.H[0]); Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres0[31:0]) + SE64(Mres1[31:0]); RV64: // SMALDA Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]); Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]); Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[0]); Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[1]); // SMALXDA Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[1]); Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]); Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[1]); Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[0]); Rd = Rd + SE64(Mres0[0][31:0]) + SE64(Mres1[0][31:0]) + SE64(Mres0[1][31:0]) + SE64(Mres1[1][31:0]);
- Parameters
t – [in] long long type of value stored in t
a – [in] unsigned long type of value stored in a
b – [in] unsigned long type of value stored in b
- Returns
value stored in long long type
- __STATIC_FORCEINLINE long long __RV_SMALDS (long long t, unsigned long a, unsigned long b)
SMALDS (Signed Multiply Two Halfs & Subtract & Add 64-bit)
Type: DSP (64-bit Profile)
Syntax:
SMALDS Rd, Rs1, Rs2 SMALDRS Rd, Rs1, Rs2 SMALXDS Rd, Rs1, Rs2
Purpose
:
Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then perform a subtraction operation between the two 32-bit results. Then add the subtraction result to the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back to the register-pair.
SMALDS: rt pair + (top*top - bottom*bottom) (all 32-bit elements)
SMALDRS: rt pair + (bottom*bottom - top*top) (all 32-bit elements)
SMALXDS: rt pair + (top*bottom - bottom*top) (all 32-bit elements)
RV32 Description
:
For the
SMALDS
instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of Rs1 with the top 16-bit content of Rs2. For theSMALDRS
instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2. For theSMALXDS
instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of Rs1 with the bottom 16-bit content of Rs2. The subtraction result is then added to the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers. Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd2d+1
register of the pair contains the high 32-bit of the operand and the even2d
register of the pair contains the low 32-bit of the operand.RV64 Description
:
For the
SMALDS
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. For theSMALDRS
instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. For theSMALXDS
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. The subtraction results are then added to the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.Operations:
* RV32: Mres[31:0] = (Rs1.H[1] * Rs2.H[1]) - (Rs1.H[0] * Rs2.H[0]); // SMALDS Mres[31:0] = (Rs1.H[0] * Rs2.H[0]) - (Rs1.H[1] * Rs2.H[1]); // SMALDRS Mres[31:0] = (Rs1.H[1] * Rs2.H[0]) - (Rs1.H[0] * Rs2.H[1]); // SMALXDS Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]); * RV64: // SMALDS Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]) - (Rs1.W[0].H[0] * Rs2.W[0].H[0]); Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[1]) - (Rs1.W[1].H[0] * Rs2.W[1].H[0]); // SMALDRS Mres[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]) - (Rs1.W[0].H[1] * Rs2.W[0].H[1]); Mres[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[0].H[0]) - (Rs1.W[1].H[1] * Rs2.W[1].H[1]); // SMALXDS Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]) - (Rs1.W[0].H[0] * Rs2.W[0].H[1]); Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[0]) - (Rs1.W[1].H[0] * Rs2.W[1].H[1]); Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]);
- Parameters
t – [in] long long type of value stored in t
a – [in] unsigned long type of value stored in a
b – [in] unsigned long type of value stored in b
- Returns
value stored in long long type
- __STATIC_FORCEINLINE long long __RV_SMALDRS (long long t, unsigned long a, unsigned long b)
SMALDRS (Signed Multiply Two Halfs & Reverse Subtract & Add 64- bit)
Type: DSP (64-bit Profile)
Syntax:
SMALDS Rd, Rs1, Rs2 SMALDRS Rd, Rs1, Rs2 SMALXDS Rd, Rs1, Rs2
Purpose
:
Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then perform a subtraction operation between the two 32-bit results. Then add the subtraction result to the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back to the register-pair.
SMALDS: rt pair + (top*top - bottom*bottom) (all 32-bit elements)
SMALDRS: rt pair + (bottom*bottom - top*top) (all 32-bit elements)
SMALXDS: rt pair + (top*bottom - bottom*top) (all 32-bit elements)
RV32 Description
:
For the
SMALDS
instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of Rs1 with the top 16-bit content of Rs2. For theSMALDRS
instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2. For theSMALXDS
instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of Rs1 with the bottom 16-bit content of Rs2. The subtraction result is then added to the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers. Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd2d+1
register of the pair contains the high 32-bit of the operand and the even2d
register of the pair contains the low 32-bit of the operand.RV64 Description
:
For the
SMALDS
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. For theSMALDRS
instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. For theSMALXDS
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. The subtraction results are then added to the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.Operations:
* RV32: Mres[31:0] = (Rs1.H[1] * Rs2.H[1]) - (Rs1.H[0] * Rs2.H[0]); // SMALDS Mres[31:0] = (Rs1.H[0] * Rs2.H[0]) - (Rs1.H[1] * Rs2.H[1]); // SMALDRS Mres[31:0] = (Rs1.H[1] * Rs2.H[0]) - (Rs1.H[0] * Rs2.H[1]); // SMALXDS Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]); * RV64: // SMALDS Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]) - (Rs1.W[0].H[0] * Rs2.W[0].H[0]); Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[1]) - (Rs1.W[1].H[0] * Rs2.W[1].H[0]); // SMALDRS Mres[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]) - (Rs1.W[0].H[1] * Rs2.W[0].H[1]); Mres[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[0].H[0]) - (Rs1.W[1].H[1] * Rs2.W[1].H[1]); // SMALXDS Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]) - (Rs1.W[0].H[0] * Rs2.W[0].H[1]); Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[0]) - (Rs1.W[1].H[0] * Rs2.W[1].H[1]); Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]);
- Parameters
t – [in] long long type of value stored in t
a – [in] unsigned long type of value stored in a
b – [in] unsigned long type of value stored in b
- Returns
value stored in long long type
- __STATIC_FORCEINLINE long long __RV_SMALXDS (long long t, unsigned long a, unsigned long b)
SMALXDS (Signed Crossed Multiply Two Halfs & Subtract & Add 64- bit)
Type: DSP (64-bit Profile)
Syntax:
SMALDS Rd, Rs1, Rs2 SMALDRS Rd, Rs1, Rs2 SMALXDS Rd, Rs1, Rs2
Purpose
:
Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then perform a subtraction operation between the two 32-bit results. Then add the subtraction result to the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back to the register-pair.
SMALDS: rt pair + (top*top - bottom*bottom) (all 32-bit elements)
SMALDRS: rt pair + (bottom*bottom - top*top) (all 32-bit elements)
SMALXDS: rt pair + (top*bottom - bottom*top) (all 32-bit elements)
RV32 Description
:
For the
SMALDS
instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of Rs1 with the top 16-bit content of Rs2. For theSMALDRS
instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2. For theSMALXDS
instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of Rs1 with the bottom 16-bit content of Rs2. The subtraction result is then added to the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers. Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd2d+1
register of the pair contains the high 32-bit of the operand and the even2d
register of the pair contains the low 32-bit of the operand.RV64 Description
:
For the
SMALDS
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. For theSMALDRS
instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. For theSMALXDS
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. The subtraction results are then added to the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.Operations:
* RV32: Mres[31:0] = (Rs1.H[1] * Rs2.H[1]) - (Rs1.H[0] * Rs2.H[0]); // SMALDS Mres[31:0] = (Rs1.H[0] * Rs2.H[0]) - (Rs1.H[1] * Rs2.H[1]); // SMALDRS Mres[31:0] = (Rs1.H[1] * Rs2.H[0]) - (Rs1.H[0] * Rs2.H[1]); // SMALXDS Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); R[Idx1].R[Idx0] = R[Idx1].R[Idx0] + SE64(Mres[31:0]); * RV64: // SMALDS Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]) - (Rs1.W[0].H[0] * Rs2.W[0].H[0]); Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[1]) - (Rs1.W[1].H[0] * Rs2.W[1].H[0]); // SMALDRS Mres[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]) - (Rs1.W[0].H[1] * Rs2.W[0].H[1]); Mres[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[0].H[0]) - (Rs1.W[1].H[1] * Rs2.W[1].H[1]); // SMALXDS Mres[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]) - (Rs1.W[0].H[0] * Rs2.W[0].H[1]); Mres[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[0].H[0]) - (Rs1.W[1].H[0] * Rs2.W[1].H[1]); Rd = Rd + SE64(Mres[0][31:0]) + SE64(Mres[1][31:0]);
- Parameters
t – [in] long long type of value stored in t
a – [in] unsigned long type of value stored in a
b – [in] unsigned long type of value stored in b
- Returns
value stored in long long type
- __STATIC_FORCEINLINE long long __RV_SMSLDA (long long t, unsigned long a, unsigned long b)
SMSLDA (Signed Multiply Two Halfs & Add & Subtract 64-bit)
Type: DSP (64-bit Profile)
Syntax:
SMSLDA Rd, Rs1, Rs2 SMSLXDA Rd, Rs1, Rs2
Purpose
:
Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then subtracts the two 32-bit results from the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The subtraction result is written back to the register-pair.
SMSLDA: rd pair - top*top - bottom*bottom (all 32-bit elements)
SMSLXDA: rd pair - top*bottom - bottom*top (all 32-bit elements)
RV32 Description
:
For the
SMSLDA
instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit content Rs2 and multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2. For theSMSLXDA
instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit content of Rs2 and multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2. The two multiplication results are subtracted from the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64-bit subtraction result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers. Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd2d+1
register of the pair contains the high 32-bit of the result and the even2d
register of the pair contains the low 32-bit of the result.RV64 Description
:
For the
SMSLDA
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. For theSMSLXDA
instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. The four multiplication results are subtracted from the 64-bit value of Rd. The 64-bit subtraction result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.Operations:
* RV32: // SMSLDA Mres0[31:0] = (Rs1.H[0] * Rs2.H[0]); Mres1[31:0] = (Rs1.H[1] * Rs2.H[1]); // SMSLXDA Mres0[31:0] = (Rs1.H[0] * Rs2.H[1]); Mres1[31:0] = (Rs1.H[1] * Rs2.H[0]); Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); R[Idx1].R[Idx0] = R[Idx1].R[Idx0] - SE64(Mres0[31:0]) - SE64(Mres1[31:0]); * RV64: // SMSLDA Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]); Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]); Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[0]); Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[1]); // SMSLXDA Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[1]); Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]); Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[1]); Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[0]); Rd = Rd - SE64(Mres0[0][31:0]) - SE64(Mres1[0][31:0]) - SE64(Mres0[1][31:0]) - SE64(Mres1[1][31:0]);
- Parameters
t – [in] long long type of value stored in t
a – [in] unsigned long type of value stored in a
b – [in] unsigned long type of value stored in b
- Returns
value stored in long long type
- __STATIC_FORCEINLINE long long __RV_SMSLXDA (long long t, unsigned long a, unsigned long b)
SMSLXDA (Signed Crossed Multiply Two Halfs & Add & Subtract 64- bit)
Type: DSP (64-bit Profile)
Syntax:
SMSLDA Rd, Rs1, Rs2 SMSLXDA Rd, Rs1, Rs2
Purpose
:
Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then subtracts the two 32-bit results from the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The subtraction result is written back to the register-pair.
SMSLDA: rd pair - top*top - bottom*bottom (all 32-bit elements)
SMSLXDA: rd pair - top*bottom - bottom*top (all 32-bit elements)
RV32 Description
:
For the
SMSLDA
instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit content Rs2 and multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2. For theSMSLXDA
instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit content of Rs2 and multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2. The two multiplication results are subtracted from the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64-bit subtraction result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers. Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd2d+1
register of the pair contains the high 32-bit of the result and the even2d
register of the pair contains the low 32-bit of the result.RV64 Description
:
For the
SMSLDA
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. For theSMSLXDA
instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. The four multiplication results are subtracted from the 64-bit value of Rd. The 64-bit subtraction result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.Operations:
* RV32: // SMSLDA Mres0[31:0] = (Rs1.H[0] * Rs2.H[0]); Mres1[31:0] = (Rs1.H[1] * Rs2.H[1]); // SMSLXDA Mres0[31:0] = (Rs1.H[0] * Rs2.H[1]); Mres1[31:0] = (Rs1.H[1] * Rs2.H[0]); Idx0 = CONCAT(Rd(4,1),1'b0); Idx1 = CONCAT(Rd(4,1),1'b1); R[Idx1].R[Idx0] = R[Idx1].R[Idx0] - SE64(Mres0[31:0]) - SE64(Mres1[31:0]); * RV64: // SMSLDA Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[0]); Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[1]); Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[0]); Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[1]); // SMSLXDA Mres0[0][31:0] = (Rs1.W[0].H[0] * Rs2.W[0].H[1]); Mres1[0][31:0] = (Rs1.W[0].H[1] * Rs2.W[0].H[0]); Mres0[1][31:0] = (Rs1.W[1].H[0] * Rs2.W[1].H[1]); Mres1[1][31:0] = (Rs1.W[1].H[1] * Rs2.W[1].H[0]); Rd = Rd - SE64(Mres0[0][31:0]) - SE64(Mres1[0][31:0]) - SE64(Mres0[1][31:0]) - SE64(Mres1[1][31:0]);
- Parameters
t – [in] long long type of value stored in t
a – [in] unsigned long type of value stored in a
b – [in] unsigned long type of value stored in b
- Returns
value stored in long long type