NMSIS-Core  Version 1.2.0
NMSIS-Core support for Nuclei processor-based devices
System Device Configuration

Functions for system and clock setup available in system_<device>.c. More...

Modules

 Interrupt and Exception and NMI Handling
 Functions for interrupt, exception and nmi handle available in system_<device>.c.
 

Macros

#define FALLBACK_DEFAULT_ECLIC_BASE   0x0C000000UL
 
#define FALLBACK_DEFAULT_SYSTIMER_BASE   0x02000000UL
 
#define CLINT_MSIP(base, hartid)   (*(volatile uint32_t *)((uintptr_t)((base) + ((hartid) * 4))))
 
#define SMP_CTRLREG(base, ofs)   (*(volatile uint32_t *)((uintptr_t)((base) + (ofs))))
 

Typedefs

typedef void(* fnptr) (void)
 

Functions

void default_intexc_handler (void)
 default eclic interrupt or exception interrupt handler More...
 
void SystemCoreClockUpdate (void)
 Function to update the variable SystemCoreClock. More...
 
void SystemInit (void)
 Function to Initialize the system. More...
 
void SystemBannerPrint (void)
 Banner Print for Nuclei SDK. More...
 
void ECLIC_Init (void)
 initialize eclic config More...
 
int32_t ECLIC_Register_IRQ (IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void *handler)
 Initialize a specific IRQ and register the handler. More...
 
int32_t ECLIC_Register_IRQ_S (IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void *handler)
 Initialize a specific IRQ and register the handler for supervisor mode. More...
 
static void _get_iregion_info (IRegion_Info_Type *iregion)
 Get Nuclei Internal Region Information. More...
 
void __sync_harts (void)
 Synchronize all harts. More...
 
static void Trap_Init (void)
 do the init for trap(interrupt and exception) entry for supervisor mode More...
 
void _premain_init (void)
 early init function before main More...
 
void _postmain_fini (int status)
 finish function after main More...
 
void _init (void)
 _init function called in __libc_init_array() More...
 
void _fini (void)
 _fini function called in __libc_fini_array() More...
 

Variables

fnptr irq_entry_s
 default entry for s-mode non-vector irq entry More...
 
fnptr exc_entry_s
 default entry for s-mode exception entry More...
 
volatile uint32_t SystemCoreClock = SYSTEM_CLOCK
 Variable to hold the system core clock value. More...
 
volatile IRegion_Info_Type SystemIRegionInfo
 Nuclei RISC-V CPU IRegion Information Variable used to store probed info. More...
 

Detailed Description

Functions for system and clock setup available in system_<device>.c.

Nuclei provides a template file system_Device.c that must be adapted by the silicon vendor to match their actual device. As a minimum requirement, this file must provide:

The file configures the device and, typically, initializes the oscillator (PLL) that is part of the microcontroller device. This file might export other functions or variables that provide a more flexible configuration of the microcontroller system.

And this file also provided common interrupt, exception and NMI exception handling framework template, Silicon vendor can customize these template code as they want.

Note
Please pay special attention to the static variable SystemCoreClock. This variable might be used throughout the whole system initialization and runtime to calculate frequency/time related values. Thus one must assure that the variable always reflects the actual system clock speed.
Attention
Be aware that a value stored to SystemCoreClock during low level initialization (i.e. SystemInit()) might get overwritten by C libray startup code and/or .bss section initialization. Thus its highly recommended to call SystemCoreClockUpdate at the beginning of the user main() routine.

Macro Definition Documentation

◆ CLINT_MSIP

#define CLINT_MSIP (   base,
  hartid 
)    (*(volatile uint32_t *)((uintptr_t)((base) + ((hartid) * 4))))

Definition at line 681 of file system_Device.c.

◆ FALLBACK_DEFAULT_ECLIC_BASE

#define FALLBACK_DEFAULT_ECLIC_BASE   0x0C000000UL

Definition at line 649 of file system_Device.c.

◆ FALLBACK_DEFAULT_SYSTIMER_BASE

#define FALLBACK_DEFAULT_SYSTIMER_BASE   0x02000000UL

Definition at line 650 of file system_Device.c.

◆ SMP_CTRLREG

#define SMP_CTRLREG (   base,
  ofs 
)    (*(volatile uint32_t *)((uintptr_t)((base) + (ofs))))

Definition at line 682 of file system_Device.c.

Typedef Documentation

◆ fnptr

typedef void(* fnptr) (void)

Definition at line 74 of file system_Device.c.

Function Documentation

◆ __sync_harts()

void __sync_harts ( void  )

Synchronize all harts.

This function is used to synchronize all the harts, especially to wait the boot hart finish initialization of data section, bss section and c runtines initialization This function must be placed in .text.init section, since section initialization is not ready, global variable and static variable should be avoid to use in this function, and avoid to call other functions

Definition at line 684 of file system_Device.c.

697 {
698 // Only do synchronize when SMP_CPU_CNT is defined and number > 0
699 #if defined(SMP_CPU_CNT) && (SMP_CPU_CNT > 1)
700  unsigned long hartid = __get_hart_id();
701  unsigned long tmr_hartid = __get_hart_index();
702  unsigned long clint_base, irgb_base, smp_base;
703  unsigned long mcfg_info;
704 
705  mcfg_info = __RV_CSR_READ(CSR_MCFG_INFO);
706  if (mcfg_info & MCFG_INFO_IREGION_EXIST) { // IRegion Info present
707  // clint base = system timer base + 0x1000
708  irgb_base = (__RV_CSR_READ(CSR_MIRGB_INFO) >> 10) << 10;
709  clint_base = irgb_base + IREGION_TIMER_OFS + 0x1000;
710  smp_base = irgb_base + IREGION_SMP_OFS;
711  } else {
712  clint_base = FALLBACK_DEFAULT_SYSTIMER_BASE + 0x1000;
713  smp_base = (__RV_CSR_READ(CSR_MSMPCFG_INFO) >> 4) << 4;
714  }
715  // Enable SMP and L2, disable cluster local memory
716  SMP_CTRLREG(smp_base, 0xc) = 0xFFFFFFFF;
717  SMP_CTRLREG(smp_base, 0x10) = 0x1;
718  SMP_CTRLREG(smp_base, 0xd8) = 0x0;
719  __SMP_RWMB();
720 
721  // pre-condition: interrupt must be disabled, this is done before calling this function
722  // BOOT_HARTID is defined <Device.h>
723  if (hartid == BOOT_HARTID) { // boot hart
724  // clear msip pending
725  for (int i = 0; i < SMP_CPU_CNT; i ++) {
726  CLINT_MSIP(clint_base, i) = 0;
727  }
728  __SMP_RWMB();
729  } else {
730  // Set machine software interrupt pending to 1
731  CLINT_MSIP(clint_base, tmr_hartid) = 1;
732  __SMP_RWMB();
733  // wait for pending bit cleared by boot hart
734  while (CLINT_MSIP(clint_base, tmr_hartid) == 1);
735  }
736 #endif
737 }

◆ _fini()

void _fini ( void  )

_fini function called in __libc_fini_array()

This __libc_fini_array() function is called when exit main. user need to implement this function, otherwise when link it will error fini.c:(.text.__libc_fini_array+0x28): undefined reference to ‘_fini’

Note
Please use _postmain_fini function now

Definition at line 884 of file system_Device.c.

885 {
886  /* Don't put any code here, please use _postmain_fini now */
887 }

◆ _get_iregion_info()

static void _get_iregion_info ( IRegion_Info_Type *  iregion)
static

Get Nuclei Internal Region Information.

This function is used to get nuclei cpu internal region information, such as iregion base, eclic base, smp base, timer base and idu base, and fallback to old evalsoc timer and eclic base if no iregion feature found

Definition at line 662 of file system_Device.c.

663 {
664  unsigned long mcfg_info;
665  if (iregion == NULL) {
666  return;
667  }
668  mcfg_info = __RV_CSR_READ(CSR_MCFG_INFO);
669  if (mcfg_info & MCFG_INFO_IREGION_EXIST) { // IRegion Info present
670  iregion->iregion_base = (__RV_CSR_READ(CSR_MIRGB_INFO) >> 10) << 10;
671  iregion->eclic_base = iregion->iregion_base + IREGION_ECLIC_OFS;
672  iregion->systimer_base = iregion->iregion_base + IREGION_TIMER_OFS;
673  iregion->smp_base = iregion->iregion_base + IREGION_SMP_OFS;
674  iregion->idu_base = iregion->iregion_base + IREGION_IDU_OFS;
675  } else {
676  iregion->eclic_base = FALLBACK_DEFAULT_ECLIC_BASE;
677  iregion->systimer_base = FALLBACK_DEFAULT_SYSTIMER_BASE;
678  }
679 }

◆ _init()

void _init ( void  )

_init function called in __libc_init_array()

This __libc_init_array() function is called during startup code, user need to implement this function, otherwise when link it will error init.c:(.text.__libc_init_array+0x26): undefined reference to ‘_init’

Note
Please use _premain_init function now

Definition at line 870 of file system_Device.c.

871 {
872  /* Don't put any code here, please use _premain_init now */
873 }

◆ _postmain_fini()

void _postmain_fini ( int  status)

finish function after main

Parameters
[in]statusstatus code return from main

This function is executed right after main function. For RISC-V gnu toolchain, _fini function might not be called by __libc_fini_array function, so we defined a new function to do initialization

Definition at line 854 of file system_Device.c.

855 {
856  /* TODO: Add your own finishing code here, called after main */
857  extern void simulation_exit(int status);
858  simulation_exit(status);
859 }

◆ _premain_init()

void _premain_init ( void  )

early init function before main

This function is executed right before main function. For RISC-V gnu toolchain, _init function might not be called by __libc_init_array function, so we defined a new function to do initialization.

Definition at line 774 of file system_Device.c.

775 {
776  // TODO to make it possible for configurable boot hartid
777  unsigned long hartid = __get_hart_id();
778 
779  // BOOT_HARTID is defined <Device.h>
780  if (hartid == BOOT_HARTID) { // only done in boot hart
781  // IREGION INFO MUST BE SET BEFORE ANY PREMAIN INIT STEPS
782  _get_iregion_info((IRegion_Info_Type *)(&SystemIRegionInfo));
783  }
784  /* TODO: Add your own initialization code here, called before main */
785  // This code located in RUNMODE_CONTROL ifdef endif block just for internal usage
786  // No need to use in your code
787 #ifdef RUNMODE_CONTROL
788 #if defined(RUNMODE_ILM_EN) && RUNMODE_ILM_EN == 0
789  // Only disable ilm when it is present
792  }
793 #endif
794 #if defined(RUNMODE_DLM_EN) && RUNMODE_DLM_EN == 0
795  // Only disable dlm when it is present
798  }
799 #endif
800 #endif
801 
802  /* __ICACHE_PRESENT and __DCACHE_PRESENT are defined in demosoc.h */
803  // For our internal cpu testing, they want to set demosoc __ICACHE_PRESENT/__DCACHE_PRESENT to be 1
804  // __CCM_PRESENT is still default to 0 in demosoc.h, since it is used in core_feature_eclic.h to register interrupt, if set to 1, it might cause exception
805  // but in the cpu, icache or dcache might not exist due to cpu configuration, so here
806  // we need to check whether icache/dcache really exist, if yes, then turn on it
807 #if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1)
808  if (ICachePresent()) { // Check whether icache real present or not
809  EnableICache();
810  }
811 #endif
812 #if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1)
813  if (DCachePresent()) { // Check whether dcache real present or not
814  EnableDCache();
815  }
816 #endif
817 
818  /* Do fence and fence.i to make sure previous ilm/dlm/icache/dcache control done */
819  __RWMB();
820  __FENCE_I();
821 
822  if (hartid == BOOT_HARTID) { // only required for boot hartid
823  // TODO implement get_cpu_freq function to get real cpu clock freq in HZ or directly give the real cpu HZ
824  SystemCoreClock = get_cpu_freq();
825  uart_init(SOC_DEBUG_UART, 115200);
826  /* Display banner after UART initialized */
828  /* Initialize exception default handlers */
829  Exception_Init();
830  /* ECLIC initialization, mainly MTH and NLBIT */
831  ECLIC_Init();
832  Trap_Init();
833  // TODO: internal usage for Nuclei
834 #ifdef RUNMODE_CONTROL
835  printf("Current RUNMODE=%s, ilm:%d, dlm %d, icache %d, dcache %d, ccm %d\n", \
836  RUNMODE_STRING, RUNMODE_ILM_EN, RUNMODE_DLM_EN, \
837  RUNMODE_IC_EN, RUNMODE_DC_EN, RUNMODE_CCM_EN);
838  printf("CSR: MILM_CTL 0x%x, MDLM_CTL 0x%x, MCACHE_CTL 0x%x\n", \
841 #endif
842  }
843 }

◆ default_intexc_handler()

void default_intexc_handler ( void  )

default eclic interrupt or exception interrupt handler

◆ ECLIC_Init()

void ECLIC_Init ( void  )

initialize eclic config

ECLIC needs be initialized after boot up, Vendor could also change the initialization configuration.

Definition at line 553 of file system_Device.c.

554 {
555  /* Global Configuration about MTH and NLBits.
556  * TODO: Please adapt it according to your system requirement.
557  * This function is called in _init function */
558  ECLIC_SetMth(0);
559  ECLIC_SetCfgNlbits(__ECLIC_INTCTLBITS);
560 
561 #if defined(__TEE_PRESENT) && (__TEE_PRESENT == 1)
562  /* Global Configuration about STH */
563  ECLIC_SetSth(0);
564 #endif
565 }

◆ ECLIC_Register_IRQ()

int32_t ECLIC_Register_IRQ ( IRQn_Type  IRQn,
uint8_t  shv,
ECLIC_TRIGGER_Type  trig_mode,
uint8_t  lvl,
uint8_t  priority,
void *  handler 
)

Initialize a specific IRQ and register the handler.

This function set vector mode, trigger mode and polarity, interrupt level and priority, assign handler for specific IRQn.

Parameters
[in]IRQnNMI interrupt handler address
[in]shvECLIC_NON_VECTOR_INTERRUPT means non-vector mode, and ECLIC_VECTOR_INTERRUPT is vector mode
[in]trig_modesee ECLIC_TRIGGER_Type
[in]lvlinterupt level
[in]priorityinterrupt priority
[in]handlerinterrupt handler, if NULL, handler will not be installed
Returns
-1 means invalid input parameter. 0 means successful.
Remarks
  • This function use to configure specific eclic interrupt and register its interrupt handler and enable its interrupt.
  • If the vector table is placed in read-only section(FLASHXIP mode), handler could not be installed

Definition at line 583 of file system_Device.c.

584 {
585  if ((IRQn > SOC_INT_MAX) || (shv > ECLIC_VECTOR_INTERRUPT) \
586  || (trig_mode > ECLIC_NEGTIVE_EDGE_TRIGGER)) {
587  return -1;
588  }
589 
590  /* set interrupt vector mode */
591  ECLIC_SetShvIRQ(IRQn, shv);
592  /* set interrupt trigger mode and polarity */
593  ECLIC_SetTrigIRQ(IRQn, trig_mode);
594  /* set interrupt level */
595  ECLIC_SetLevelIRQ(IRQn, lvl);
596  /* set interrupt priority */
597  ECLIC_SetPriorityIRQ(IRQn, priority);
598  if (handler != NULL) {
599  /* set interrupt handler entry to vector table */
600  ECLIC_SetVector(IRQn, (rv_csr_t)handler);
601  }
602  /* enable interrupt */
604  return 0;
605 }

◆ ECLIC_Register_IRQ_S()

int32_t ECLIC_Register_IRQ_S ( IRQn_Type  IRQn,
uint8_t  shv,
ECLIC_TRIGGER_Type  trig_mode,
uint8_t  lvl,
uint8_t  priority,
void *  handler 
)

Initialize a specific IRQ and register the handler for supervisor mode.

This function set vector mode, trigger mode and polarity, interrupt level and priority, assign handler for specific IRQn.

Parameters
[in]IRQnNMI interrupt handler address
[in]shvECLIC_NON_VECTOR_INTERRUPT means non-vector mode, and ECLIC_VECTOR_INTERRUPT is vector mode
[in]trig_modesee ECLIC_TRIGGER_Type
[in]lvlinterupt level
[in]priorityinterrupt priority
[in]handlerinterrupt handler, if NULL, handler will not be installed
Returns
-1 means invalid input parameter. 0 means successful.
Remarks
  • This function use to configure specific eclic S-mode interrupt and register its interrupt handler and enable its interrupt.
  • If the vector table is placed in read-only section (FLASHXIP mode), handler could not be installed.

Definition at line 624 of file system_Device.c.

625 {
626  if ((IRQn > SOC_INT_MAX) || (shv > ECLIC_VECTOR_INTERRUPT) \
627  || (trig_mode > ECLIC_NEGTIVE_EDGE_TRIGGER)) {
628  return -1;
629  }
630 
631  /* set interrupt vector mode */
632  ECLIC_SetShvIRQ_S(IRQn, shv);
633  /* set interrupt trigger mode and polarity */
634  ECLIC_SetTrigIRQ_S(IRQn, trig_mode);
635  /* set interrupt level */
637  /* set interrupt priority */
638  ECLIC_SetPriorityIRQ_S(IRQn, priority);
639  if (handler != NULL) {
640  /* set interrupt handler entry to vector table */
641  ECLIC_SetVector_S(IRQn, (rv_csr_t)handler);
642  }
643  /* enable interrupt */
645  return 0;
646 }

◆ SystemBannerPrint()

void SystemBannerPrint ( void  )

Banner Print for Nuclei SDK.

Definition at line 534 of file system_Device.c.

535 {
536 #if defined(NUCLEI_BANNER) && (NUCLEI_BANNER == 1)
537  printf("Nuclei SDK Build Time: %s, %s\r\n", __DATE__, __TIME__);
538 #ifdef DOWNLOAD_MODE_STRING
539  printf("Download Mode: %s\r\n", DOWNLOAD_MODE_STRING);
540 #endif
541  printf("CPU Frequency %u Hz\r\n", (unsigned int)SystemCoreClock);
542  printf("CPU HartID: %u\r\n", (unsigned int)__get_hart_id());
543 #endif
544 }

◆ SystemCoreClockUpdate()

void SystemCoreClockUpdate ( void  )

Function to update the variable SystemCoreClock.

Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution. The function evaluates the clock register settings and calculates the current core clock.

Definition at line 231 of file system_Device.c.

232 {
233  /* ToDo: add code to calculate the system frequency based upon the current
234  * register settings.
235  * Note: This function can be used to retrieve the system core clock frequeny
236  * after user changed register settings.
237  */
238  SystemCoreClock = SYSTEM_CLOCK;
239 }

◆ SystemInit()

void SystemInit ( void  )

Function to Initialize the system.

Initializes the microcontroller system. Typically, this function configures the oscillator (PLL) that is part of the microcontroller device. For systems with a variable clock speed, it updates the variable SystemCoreClock. SystemInit is called from the file startup_device.

Definition at line 249 of file system_Device.c.

250 {
251  /* ToDo: add code to initialize the system
252  * Warn: do not use global variables because this function is called before
253  * reaching pre-main. RW section maybe overwritten afterwards.
254  */
255  SystemCoreClock = SYSTEM_CLOCK;
256 }

◆ Trap_Init()

static void Trap_Init ( void  )
static

do the init for trap(interrupt and exception) entry for supervisor mode

This function provide initialization of CSR_STVT CSR_STVT2 and CSR_STVEC.

Definition at line 744 of file system_Device.c.

745 {
746 #if defined(__TEE_PRESENT) && (__TEE_PRESENT == 1)
747  /*
748  * Intialize ECLIC supervisor mode vector interrupt
749  * base address stvt to vector_table_s
750  */
751  __RV_CSR_WRITE(CSR_STVT, (unsigned long)&vector_table_s);
752  /*
753  * Set ECLIC supervisor mode non-vector entry to be controlled
754  * by stvt2 CSR register.
755  * Intialize supervisor mode ECLIC non-vector interrupt
756  * base address stvt2 to irq_entry_s.
757  */
758  __RV_CSR_WRITE(CSR_STVT2, (unsigned long)&irq_entry_s);
759  __RV_CSR_SET(CSR_STVT2, 0x01);
760  /*
761  * Set supervisor exception entry stvec to exc_entry_s */
762  __RV_CSR_WRITE(CSR_STVEC, (unsigned long)&exc_entry_s);
763 #endif
764 }

Variable Documentation

◆ exc_entry_s

fnptr exc_entry_s

default entry for s-mode exception entry

◆ irq_entry_s

fnptr irq_entry_s

default entry for s-mode non-vector irq entry

◆ SystemCoreClock

volatile uint32_t SystemCoreClock = SYSTEM_CLOCK

Variable to hold the system core clock value.

Holds the system core clock, which is the system clock frequency supplied to the SysTick timer and the processor core clock. This variable can be used by debuggers to query the frequency of the debug timer or to configure the trace clock speed.

Attention
Compilers must be configured to avoid removing this variable in case the application program is not using it. Debugging systems require the variable to be physically present in memory so that it can be examined to configure the debugger.

Definition at line 218 of file system_Device.c.

◆ SystemIRegionInfo

volatile IRegion_Info_Type SystemIRegionInfo

Nuclei RISC-V CPU IRegion Information Variable used to store probed info.

Definition at line 653 of file system_Device.c.

IREGION_IDU_OFS
#define IREGION_IDU_OFS
Definition: riscv_encoding.h:303
DCachePresent
__STATIC_FORCEINLINE int32_t DCachePresent(void)
Check DCache Unit Present or Not.
Definition: core_feature_cache.h:699
ECLIC_SetCfgNlbits
#define ECLIC_SetCfgNlbits
Definition: core_feature_eclic.h:242
SystemBannerPrint
void SystemBannerPrint(void)
Banner Print for Nuclei SDK.
Definition: system_Device.c:534
__get_hart_index
__STATIC_FORCEINLINE unsigned long __get_hart_index(void)
Get hart index of current cluster.
Definition: core_feature_base.h:776
_get_iregion_info
static void _get_iregion_info(IRegion_Info_Type *iregion)
Get Nuclei Internal Region Information.
Definition: system_Device.c:662
ECLIC_Init
void ECLIC_Init(void)
initialize eclic config
Definition: system_Device.c:553
CSR_MSMPCFG_INFO
#define CSR_MSMPCFG_INFO
Definition: riscv_encoding.h:956
CSR_MIRGB_INFO
#define CSR_MIRGB_INFO
Definition: riscv_encoding.h:957
ECLIC_NEGTIVE_EDGE_TRIGGER
@ ECLIC_NEGTIVE_EDGE_TRIGGER
Negtive/Falling Edge Triggered, trig[0] = 1, trig[1] = 1.
Definition: core_feature_eclic.h:159
__RV_CSR_CLEAR
#define __RV_CSR_CLEAR(csr, val)
CSR operation Macro for csrc instruction.
Definition: core_feature_base.h:573
MCFG_INFO_DLM
#define MCFG_INFO_DLM
Definition: riscv_encoding.h:253
SystemCoreClock
volatile uint32_t SystemCoreClock
Variable to hold the system core clock value.
Definition: system_Device.c:218
ECLIC_EnableIRQ
#define ECLIC_EnableIRQ
Definition: core_feature_eclic.h:249
ECLIC_SetLevelIRQ
#define ECLIC_SetLevelIRQ
Definition: core_feature_eclic.h:261
ECLIC_SetTrigIRQ
#define ECLIC_SetTrigIRQ
Definition: core_feature_eclic.h:255
IREGION_ECLIC_OFS
#define IREGION_ECLIC_OFS
Definition: riscv_encoding.h:300
ECLIC_SetLevelIRQ_S
#define ECLIC_SetLevelIRQ_S
Definition: core_feature_eclic.h:277
ECLIC_EnableIRQ_S
#define ECLIC_EnableIRQ_S
Definition: core_feature_eclic.h:281
CLINT_MSIP
#define CLINT_MSIP(base, hartid)
Definition: system_Device.c:681
ECLIC_SetShvIRQ_S
#define ECLIC_SetShvIRQ_S
Definition: core_feature_eclic.h:273
CSR_STVT
#define CSR_STVT
Definition: riscv_encoding.h:556
ECLIC_SetVector_S
#define ECLIC_SetVector_S
Definition: core_feature_eclic.h:298
CSR_MCFG_INFO
#define CSR_MCFG_INFO
Definition: riscv_encoding.h:969
IRQn
IRQn
Definition of IRQn numbers.
Definition: core_feature_eclic.h:202
irq_entry_s
fnptr irq_entry_s
default entry for s-mode non-vector irq entry
__RV_CSR_WRITE
#define __RV_CSR_WRITE(csr, val)
CSR operation Macro for csrw instruction.
Definition: core_feature_base.h:499
MCFG_INFO_IREGION_EXIST
#define MCFG_INFO_IREGION_EXIST
Definition: riscv_encoding.h:260
__get_hart_id
__STATIC_FORCEINLINE unsigned long __get_hart_id(void)
Get hart id of current cluster.
Definition: core_feature_base.h:796
SOC_INT_MAX
@ SOC_INT_MAX
Number of total interrupts.
Definition: core_feature_eclic.h:232
__RWMB
#define __RWMB()
Read & Write Memory barrier.
Definition: core_feature_base.h:1481
FALLBACK_DEFAULT_ECLIC_BASE
#define FALLBACK_DEFAULT_ECLIC_BASE
Definition: system_Device.c:649
ECLIC_SetTrigIRQ_S
#define ECLIC_SetTrigIRQ_S
Definition: core_feature_eclic.h:271
exc_entry_s
fnptr exc_entry_s
default entry for s-mode exception entry
EnableDCache
__STATIC_FORCEINLINE void EnableDCache(void)
Enable DCache.
Definition: core_feature_cache.h:717
CSR_MDLM_CTL
#define CSR_MDLM_CTL
Definition: riscv_encoding.h:913
MCFG_INFO_ILM
#define MCFG_INFO_ILM
Definition: riscv_encoding.h:252
CSR_STVT2
#define CSR_STVT2
Definition: riscv_encoding.h:963
FALLBACK_DEFAULT_SYSTIMER_BASE
#define FALLBACK_DEFAULT_SYSTIMER_BASE
Definition: system_Device.c:650
Exception_Init
static void Exception_Init(void)
Initialize all the default core exception handlers.
Definition: system_Device.c:333
MILM_CTL_ILM_EN
#define MILM_CTL_ILM_EN
Definition: riscv_encoding.h:206
ECLIC_SetSth
#define ECLIC_SetSth
Definition: core_feature_eclic.h:269
CSR_MCACHE_CTL
#define CSR_MCACHE_CTL
Definition: riscv_encoding.h:918
__RV_CSR_READ
#define __RV_CSR_READ(csr)
CSR operation Macro for csrr instruction.
Definition: core_feature_base.h:481
CSR_STVEC
#define CSR_STVEC
Definition: riscv_encoding.h:505
Trap_Init
static void Trap_Init(void)
do the init for trap(interrupt and exception) entry for supervisor mode
Definition: system_Device.c:744
ECLIC_SetVector
#define ECLIC_SetVector
Definition: core_feature_eclic.h:294
ECLIC_SetPriorityIRQ
#define ECLIC_SetPriorityIRQ
Definition: core_feature_eclic.h:263
__RV_CSR_SET
#define __RV_CSR_SET(csr, val)
CSR operation Macro for csrs instruction.
Definition: core_feature_base.h:536
IREGION_TIMER_OFS
#define IREGION_TIMER_OFS
Definition: riscv_encoding.h:301
IREGION_SMP_OFS
#define IREGION_SMP_OFS
Definition: riscv_encoding.h:302
ECLIC_VECTOR_INTERRUPT
#define ECLIC_VECTOR_INTERRUPT
Vector Interrupt Mode of ECLIC.
Definition: core_feature_eclic.h:153
ECLIC_SetMth
#define ECLIC_SetMth
Definition: core_feature_eclic.h:247
SMP_CTRLREG
#define SMP_CTRLREG(base, ofs)
Definition: system_Device.c:682
EnableICache
__STATIC_FORCEINLINE void EnableICache(void)
Enable ICache.
Definition: core_feature_cache.h:196
ECLIC_SetPriorityIRQ_S
#define ECLIC_SetPriorityIRQ_S
Definition: core_feature_eclic.h:279
__FENCE_I
__STATIC_FORCEINLINE void __FENCE_I(void)
Fence.i Instruction.
Definition: core_feature_base.h:1475
rv_csr_t
unsigned long rv_csr_t
Type of Control and Status Register(CSR), depends on the XLEN defined in RISC-V.
Definition: core_feature_base.h:55
ICachePresent
__STATIC_FORCEINLINE int32_t ICachePresent(void)
Check ICache Unit Present or Not.
Definition: core_feature_cache.h:178
ECLIC_SetShvIRQ
#define ECLIC_SetShvIRQ
Definition: core_feature_eclic.h:257
SystemIRegionInfo
volatile IRegion_Info_Type SystemIRegionInfo
Nuclei RISC-V CPU IRegion Information Variable used to store probed info.
Definition: system_Device.c:653
MDLM_CTL_DLM_EN
#define MDLM_CTL_DLM_EN
Definition: riscv_encoding.h:212
CSR_MILM_CTL
#define CSR_MILM_CTL
Definition: riscv_encoding.h:912
__SMP_RWMB
#define __SMP_RWMB()
SMP Read & Write Memory barrier.
Definition: core_feature_base.h:1490