System Device Configuration

Functions for system and clock setup available in system_<device>.c. More...

Modules
	Interrupt and Exception and NMI Handling
	Functions for interrupt, exception and nmi handle available in system_<device>.c.

Macros
#define	CLINT_MSIP(base, hartid)   (*(volatile uint32_t *)((uintptr_t)((base) + ((hartid) * 4))))
#define	SMP_CTRLREG(base, ofs)   (*(volatile uint32_t *)((uintptr_t)((base) + (ofs))))

Functions
void	exc_entry_s (void)
void	irq_entry_s (void)
	default entry for s-mode non-vector irq entry More...
void	default_intexc_handler (void)
	default entry for s-mode exception entry More...
void	SystemCoreClockUpdate (void)
	Function to update the variable SystemCoreClock. More...
void	SystemInit (void)
	Function to Initialize the system. More...
void	SystemBannerPrint (void)
	Banner Print for Nuclei SDK. More...
void	irq_entry (void)
void	exc_entry (void)
void	ECLIC_Interrupt_Init (void)
	Do ECLIC Interrupt configuration. More...
void	CLINT_Interrupt_Init (void)
	Do CLINT Interrupt configuration. More...
void	PLIC_Interrupt_Init (void)
	Do PLIC Interrupt configuration. More...
void	Interrupt_Init (void)
	initialize interrupt controller More...
int32_t	ECLIC_Register_IRQ (IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void *handler)
	Initialize a specific IRQ and register the handler. More...
int32_t	Core_Register_IRQ (uint32_t irqn, void *handler)
	Register a m-mode riscv core interrupt and register the handler. More...
int32_t	Core_Register_IRQ_S (uint32_t irqn, void *handler)
	Register a riscv s-mode core interrupt and register the handler. More...
int32_t	PLIC_Register_IRQ (uint32_t source, uint8_t priority, void *handler)
	Register a m-mode specific plic interrupt and register the handler. More...
int32_t	PLIC_Register_IRQ_S (uint32_t source, uint8_t priority, void *handler)
	Register a s-mode specific plic interrupt and register the handler. More...
int32_t	ECLIC_Register_IRQ_S (IRQn_Type IRQn, uint8_t shv, ECLIC_TRIGGER_Type trig_mode, uint8_t lvl, uint8_t priority, void *handler)
	Initialize a specific IRQ and register the handler for supervisor mode. More...
void	__sync_harts (void)
	Synchronize all harts. More...
static void	Trap_Init (void)
	do the init for trap More...
void	_premain_init (void)
	early init function before main More...
void	_postmain_fini (int status)
	finish function after main More...
void	_init (void)
	_init function called in __libc_init_array() More...
void	_fini (void)
	_fini function called in __libc_fini_array() More...

Variables
volatile uint32_t	SystemCoreClock = SYSTEM_CLOCK
	Variable to hold the system core clock value. More...
unsigned long	vector_base []
volatile unsigned long	CpuIRegionBase = 0xFFFFFFFF
	Nuclei RISC-V CPU IRegion Base Address Probed, you should avoid to use it in your application code, please use __IREGION_BASEADDR if you want. More...

Detailed Description

Functions for system and clock setup available in system_<device>.c.

Nuclei provides a template file system_Device.c that must be adapted by the silicon vendor to match their actual device. As a minimum requirement, this file must provide:

• A device-specific system configuration function, SystemInit.
• Global c library _premain_init and _postmain_fini functions called right before calling main function.
  • A global variable that contains the system frequency, SystemCoreClock.
  • A global eclic configuration initialization, ECLIC_Init.
  • A global exception and trap configuration initialization, Trap_Init and Exception_Init.
• Vendor customized interrupt, exception and nmi handling code, see Interrupt and Exception and NMI Handling

The file configures the device and, typically, initializes the oscillator (PLL) that is part of the microcontroller device. This file might export other functions or variables that provide a more flexible configuration of the microcontroller system.

And this file also provided common interrupt, exception and NMI exception handling framework template, Silicon vendor can customize these template code as they want.

Note

Please pay special attention to the static variable SystemCoreClock. This variable might be used throughout the whole system initialization and runtime to calculate frequency/time related values. Thus one must assure that the variable always reflects the actual system clock speed.

Attention

Be aware that a value stored to SystemCoreClock during low level initialization (i.e. SystemInit()) might get overwritten by C libray startup code and/or .bss section initialization. Thus its highly recommended to call SystemCoreClockUpdate at the beginning of the user main() routine.

Macro Definition Documentation

CLINT_MSIP

#define CLINT_MSIP	(		base,
			hartid
	)		(*(volatile uint32_t *)((uintptr_t)((base) + ((hartid) * 4))))

Definition at line 1244 of file system_Device.c.

SMP_CTRLREG

#define SMP_CTRLREG	(		base,
			ofs
	)		(*(volatile uint32_t *)((uintptr_t)((base) + (ofs))))

Definition at line 1245 of file system_Device.c.

Function Documentation

__sync_harts()

void __sync_harts

(

void

)

Synchronize all harts.

This function is used to synchronize all the harts, especially to wait the boot hart finish initialization of data section, bss section and c runtines initialization This function must be placed in .text.init section, since section initialization is not ready, global variable and static variable should be avoid to use in this function, and avoid to call other functions

Definition at line 1247 of file system_Device.c.

{
// Only do synchronize when SMP_CPU_CNT is defined and number > 0
// TODO: If you don't need to support SMP, you can directly remove code in it
#if defined(SMP_CPU_CNT) && (SMP_CPU_CNT > 1)
    unsigned long hartid = __get_hart_id();
    unsigned long tmr_hartid = __get_hart_index();
    unsigned long clint_base, irgb_base, smp_base;
    unsigned long mcfg_info;
 
    // NOTE: we should avoid to use global variable such as CpuIRegionBase before smp cpu are configured
    mcfg_info = __RV_CSR_READ(CSR_MCFG_INFO);
    // Assume IREGION feature present
    if (mcfg_info & MCFG_INFO_IREGION_EXIST) { // IRegion Info present
        // clint base = system timer base + 0x1000
        irgb_base = (__RV_CSR_READ(CSR_MIRGB_INFO) >> 10) << 10;
        clint_base = irgb_base + IREGION_TIMER_OFS + 0x1000;
        smp_base = irgb_base + IREGION_SMP_OFS;
    } else {
        // Should not enter to here if iregion feature present
        while(1);
    }
    // Enable SMP
    SMP_CTRLREG(smp_base, 0xc) = 0xFFFFFFFF;
    // Enaable L2, disable cluster local memory
    if (SMP_CTRLREG(smp_base, 0x4) & 0x1) {
        SMP_CTRLREG(smp_base, 0x10) = 0x1;
        SMP_CTRLREG(smp_base, 0xd8) = 0x0;
    }
    __SMP_RWMB();
 
    // pre-condition: interrupt must be disabled, this is done before calling this function
    // BOOT_HARTID is defined <Device.h>
    if (hartid == BOOT_HARTID) { // boot hart
        // clear msip pending
        for (int i = 0; i < SMP_CPU_CNT; i ++) {
            CLINT_MSIP(clint_base, i) = 0;
        }
        __SMP_RWMB();
    } else {
        // Set machine software interrupt pending to 1
        CLINT_MSIP(clint_base, tmr_hartid) = 1;
        __SMP_RWMB();
        // wait for pending bit cleared by boot hart
        while (CLINT_MSIP(clint_base, tmr_hartid) == 1);
    }
#endif
}

_fini()

void _fini

(

void

)

_fini function called in __libc_fini_array()

This __libc_fini_array() function is called when exit main. user need to implement this function, otherwise when link it will error fini.c:(.text.__libc_fini_array+0x28): undefined reference to ‘_fini’

Note

Please use _postmain_fini function now

Definition at line 1554 of file system_Device.c.

{
    /* Don't put any code here, please use _postmain_fini now */
}

_init()

void _init

(

void

)

_init function called in __libc_init_array()

This __libc_init_array() function is called during startup code, user need to implement this function, otherwise when link it will error init.c:(.text.__libc_init_array+0x26): undefined reference to ‘_init’

Note

Please use _premain_init function now

Definition at line 1540 of file system_Device.c.

{
    /* Don't put any code here, please use _premain_init now */
}

_postmain_fini()

void _postmain_fini

(

int

status

)

finish function after main

Parameters

[in]

status

status code return from main

This function is executed right after main function. For RISC-V gnu toolchain, _fini function might not be called by __libc_fini_array function, so we defined a new function to do initialization

Definition at line 1518 of file system_Device.c.

{
#if defined(CODESIZE) && (CODESIZE == 1)
#ifdef CFG_SIMULATION
    SIMULATION_EXIT(status);
#endif
#else
    /* TODO: Add your own finishing code here, called after main */
    extern void simulation_exit(int status);
    simulation_exit(status);
#endif
}

_premain_init()

void _premain_init

(

void

)

early init function before main

This function is executed right before main function. For RISC-V gnu toolchain, _init function might not be called by __libc_init_array function, so we defined a new function to do initialization.

Definition at line 1324 of file system_Device.c.

{
#if defined(CODESIZE) && (CODESIZE == 1)
    // TODO to reduce the code size of application
    // No need to do so complex premain initialization steps
    // You just need to initialize the cpu resource you need to use in your
    // application code.
 
#ifndef CFG_IREGION_BASE_ADDR       // Need to probe the cpu iregion base address
    // Probe CPUIRegionBase for other cpu internal peripheral to use
    CpuIRegionBase = (__RV_CSR_READ(CSR_MIRGB_INFO) >> 10) << 10;
#endif
    // TODO Still need to initialize uart for other code need to do printf
    // If you want to reduce more code, you can comment below code
    uart_init(SOC_DEBUG_UART, 115200);
 
#else
    // TODO to make it possible for configurable boot hartid
    unsigned long hartid = __get_hart_id();
    unsigned long mcfginfo = __RV_CSR_READ(CSR_MCFG_INFO);
 
    /* TODO: Add your own initialization code here, called before main */
    // TODO This code controlled by macros RUNMODE_* are only used internally by Nuclei
    // You can remove it if you don't want it
    // No need to use in your code
#if defined(RUNMODE_ILM_EN) || defined(RUNMODE_ECC_EN)
    // Only disable ilm when it is present
    if (mcfginfo & MCFG_INFO_ILM) {
#if defined(RUNMODE_ECC_EN)
#if RUNMODE_ECC_EN == 0
        __RV_CSR_CLEAR(CSR_MILM_CTL, MILM_CTL_ILM_ECC_EN | MILM_CTL_ILM_ECC_EXCP_EN | MILM_CTL_ILM_ECC_CHK_EN);
#else
        __RV_CSR_SET(CSR_MILM_CTL, MILM_CTL_ILM_ECC_EN | MILM_CTL_ILM_ECC_EXCP_EN | MILM_CTL_ILM_ECC_CHK_EN);
#endif
#endif
#if defined(RUNMODE_ILM_EN)
#if RUNMODE_ILM_EN == 0
        __RV_CSR_CLEAR(CSR_MILM_CTL, MILM_CTL_ILM_EN);
#else
        __RV_CSR_SET(CSR_MILM_CTL, MILM_CTL_ILM_EN);
#endif
#endif
    }
#endif
 
#if defined(RUNMODE_DLM_EN) || defined(RUNMODE_ECC_EN)
    // Only disable dlm when it is present
    if (mcfginfo & MCFG_INFO_DLM) {
#if defined(RUNMODE_ECC_EN)
#if RUNMODE_ECC_EN == 0
        __RV_CSR_CLEAR(CSR_MDLM_CTL, MDLM_CTL_DLM_ECC_EN | MDLM_CTL_DLM_ECC_EXCP_EN | MDLM_CTL_DLM_ECC_CHK_EN);
#else
        __RV_CSR_SET(CSR_MDLM_CTL, MDLM_CTL_DLM_ECC_EN | MDLM_CTL_DLM_ECC_EXCP_EN | MDLM_CTL_DLM_ECC_CHK_EN);
#endif
#endif
#if defined(RUNMODE_DLM_EN)
#if RUNMODE_DLM_EN == 0
        __RV_CSR_CLEAR(CSR_MDLM_CTL, MDLM_CTL_DLM_EN);
#else
        __RV_CSR_SET(CSR_MDLM_CTL, MDLM_CTL_DLM_EN);
#endif
#endif
    }
#endif
 
#if defined(RUNMODE_LDSPEC_EN)
#if RUNMODE_LDSPEC_EN == 1
    __RV_CSR_SET(CSR_MMISC_CTL, MMISC_CTL_LDSPEC_ENABLE);
#else
    __RV_CSR_CLEAR(CSR_MMISC_CTL, MMISC_CTL_LDSPEC_ENABLE);
#endif
#endif
 
    /* __ICACHE_PRESENT and __DCACHE_PRESENT are defined in evalsoc.h */
    // For our internal cpu testing, they want to set evalsoc __ICACHE_PRESENT/__DCACHE_PRESENT to be 1
    // __CCM_PRESENT is still default to 0 in evalsoc.h, since it is used in core_feature_eclic.h to register interrupt, if set to 1, it might cause exception
    // but in the cpu, icache or dcache might not exist due to cpu configuration, so here
    // we need to check whether icache/dcache really exist, if yes, then turn on it
#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1)
    if (ICachePresent()) { // Check whether icache real present or not
#if defined(RUNMODE_ECC_EN)
#if RUNMODE_ECC_EN == 0
        __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_IC_ECC_EN | MCACHE_CTL_IC_ECC_EXCP_EN | MCACHE_CTL_IC_ECC_CHK_EN);
#else
        __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_IC_ECC_EN | MCACHE_CTL_IC_ECC_EXCP_EN | MCACHE_CTL_IC_ECC_CHK_EN);
#endif
#endif
        EnableICache();
    }
#endif
#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1)
    if (DCachePresent()) { // Check whether dcache real present or not
#if defined(RUNMODE_ECC_EN)
#if RUNMODE_ECC_EN == 0
        __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_DC_ECC_EN | MCACHE_CTL_DC_ECC_EXCP_EN | MCACHE_CTL_DC_ECC_CHK_EN);
#else
        __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_DC_ECC_EN | MCACHE_CTL_DC_ECC_EXCP_EN | MCACHE_CTL_DC_ECC_CHK_EN);
#endif
#endif
        EnableDCache();
    }
#endif
 
    /* Do fence and fence.i to make sure previous ilm/dlm/icache/dcache control done */
    __RWMB();
    __FENCE_I();
 
    // BOOT_HARTID is defined <Device.h> and also controlled by BOOT_HARTID in conf/evalsoc/build.mk
#ifndef CFG_IREGION_BASE_ADDR       // Need to probe the cpu iregion base address
    if (hartid == BOOT_HARTID) { // only done in boot hart
        // IREGION INFO MUST BE AFTER L1/L2 Cache enabled and SMP enabled if SMP present
        CpuIRegionBase = (__RV_CSR_READ(CSR_MIRGB_INFO) >> 10) << 10;
    } else {
        // wait for correct iregion base addr is set by boot hart
        while (CpuIRegionBase == 0xFFFFFFFF);
    }
#endif
 
#if defined(RUNMODE_L2_EN)
    if ((mcfginfo & (0x1 << 11)) && SMP_CTRLREG(__SMPCC_BASEADDR, 0x4) & 0x1 ) { // L2 Cache present
#if RUNMODE_L2_EN == 1
        // Enable L2, disable cluster local memory
        SMP_CTRLREG(__SMPCC_BASEADDR, 0x10) = 0x1;
        SMP_CTRLREG(__SMPCC_BASEADDR, 0xd8) = 0x0;
        __SMP_RWMB();
#else
        // Disable L2, enable cluster local memory
        SMP_CTRLREG(__SMPCC_BASEADDR, 0x10) = 0x0;
        // use as clm or cache, when l2 disable, the affect to ddr is the same, l2 is really disabled
        SMP_CTRLREG(__SMPCC_BASEADDR, 0xd8) = 0;//0xFFFFFFFF;
        __SMP_RWMB();
#endif
    }
#endif
 
#if defined(RUNMODE_BPU_EN)
#if RUNMODE_BPU_EN == 1
    __RV_CSR_SET(CSR_MMISC_CTL, MMISC_CTL_BPU);
#else
    __RV_CSR_CLEAR(CSR_MMISC_CTL, MMISC_CTL_BPU);
#endif
#endif
 
#if defined(__CCM_PRESENT) && (__CCM_PRESENT == 1)
    // NOTE: CFG_HAS_SMODE and CFG_HAS_UMODE are defined in auto generated cpufeature.h if present in cpu
#if defined(CFG_HAS_SMODE) || defined(CFG_HAS_UMODE)
    EnableSUCCM();
#endif
#endif
 
    if (hartid == BOOT_HARTID) { // only required for boot hartid
        // TODO implement get_cpu_freq function to get real cpu clock freq in HZ or directly give the real cpu HZ
        // TODO you can directly give the correct cpu frequency here, if you know it without call get_cpu_freq function
        SystemCoreClock = get_cpu_freq();
        uart_init(SOC_DEBUG_UART, 115200);
        /* Display banner after UART initialized */
        SystemBannerPrint();
        /* Initialize exception default handlers */
        Exception_Init();
        /* Interrupt initialization */
        Interrupt_Init();
        // TODO: internal usage for Nuclei
#ifdef RUNMODE_CONTROL
        NSDK_DEBUG("Current RUNMODE=%s, ilm:%d, dlm %d, icache %d, dcache %d, ccm %d\n", \
            RUNMODE_STRING, RUNMODE_ILM_EN, RUNMODE_DLM_EN, \
            RUNMODE_IC_EN, RUNMODE_DC_EN, RUNMODE_CCM_EN);
        // ILM and DLM need to be present
        if (mcfginfo & 0x180 == 0x180) {
            NSDK_DEBUG("CSR: MILM_CTL 0x%x, MDLM_CTL 0x%x\n", \
                __RV_CSR_READ(CSR_MILM_CTL), __RV_CSR_READ(CSR_MDLM_CTL));
        }
        // I/D cache need to be present
        if (mcfginfo & 0x600) {
            NSDK_DEBUG("CSR: MCACHE_CTL 0x%x\n", __RV_CSR_READ(CSR_MCACHE_CTL));
        }
        NSDK_DEBUG("CSR: MMISC_CTL 0x%x\n", __RV_CSR_READ(CSR_MMISC_CTL));
#endif
    } else {
        /* Interrupt initialization */
        Interrupt_Init();
    }
 
#endif
}

References __FENCE_I(), __get_hart_id(), __RV_CSR_CLEAR, __RV_CSR_READ, __RV_CSR_SET, __RWMB, __SMP_RWMB, CpuIRegionBase, CSR_MCACHE_CTL, CSR_MCFG_INFO, CSR_MDLM_CTL, CSR_MILM_CTL, CSR_MIRGB_INFO, CSR_MMISC_CTL, DCachePresent(), EnableDCache(), EnableICache(), EnableSUCCM(), Exception_Init(), ICachePresent(), Interrupt_Init(), MCACHE_CTL_DC_ECC_CHK_EN, MCACHE_CTL_DC_ECC_EN, MCACHE_CTL_DC_ECC_EXCP_EN, MCACHE_CTL_IC_ECC_CHK_EN, MCACHE_CTL_IC_ECC_EN, MCACHE_CTL_IC_ECC_EXCP_EN, MCFG_INFO_DLM, MCFG_INFO_ILM, MDLM_CTL_DLM_ECC_CHK_EN, MDLM_CTL_DLM_ECC_EN, MDLM_CTL_DLM_ECC_EXCP_EN, MDLM_CTL_DLM_EN, MILM_CTL_ILM_ECC_CHK_EN, MILM_CTL_ILM_ECC_EN, MILM_CTL_ILM_ECC_EXCP_EN, MILM_CTL_ILM_EN, MMISC_CTL_BPU, MMISC_CTL_LDSPEC_ENABLE, SMP_CTRLREG, SystemBannerPrint(), and SystemCoreClock.

CLINT_Interrupt_Init()

void CLINT_Interrupt_Init

(

void

)

Do CLINT Interrupt configuration.

This function will initialize cpu interrupt mode to clint mode. It will

• Set exception/interrupt entry to exc_entry, now interrupt and exception share the same entry point
• Register interrupt handling routine system_core_interrupt_handler to core_interrupt_handler function, which will be called in core_exception_handler function

Definition at line 935 of file system_Device.c.

{
    /* Register core interrupt handler for clint/plic interrupt mode */
    system_core_interrupt_handler = core_interrupt_handler;
    /* Set as CLINT interrupt mode */
    __RV_CSR_WRITE(CSR_MTVEC, (unsigned long)exc_entry);
#if defined(__SMODE_PRESENT) && (__SMODE_PRESENT == 1)
    /*
     * Set supervisor exception entry stvec to exc_entry_s
     */
    __RV_CSR_WRITE(CSR_STVEC, (unsigned long)exc_entry_s);
    system_core_interrupt_handler_s = core_interrupt_handler_s;
#endif
    for (int i = 0; i < SYSTEM_CORE_INTNUM; i++) {
        SystemCoreInterruptHandlers[i] = (unsigned long)system_default_interrupt_handler;
#if defined(__SMODE_PRESENT) && (__SMODE_PRESENT == 1)
        SystemCoreInterruptHandlers_S[i] = (unsigned long)system_default_interrupt_handler_s;
#endif
    }
}

References __RV_CSR_WRITE, core_interrupt_handler(), core_interrupt_handler_s(), CSR_MTVEC, CSR_STVEC, exc_entry(), exc_entry_s(), system_core_interrupt_handler, system_core_interrupt_handler_s, SYSTEM_CORE_INTNUM, system_default_interrupt_handler(), system_default_interrupt_handler_s(), SystemCoreInterruptHandlers, and SystemCoreInterruptHandlers_S.

Referenced by PLIC_Interrupt_Init().

Core_Register_IRQ()

int32_t Core_Register_IRQ	(	uint32_t	irqn,
		void *	handler
	)

Register a m-mode riscv core interrupt and register the handler.

This function set interrupt handler for core interrupt in non-eclic mode

Parameters

[in]	irqn	interrupt number
[in]	handler	interrupt handler, if NULL, handler will not be installed

Returns

-1 means invalid input parameter. 0 means successful.

Remarks

• This function use to configure riscv core interrupt and register its interrupt handler and enable its interrupt.
• You can only use it when you are not in eclic interrupt mode

Definition at line 1069 of file system_Device.c.

{
    if ((irqn > SYSTEM_CORE_INTNUM)) {
        return -1;
    }
 
    if (handler != NULL) {
        /* register interrupt handler entry to core handlers */
        Interrupt_Register_CoreIRQ(irqn, (unsigned long)handler);
    }
    switch (irqn) {
        case SysTimerSW_IRQn:
            __enable_sw_irq();
            break;
        case SysTimer_IRQn:
            __enable_timer_irq();
            break;
        default:
            break;
    }
 
    return 0;
}

References __enable_sw_irq(), __enable_timer_irq(), Interrupt_Register_CoreIRQ(), SYSTEM_CORE_INTNUM, SysTimer_IRQn, and SysTimerSW_IRQn.

Core_Register_IRQ_S()

int32_t Core_Register_IRQ_S	(	uint32_t	irqn,
		void *	handler
	)

Register a riscv s-mode core interrupt and register the handler.

This function set interrupt handler for core interrupt in non-eclic mode

Parameters

[in]	irqn	interrupt number
[in]	handler	interrupt handler, if NULL, handler will not be installed

Returns

-1 means invalid input parameter. 0 means successful.

Remarks

• This function use to configure riscv core interrupt and register its interrupt handler and enable its interrupt.
• You can only use it when you are not in eclic interrupt mode

Definition at line 1105 of file system_Device.c.

{
    if ((irqn > SYSTEM_CORE_INTNUM)) {
        return -1;
    }
 
    if (handler != NULL) {
        /* register interrupt handler entry to core handlers */
        Interrupt_Register_CoreIRQ_S(irqn, (unsigned long)handler);
    }
    switch (irqn) {
        case SysTimerSW_S_IRQn:
            __enable_sw_irq_s();
            break;
        case SysTimer_S_IRQn:
            __enable_timer_irq_s();
            break;
        default:
            break;
    }
 
    return 0;
}

References __enable_sw_irq_s(), __enable_timer_irq_s(), Interrupt_Register_CoreIRQ_S(), and SYSTEM_CORE_INTNUM.

default_intexc_handler()

void default_intexc_handler

(

void

)

default entry for s-mode exception entry

default eclic interrupt or exception interrupt handler

ECLIC_Interrupt_Init()

void ECLIC_Interrupt_Init

(

void

)

Do ECLIC Interrupt configuration.

This function will initialize cpu interrupt mode to eclic mode. It will

• set common non-vector entry to irq_entry
• set vector interrupt table to vector_base
• set exception entry to exc_entry
• set eclic mth to 0, and nlbits to the bigest bits it supports
• set s-mode common non-vector entry to irq_entry_s if tee present
• set s-mode vector interrupt table to vector_base_s if tee present
• set s-mode exception entry to exc_entry_s if tee present
• set eclic sth to 0 if tee present

Definition at line 879 of file system_Device.c.

{
#if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1)
    unsigned long mcfg_info;
 
    mcfg_info = __RV_CSR_READ(CSR_MCFG_INFO);
    if (mcfg_info & MCFG_INFO_CLIC) {
        /* Set ECLIC vector interrupt base address to vector_base */
        __RV_CSR_WRITE(CSR_MTVT, (unsigned long)vector_base);
        /* Set ECLIC non-vector entry to irq_entry */
        __RV_CSR_WRITE(CSR_MTVT2, (unsigned long)irq_entry | 0x1);
        /* Set as CLIC interrupt mode */
        __RV_CSR_WRITE(CSR_MTVEC, (unsigned long)exc_entry | 0x3);
        /* Global Configuration about MTH and NLBits.
         * TODO: Please adapt it according to your system requirement.
         * This function is called in _init function */
        ECLIC_SetMth(0);
        ECLIC_SetCfgNlbits(__ECLIC_INTCTLBITS);
 
#if defined(__TEE_PRESENT) && (__TEE_PRESENT == 1)
        if (mcfg_info & MCFG_INFO_TEE) {
            /*
             * Intialize ECLIC supervisor mode vector interrupt
             * base address stvt to vector_table_s
             */
            __RV_CSR_WRITE(CSR_STVT, (unsigned long)vector_table_s);
            /*
             * Set ECLIC supervisor mode non-vector entry to be controlled
             * by stvt2 CSR register.
             * Intialize supervisor mode ECLIC non-vector interrupt
             * base address stvt2 to irq_entry_s.
            */
            __RV_CSR_WRITE(CSR_STVT2, (unsigned long)irq_entry_s);
            __RV_CSR_SET(CSR_STVT2, 0x01);
            /*
             * Set supervisor exception entry stvec to exc_entry_s */
            __RV_CSR_WRITE(CSR_STVEC, (unsigned long)exc_entry_s);
            /* Global Configuration about STH */
            ECLIC_SetSth(0);
        }
#endif
    } else {
        /* Set as CLINT interrupt mode */
        __RV_CSR_WRITE(CSR_MTVEC, (unsigned long)exc_entry);
    }
#endif
}

References __RV_CSR_READ, __RV_CSR_SET, __RV_CSR_WRITE, CSR_MCFG_INFO, CSR_MTVEC, CSR_MTVT, CSR_MTVT2, CSR_STVEC, CSR_STVT, CSR_STVT2, ECLIC_SetCfgNlbits, ECLIC_SetMth, ECLIC_SetSth, exc_entry(), exc_entry_s(), irq_entry(), irq_entry_s(), MCFG_INFO_CLIC, MCFG_INFO_TEE, and vector_base.

Referenced by Interrupt_Init().

ECLIC_Register_IRQ()

int32_t ECLIC_Register_IRQ	(	IRQn_Type	IRQn,
		uint8_t	shv,
		ECLIC_TRIGGER_Type	trig_mode,
		uint8_t	lvl,
		uint8_t	priority,
		void *	handler
	)

Initialize a specific IRQ and register the handler.

This function set vector mode, trigger mode and polarity, interrupt level and priority, assign handler for specific IRQn.

Parameters

[in]	IRQn	NMI interrupt handler address
[in]	shv	ECLIC_NON_VECTOR_INTERRUPT means non-vector mode, and ECLIC_VECTOR_INTERRUPT is vector mode
[in]	trig_mode	see ECLIC_TRIGGER_Type
[in]	lvl	interupt level
[in]	priority	interrupt priority
[in]	handler	interrupt handler, if NULL, handler will not be installed

Returns

-1 means invalid input parameter. 0 means successful.

Remarks

• This function use to configure specific eclic interrupt and register its interrupt handler and enable its interrupt.
• If the vector table is placed in read-only section(FLASHXIP mode), handler could not be installed

Definition at line 1033 of file system_Device.c.

{
    if ((IRQn > SOC_INT_MAX) || (shv > ECLIC_VECTOR_INTERRUPT) \
        || (trig_mode > ECLIC_NEGTIVE_EDGE_TRIGGER)) {
        return -1;
    }
 
    /* set interrupt vector mode */
    ECLIC_SetShvIRQ(IRQn, shv);
    /* set interrupt trigger mode and polarity */
    ECLIC_SetTrigIRQ(IRQn, trig_mode);
    /* set interrupt level */
    ECLIC_SetLevelIRQ(IRQn, lvl);
    /* set interrupt priority */
    ECLIC_SetPriorityIRQ(IRQn, priority);
    if (handler != NULL) {
        /* set interrupt handler entry to vector table */
        ECLIC_SetVector(IRQn, (rv_csr_t)handler);
    }
    /* enable interrupt */
    ECLIC_EnableIRQ(IRQn);
    return 0;
}

References ECLIC_EnableIRQ, ECLIC_NEGTIVE_EDGE_TRIGGER, ECLIC_SetLevelIRQ, ECLIC_SetPriorityIRQ, ECLIC_SetShvIRQ, ECLIC_SetTrigIRQ, ECLIC_SetVector, ECLIC_VECTOR_INTERRUPT, and SOC_INT_MAX.

ECLIC_Register_IRQ_S()

int32_t ECLIC_Register_IRQ_S	(	IRQn_Type	IRQn,
		uint8_t	shv,
		ECLIC_TRIGGER_Type	trig_mode,
		uint8_t	lvl,
		uint8_t	priority,
		void *	handler
	)

Initialize a specific IRQ and register the handler for supervisor mode.

This function set vector mode, trigger mode and polarity, interrupt level and priority, assign handler for specific IRQn.

Parameters

[in]	IRQn	NMI interrupt handler address
[in]	shv	ECLIC_NON_VECTOR_INTERRUPT means non-vector mode, and ECLIC_VECTOR_INTERRUPT is vector mode
[in]	trig_mode	see ECLIC_TRIGGER_Type
[in]	lvl	interupt level
[in]	priority	interrupt priority
[in]	handler	interrupt handler, if NULL, handler will not be installed

Returns

-1 means invalid input parameter. 0 means successful.

Remarks

• This function use to configure specific eclic S-mode interrupt and register its interrupt handler and enable its interrupt.
• If the vector table is placed in read-only section (FLASHXIP mode), handler could not be installed.

Definition at line 1211 of file system_Device.c.

{
    if ((IRQn > SOC_INT_MAX) || (shv > ECLIC_VECTOR_INTERRUPT) \
        || (trig_mode > ECLIC_NEGTIVE_EDGE_TRIGGER)) {
        return -1;
    }
 
    /* set interrupt vector mode */
    ECLIC_SetShvIRQ_S(IRQn, shv);
    /* set interrupt trigger mode and polarity */
    ECLIC_SetTrigIRQ_S(IRQn, trig_mode);
    /* set interrupt level */
    ECLIC_SetLevelIRQ_S(IRQn, lvl);
    /* set interrupt priority */
    ECLIC_SetPriorityIRQ_S(IRQn, priority);
    if (handler != NULL) {
        /* set interrupt handler entry to vector table */
        ECLIC_SetVector_S(IRQn, (rv_csr_t)handler);
    }
    /* enable interrupt */
    ECLIC_EnableIRQ_S(IRQn);
    return 0;
}

References ECLIC_EnableIRQ_S, ECLIC_NEGTIVE_EDGE_TRIGGER, ECLIC_SetLevelIRQ_S, ECLIC_SetPriorityIRQ_S, ECLIC_SetShvIRQ_S, ECLIC_SetTrigIRQ_S, ECLIC_SetVector_S, ECLIC_VECTOR_INTERRUPT, and SOC_INT_MAX.

exc_entry()

void exc_entry

(

void

)

Referenced by CLINT_Interrupt_Init(), ECLIC_Interrupt_Init(), and Interrupt_Init().

exc_entry_s()

void exc_entry_s

(

void

)

Referenced by CLINT_Interrupt_Init(), and ECLIC_Interrupt_Init().

Interrupt_Init()

void Interrupt_Init

(

void

)

initialize interrupt controller

Do CPU interrupt initialization, if plic present, init it, then init eclic if present. So if ECLIC present, the interrupt will default configured to ECLIC interrupt mode, if you want to switch to PLIC interrupt mode, you need to call PLIC_Interrupt_Init in you application code.

By default, if ECLIC present, eclic interrupt mode will be set, otherwise it will be clint/plic interrupt mode

Remarks

This function previously was ECLIC_Init, now ECLIC_Init is removed

Definition at line 997 of file system_Device.c.

{
#if defined(CODESIZE) && (CODESIZE == 1)
#else
    /* Set as CLINT interrupt mode */
    __RV_CSR_WRITE(CSR_MTVEC, (unsigned long)exc_entry);
 
    /* Init interrupt as eclic mode when ECLIC present
     * Otherwise will init interrupt as plic mode when PLIC present
     * Only initialize necessary ones to reduce initialization code size usage */
#if defined(__ECLIC_PRESENT) && (__ECLIC_PRESENT == 1)
    ECLIC_Interrupt_Init();
#elif defined(__PLIC_PRESENT) && (__PLIC_PRESENT == 1)
    PLIC_Interrupt_Init();
#endif
 
#endif
}

References __RV_CSR_WRITE, CSR_MTVEC, ECLIC_Interrupt_Init(), exc_entry(), and PLIC_Interrupt_Init().

Referenced by _premain_init().

irq_entry()

void irq_entry

(

void

)

Referenced by ECLIC_Interrupt_Init().

irq_entry_s()

void irq_entry_s

(

void

)

default entry for s-mode non-vector irq entry

Referenced by ECLIC_Interrupt_Init().

PLIC_Interrupt_Init()

void PLIC_Interrupt_Init

(

void

)

Do PLIC Interrupt configuration.

This function will initialize cpu interrupt mode to clint/plic mode. It will

• Initialize a software maintained SystemM/SExtInterruptHandlers and SystemCoreInterruptHandlers to default value
• Set exception/interrupt entry to exc_entry, now interrupt and exception share the same entry point

Definition at line 963 of file system_Device.c.

{
    CLINT_Interrupt_Init();
#if defined(__PLIC_PRESENT) && (__PLIC_PRESENT == 1)
    int i;
    for (i = 0; i < __PLIC_INTNUM; i++) {
        SystemMExtInterruptHandlers[i] = (unsigned long)system_default_interrupt_handler;
#if defined(__SMODE_PRESENT) && (__SMODE_PRESENT == 1)
        SystemSExtInterruptHandlers[i] = (unsigned long)system_default_interrupt_handler_s;
#endif
    }
 
    SystemCoreInterruptHandlers[9] = (unsigned long)system_mmode_extirq_handler;
    SystemCoreInterruptHandlers[11] = (unsigned long)system_mmode_extirq_handler;
#if defined(__SMODE_PRESENT) && (__SMODE_PRESENT == 1)
    SystemCoreInterruptHandlers_S[9] = (unsigned long)system_smode_extirq_handler;
    SystemCoreInterruptHandlers_S[11] = (unsigned long)system_smode_extirq_handler;
#endif
#endif
}

References CLINT_Interrupt_Init(), system_default_interrupt_handler(), system_default_interrupt_handler_s(), system_mmode_extirq_handler(), system_smode_extirq_handler(), SystemCoreInterruptHandlers, SystemCoreInterruptHandlers_S, SystemMExtInterruptHandlers, and SystemSExtInterruptHandlers.

Referenced by Interrupt_Init().

PLIC_Register_IRQ()

int32_t PLIC_Register_IRQ	(	uint32_t	source,
		uint8_t	priority,
		void *	handler
	)

Register a m-mode specific plic interrupt and register the handler.

This function set priority and handler for m-mode plic interrupt

Parameters

[in]	source	interrupt source
[in]	priority	interrupt priority
[in]	handler	interrupt handler, if NULL, handler will not be installed

Returns

-1 means invalid input parameter. 0 means successful.

Remarks

• This function use to configure specific plic interrupt and register its interrupt handler and enable its interrupt.
• You can only use it when you are in plic interrupt mode

Definition at line 1143 of file system_Device.c.

{
    if ((source >= __PLIC_INTNUM)) {
        return -1;
    }
 
    /* set interrupt priority */
    PLIC_SetPriority(source, priority);
    if (handler != NULL) {
        /* register interrupt handler entry to external handlers */
        Interrupt_Register_ExtIRQ(source, (unsigned long)handler);
    }
    /* enable interrupt */
    PLIC_EnableInterrupt(source);
    __enable_ext_irq();
    return 0;
}

References __enable_ext_irq(), Interrupt_Register_ExtIRQ(), PLIC_EnableInterrupt, and PLIC_SetPriority().

PLIC_Register_IRQ_S()

int32_t PLIC_Register_IRQ_S	(	uint32_t	source,
		uint8_t	priority,
		void *	handler
	)

Register a s-mode specific plic interrupt and register the handler.

This function set priority and handler for s-mode plic interrupt

Parameters

[in]	source	interrupt source
[in]	priority	interrupt priority
[in]	handler	interrupt handler, if NULL, handler will not be installed

Returns

-1 means invalid input parameter. 0 means successful.

Remarks

• This function use to configure specific plic interrupt and register its interrupt handler and enable its interrupt.
• You can only use it when you are in plic interrupt mode

Definition at line 1174 of file system_Device.c.

{
    if ((source >= __PLIC_INTNUM)) {
        return -1;
    }
 
    /* set interrupt priority */
    PLIC_SetPriority(source, priority);
    if (handler != NULL) {
        /* register interrupt handler entry to external handlers */
        Interrupt_Register_ExtIRQ_S(source, (unsigned long)handler);
    }
    /* enable interrupt */
    PLIC_EnableInterrupt_S(source);
    __enable_ext_irq_s();
    return 0;
}

References __enable_ext_irq_s(), Interrupt_Register_ExtIRQ_S(), PLIC_EnableInterrupt_S, and PLIC_SetPriority().

SystemBannerPrint()

void SystemBannerPrint

(

void

)

Banner Print for Nuclei SDK.

Definition at line 847 of file system_Device.c.

{
#if defined(NUCLEI_BANNER) && (NUCLEI_BANNER == 1)
    NSDK_DEBUG("Nuclei SDK Build Time: %s, %s\r\n", __DATE__, __TIME__);
#ifdef DOWNLOAD_MODE_STRING
    NSDK_DEBUG("Download Mode: %s\r\n", DOWNLOAD_MODE_STRING);
#endif
    NSDK_DEBUG("CPU Frequency %u Hz\r\n", (unsigned int)SystemCoreClock);
    NSDK_DEBUG("CPU HartID: %u\r\n", (unsigned int)__get_hart_id());
#endif
}

References __get_hart_id(), and SystemCoreClock.

Referenced by _premain_init().

SystemCoreClockUpdate()

void SystemCoreClockUpdate

(

void

)

Function to update the variable SystemCoreClock.

Updates the variable SystemCoreClock and must be called whenever the core clock is changed during program execution. The function evaluates the clock register settings and calculates the current core clock.

Definition at line 197 of file system_Device.c.

{
    /* ToDo: add code to calculate the system frequency based upon the current
     *    register settings.
     * Note: This function can be used to retrieve the system core clock frequeny
     *    after user changed register settings.
     */
}

SystemInit()

void SystemInit

(

void

)

Function to Initialize the system.

Initializes the microcontroller system. Typically, this function configures the oscillator (PLL) that is part of the microcontroller device. For systems with a variable clock speed, it updates the variable SystemCoreClock. SystemInit is called from the file startup_device.

Definition at line 214 of file system_Device.c.

{
    /* ToDo: add code to initialize the system
     * Warn: do not use global variables because this function is called before
     * reaching pre-main. RW section maybe overwritten afterwards.
     */
}

Trap_Init()

static void Trap_Init ( void  )

static

do the init for trap

Definition at line 1312 of file system_Device.c.

{
}

Variable Documentation

CpuIRegionBase

volatile unsigned long CpuIRegionBase = 0xFFFFFFFF

Nuclei RISC-V CPU IRegion Base Address Probed, you should avoid to use it in your application code, please use __IREGION_BASEADDR if you want.

Definition at line 1241 of file system_Device.c.

Referenced by _premain_init().

SystemCoreClock

volatile uint32_t SystemCoreClock = SYSTEM_CLOCK

Variable to hold the system core clock value.

Holds the system core clock, which is the system clock frequency supplied to the SysTick timer and the processor core clock. This variable can be used by debuggers to query the frequency of the debug timer or to configure the trace clock speed.

Attention

Compilers must be configured to avoid removing this variable in case the application program is not using it. Debugging systems require the variable to be physically present in memory so that it can be examined to configure the debugger.

Definition at line 184 of file system_Device.c.

Referenced by _premain_init(), and SystemBannerPrint().

vector_base

unsigned long vector_base[]

extern

Referenced by ECLIC_Interrupt_Init().