core_feature_plic.h

/*
 * Copyright (c) 2019 Nuclei Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#ifndef __CORE_FEATURE_PLIC__
#define __CORE_FEATURE_PLIC__
 
/*
 * PLIC Feature Configuration Macro:
 * 1. __PLIC_PRESENT:  Define whether Platform Level Interrupt Controller (PLIC) Unit is present or not
 *   * 0: Not present
 *   * 1: Present
 * 2. __PLIC_BASEADDR:  Base address of the PLIC unit.
 * 3. __PLIC_INTNUM  : Define the external interrupt number of PLIC Unit
 *
 */
#ifdef __cplusplus
 extern "C" {
#endif
 
#include "core_feature_base.h"
 
#if defined(__PLIC_PRESENT) && (__PLIC_PRESENT == 1)
 
/*
 * PLIC Memory Map (per RISC-V PLIC spec):
 *
 *  Interrupt Source Priority (per-source, not per-context):
 *    base + 0x000000: Source 0 (reserved, not exist)
 *    base + 0x000004: Source 1 priority
 *    ...
 *    base + 0x000FFC: Source 1023 priority
 *    addr = base + source * 4
 *
 *  Interrupt Pending Bits (per-source, not per-context):
 *    base + 0x001000: Source 0-31 pending
 *    base + 0x001004: Source 32-63 pending
 *    ...
 *    addr = base + 0x1000 + (source / 32) * 4
 *
 *  Interrupt Enable Bits (per-context, 0x80 bytes each):
 *    base + 0x002000: Context 0, Source 0-31 enable
 *    base + 0x002080: Context 1, Source 0-31 enable
 *    ...
 *    addr = base + 0x2000 + ctxid * 0x80 + (source / 32) * 4
 *
 *  Priority Threshold (per-context, 0x1000 bytes each):
 *    base + 0x200000: Context 0 threshold
 *    base + 0x201000: Context 1 threshold
 *    ...
 *    addr = base + 0x200000 + ctxid * 0x1000
 *
 *  Claim / Complete (per-context, same 4K block as threshold):
 *    base + 0x200004: Context 0 claim/complete
 *    base + 0x201004: Context 1 claim/complete
 *    ...
 *    addr = base + 0x200004 + ctxid * 0x1000
 *    Claim: read returns highest-priority pending interrupt ID
 *    Complete: write interrupt ID to signal handler completion
 *
 *  Context ID to Hart/Mode mapping (Nuclei RISC-V CPU, not in PLIC spec):
 *    M-mode context ID = hartid * 2     (even: 0, 2, 4, 6, 8)
 *    S-mode context ID = hartid * 2 + 1 (odd:  1, 3, 5, 7, 9)
 *
 *    Hart 0: M=ctxid 0, S=ctxid 1
 *    Hart 1: M=ctxid 2, S=ctxid 3
 *    Hart 2: M=ctxid 4, S=ctxid 5
 *    Hart 3: M=ctxid 6, S=ctxid 7
 *    Hart 4: M=ctxid 8, S=ctxid 9
 *
 * Reference: https://github.com/riscv/riscv-plic-spec
 */
 
/* Priority: 32 bits per source, addr = base + source * 4 */
#define PLIC_PRIORITY_OFFSET                _AC(0x0000,UL)      
#define PLIC_PRIORITY_SHIFT_PER_SOURCE      2                   
/* Pending: 1 bit per source, packed 32 per 32-bit register */
#define PLIC_PENDING_OFFSET                 _AC(0x1000,UL)      
#define PLIC_PENDING_SHIFT_PER_SOURCE       0                   
/* Enable: 0x80 (128) bytes per context, packed 32 sources per 32-bit word */
#define PLIC_ENABLE_OFFSET                  _AC(0x2000,UL)      
#define PLIC_ENABLE_SHIFT_PER_CONTEXT       7                   
/* Threshold: 0x1000 (4096) bytes per context */
#define PLIC_THRESHOLD_OFFSET               _AC(0x200000,UL)    
#define PLIC_CLAIM_OFFSET                   _AC(0x200004,UL)    
#define PLIC_THRESHOLD_SHIFT_PER_CONTEXT    12                  
#define PLIC_CLAIM_SHIFT_PER_CONTEXT        12                  
#ifndef __PLIC_BASEADDR
/* Base address of PLIC(__PLIC_BASEADDR) should be defined in <Device.h> */
#error "__PLIC_BASEADDR is not defined, please check!"
#endif
 
/* PLIC Memory mapping of Device */
#define PLIC_BASE                           __PLIC_BASEADDR     
#ifndef __PLIC_HARTID
#define PLIC_GetHartID()                    (__get_hart_index())
#define PLIC_GetHartID_S()                  (__get_hart_index_s())
#else
#define PLIC_GetHartID()                    (__PLIC_HARTID)
#define PLIC_GetHartID_S()                  (__PLIC_HARTID)
#endif
 
/*
 * Context ID mapping (Nuclei RISC-V CPU convention):
 *   M-mode: ctxid = hartid * 2   (even: 0, 2, 4, 6, 8)
 *   S-mode: ctxid = hartid * 2 + 1 (odd:  1, 3, 5, 7, 9)
 * This is NOT part of the RISC-V PLIC spec.
 */
#define PLIC_GetHartMContextID()            (PLIC_GetHartID() << 1)
// TODO SMODE HARTID need to handle, maybe use CSR shartid defined by Nuclei RISC-V CPU
#define PLIC_GetHartSContextID()            ((PLIC_GetHartID_S() << 1) + 1)
 
#define PLIC_PRIORITY_REGADDR(source)       ((PLIC_BASE) + (PLIC_PRIORITY_OFFSET)  + ((source) << PLIC_PRIORITY_SHIFT_PER_SOURCE))
#define PLIC_PENDING_REGADDR(source)        ((PLIC_BASE) + (PLIC_PENDING_OFFSET)   + (((source) >> 5) * 4))
#define PLIC_ENABLE_REGADDR(ctxid, source)  ((PLIC_BASE) + (PLIC_ENABLE_OFFSET)    + ((ctxid) << PLIC_ENABLE_SHIFT_PER_CONTEXT) + ((source) >> 5) * 4)
#define PLIC_THRESHOLD_REGADDR(ctxid)       ((PLIC_BASE) + (PLIC_THRESHOLD_OFFSET) + ((ctxid) << PLIC_THRESHOLD_SHIFT_PER_CONTEXT))
#define PLIC_CLAIM_REGADDR(ctxid)           ((PLIC_BASE) + (PLIC_CLAIM_OFFSET) + ((ctxid) << PLIC_CLAIM_SHIFT_PER_CONTEXT))
#define PLIC_COMPLETE_REGADDR(ctxid)        (PLIC_CLAIM_REGADDR(ctxid))
 
 /* end of group NMSIS_Core_PLIC_Registers */
 
/* ##########################   PLIC functions  #################################### */
__STATIC_FORCEINLINE void PLIC_SetContextThreshold(uint32_t ctxid, uint32_t thresh)
{
    volatile uint32_t *thresh_reg = (uint32_t *)PLIC_THRESHOLD_REGADDR(ctxid);
 
    *thresh_reg = thresh;
}
 
__STATIC_FORCEINLINE uint32_t PLIC_GetContextThreshold(uint32_t ctxid)
{
    volatile uint32_t *thresh_reg = (uint32_t *)PLIC_THRESHOLD_REGADDR(ctxid);
 
    return (*thresh_reg);
}
 
__STATIC_FORCEINLINE void PLIC_EnableContextInterrupt(uint32_t ctxid, uint32_t source)
{
    volatile uint32_t *enable_reg = (uint32_t *)PLIC_ENABLE_REGADDR(ctxid, source);
 
    uint32_t current = *enable_reg;
    current = current | (1UL << (source & 0x1F));
    *enable_reg = current;
}
 
__STATIC_FORCEINLINE void PLIC_DisableContextInterrupt(uint32_t ctxid, uint32_t source)
{
    volatile uint32_t *enable_reg = (uint32_t *)PLIC_ENABLE_REGADDR(ctxid, source);
 
    uint32_t current = *enable_reg;
    current = current & (~(1UL << (source & 0x1F)));
    *enable_reg = current;
}
 
__STATIC_FORCEINLINE uint32_t PLIC_GetContextInterruptEnable(uint32_t ctxid, uint32_t source)
{
    volatile uint32_t *enable_reg = (uint32_t *)PLIC_ENABLE_REGADDR(ctxid, source);
 
    uint32_t current = *enable_reg;
    current = (current >> (source & 0x1F)) & 0x1;
    return current;
}
 
__STATIC_FORCEINLINE void PLIC_SetInterruptPending(uint32_t source)
{
    volatile uint32_t *pending_reg = (uint32_t *)PLIC_PENDING_REGADDR(source);
 
    uint32_t current = *pending_reg;
    current = current | (1UL << (source & 0x1F));
    *pending_reg = current;
}
 
__STATIC_FORCEINLINE void PLIC_ClearInterruptPending(uint32_t source)
{
    volatile uint32_t *pending_reg = (uint32_t *)PLIC_PENDING_REGADDR(source);
 
    uint32_t current = *pending_reg;
    current = current & (~(1UL << (source & 0x1F)));
    *pending_reg = current;
}
 
__STATIC_FORCEINLINE uint32_t PLIC_GetInterruptPending(uint32_t source)
{
    volatile uint32_t *pending_reg = (uint32_t *)PLIC_PENDING_REGADDR(source);
 
    uint32_t current = *pending_reg;
    current = (current >> (source & 0x1F)) & 0x1;
    return current;
}
 
__STATIC_FORCEINLINE void PLIC_SetPriority(uint32_t source, uint32_t priority)
{
    volatile uint32_t *priority_reg = (uint32_t *)PLIC_PRIORITY_REGADDR(source);
 
    *priority_reg = priority;
}
 
__STATIC_FORCEINLINE uint32_t PLIC_GetPriority(uint32_t source)
{
    volatile uint32_t *priority_reg = (uint32_t *)PLIC_PRIORITY_REGADDR(source);
 
    return (*priority_reg);
}
 
__STATIC_FORCEINLINE uint32_t PLIC_ClaimContextInterrupt(uint32_t ctxid)
{
    volatile uint32_t *claim_reg = (uint32_t *)PLIC_CLAIM_REGADDR(ctxid);
 
    return (*claim_reg);
}
 
__STATIC_FORCEINLINE void PLIC_CompleteContextInterrupt(uint32_t ctxid, uint32_t source)
{
    volatile uint32_t *complete_reg = (uint32_t *)PLIC_COMPLETE_REGADDR(ctxid);
 
    *complete_reg = source;
}
 
__STATIC_INLINE void PLIC_Context_Init(uint32_t ctxid, uint32_t num_sources, uint32_t enable, uint32_t thresh)
{
    uint32_t i;
 
    for (i = 0; i < num_sources; i ++) {
        if (enable) {
            PLIC_EnableContextInterrupt(ctxid, i);
        } else {
            PLIC_DisableContextInterrupt(ctxid, i);
        }
    }
    PLIC_SetContextThreshold(ctxid, thresh);
}
 
#define PLIC_Init(num_sources, enable, thresh)          PLIC_Context_Init(PLIC_GetHartMContextID(), (num_sources), (enable), (thresh))
#define PLIC_Init_S(num_sources, enable, thresh)        PLIC_Context_Init(PLIC_GetHartSContextID(), (num_sources), (enable), (thresh))
 
#define PLIC_ClaimInterrupt()                           PLIC_ClaimContextInterrupt(PLIC_GetHartMContextID())
#define PLIC_ClaimInterrupt_S()                         PLIC_ClaimContextInterrupt(PLIC_GetHartSContextID())
 
#define PLIC_CompleteInterrupt(source)                  PLIC_CompleteContextInterrupt(PLIC_GetHartMContextID(), (source))
#define PLIC_CompleteInterrupt_S(source)                PLIC_CompleteContextInterrupt(PLIC_GetHartSContextID(), (source))
 
#define PLIC_GetInterruptEnable(source)                 PLIC_GetContextInterruptEnable(PLIC_GetHartMContextID(), (source))
#define PLIC_GetInterruptEnable_S(source)               PLIC_GetContextInterruptEnable(PLIC_GetHartSContextID(), (source))
 
#define PLIC_EnableInterrupt(source)                    PLIC_EnableContextInterrupt(PLIC_GetHartMContextID(), (source))
#define PLIC_EnableInterrupt_S(source)                  PLIC_EnableContextInterrupt(PLIC_GetHartSContextID(), (source))
 
#define PLIC_DisableInterrupt(source)                   PLIC_DisableContextInterrupt(PLIC_GetHartMContextID(), (source))
#define PLIC_DisableInterrupt_S(source)                 PLIC_DisableContextInterrupt(PLIC_GetHartSContextID(), (source))
 
#define PLIC_SetThreshold(thresh)                       PLIC_SetContextThreshold(PLIC_GetHartMContextID(), (thresh))
#define PLIC_SetThreshold_S(thresh)                     PLIC_SetContextThreshold(PLIC_GetHartSContextID(), (thresh))
 
#define PLIC_GetThreshold()                             PLIC_GetContextThreshold(PLIC_GetHartMContextID())
#define PLIC_GetThreshold_S()                           PLIC_GetContextThreshold(PLIC_GetHartSContextID())
 
__STATIC_FORCEINLINE void __set_trap_entry(rv_csr_t addr)
{
    addr &= (rv_csr_t)(~0x7);
    __RV_CSR_WRITE(CSR_MTVEC, addr);
}
 
__STATIC_FORCEINLINE rv_csr_t __get_trap_entry(void)
{
    unsigned long addr = __RV_CSR_READ(CSR_MTVEC);
    return (addr);
}
 /* End of Doxygen Group NMSIS_Core_IntExc */
 
#endif /* defined(__PLIC_PRESENT) && (__PLIC_PRESENT == 1) */
 
#ifdef __cplusplus
}
#endif
#endif