(RV64 Only) SIMD 32bit Shift Instructions
 __STATIC_FORCEINLINE unsigned long __RV_KSLL32 (unsigned long a, unsigned int b)
 __STATIC_FORCEINLINE unsigned long __RV_KSLRA32 (unsigned long a, int b)
 __STATIC_FORCEINLINE unsigned long __RV_KSLRA32_U (unsigned long a, int b)
 __STATIC_FORCEINLINE unsigned long __RV_SLL32 (unsigned long a, unsigned int b)
 __STATIC_FORCEINLINE unsigned long __RV_SRA32 (unsigned long a, unsigned int b)
 __STATIC_FORCEINLINE unsigned long __RV_SRA32_U (unsigned long a, unsigned int b)
 __STATIC_FORCEINLINE unsigned long __RV_SRL32 (unsigned long a, unsigned int b)
 __STATIC_FORCEINLINE unsigned long __RV_SRL32_U (unsigned long a, unsigned int b)

__RV_KSLLI32(a, b)

__RV_SLLI32(a, b)

__RV_SRAI32(a, b)

__RV_SRAI32_U(a, b)

__RV_SRLI32(a, b)

__RV_SRLI32_U(a, b)
 group NMSIS_Core_DSP_Intrinsic_RV64_SIMD_32B_SHIFT
(RV64 Only) SIMD 32bit Shift Instructions
there are 14 (RV64 Only) SIMD 32bit Shift Instructions
Defines

__RV_KSLLI32(a, b)
KSLLI32 (SIMD 32bit Saturating Shift Left Logical Immediate)
Type: SIMD (RV64 Only)
Syntax:
KSLLI32 Rd, Rs1, imm5u
Purpose
:
Do 32bit elements logical left shift operations with saturation simultaneously. The shift amount is an immediate value.
Description
:
The 32bit data elements in Rs1 are leftshifted logically. The shifted out bits are filled with zero and the shift amount is specified by the imm5u constant. Any shifted value greater than 2^311 is saturated to 2^311. Any shifted value smaller than 2^31 is saturated to 2^31. And the saturated results are written to Rd. If any saturation is performed, set OV bit to 1.
Operations:
sa = imm5u[4:0]; if (sa != 0) { res[(31+sa):0] = Rs1.W[x] << sa; if (res > (2^31)1) { res = 0x7fffffff; OV = 1; } else if (res < 2^31) { res = 0x80000000; OV = 1; } Rd.W[x] = res[31:0]; } else { Rd = Rs1; } for RV64: x=1...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type

__RV_SLLI32(a, b)
SLLI32 (SIMD 32bit Shift Left Logical Immediate)
Type: SIMD (RV64 Only)
Syntax:
SLLI32 Rd, Rs1, imm5u[4:0]
Purpose
:
Do 32bit element logical left shift operations simultaneously. The shift amount is an immediate value.
Description
:
The 32bit elements in Rs1 are leftshifted logically. The shifted out bits are filled with zero and the shift amount is specified by the imm5u[4:0] constant. And the results are written to Rd.
Operations:
sa = imm5u[4:0]; Rd.W[x] = Rs1.W[x] << sa; for RV64: x=1...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type

__RV_SRAI32(a, b)
SRAI32 (SIMD 32bit Shift Right Arithmetic Immediate)
Type: DSP (RV64 Only)
Syntax:
SRAI32 Rd, Rs1, imm5u SRAI32.u Rd, Rs1, imm5u
Purpose
:
Do 32bit elements arithmetic right shift operations simultaneously. The shift amount is an immediate value. The
.u
form performs additional rounding up operations on the shifted results.Description
:
The 32bit data elements in Rs1 are rightshifted arithmetically, that is, the shifted out bits are filled with the signbit of the 32bit data elements. The shift amount is specified by the imm5u constant. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 32bit data to calculate the final results. And the results are written to Rd.Operations:
sa = imm5u[4:0]; if (sa > 0) { if (`.u` form) { // SRAI32.u res[31:1] = SE33(Rs1.W[x][31:sa1]) + 1; Rd.W[x] = res[31:0]; else { // SRAI32 Rd.W[x] = SE32(Rs1.W[x][31:sa]); } } else { Rd = Rs1; } for RV64: x=1...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type

__RV_SRAI32_U(a, b)
SRAI32.u (SIMD 32bit Rounding Shift Right Arithmetic Immediate)
Type: DSP (RV64 Only)
Syntax:
SRAI32 Rd, Rs1, imm5u SRAI32.u Rd, Rs1, imm5u
Purpose
:
Do 32bit elements arithmetic right shift operations simultaneously. The shift amount is an immediate value. The
.u
form performs additional rounding up operations on the shifted results.Description
:
The 32bit data elements in Rs1 are rightshifted arithmetically, that is, the shifted out bits are filled with the signbit of the 32bit data elements. The shift amount is specified by the imm5u constant. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 32bit data to calculate the final results. And the results are written to Rd.Operations:
sa = imm5u[4:0]; if (sa > 0) { if (`.u` form) { // SRAI32.u res[31:1] = SE33(Rs1.W[x][31:sa1]) + 1; Rd.W[x] = res[31:0]; else { // SRAI32 Rd.W[x] = SE32(Rs1.W[x][31:sa]); } } else { Rd = Rs1; } for RV64: x=1...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type

__RV_SRLI32(a, b)
SRLI32 (SIMD 32bit Shift Right Logical Immediate)
Type: SIMD (RV64 Only)
Syntax:
SRLI32 Rd, Rs1, imm5u SRLI32.u Rd, Rs1, imm5u
Purpose
:
Do 32bit elements logical right shift operations simultaneously. The shift amount is an immediate value. The
.u
form performs additional rounding up operations on the shifted results.Description
:
The 32bit data elements in Rs1 are rightshifted logically, that is, the shifted out bits are filled with zero. The shift amount is specified by the imm5u constant. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 32bit data to calculate the final results. And the results are written to Rd.Operations:
sa = imm5u[4:0]; if (sa > 0) { if (`.u` form) { // SRLI32.u res[31:1] = ZE33(Rs1.W[x][31:sa1]) + 1; Rd.W[x] = res[31:0]; else { // SRLI32 Rd.W[x] = ZE32(Rs1.W[x][31:sa]); } } else { Rd = Rs1; } for RV64: x=1...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type

__RV_SRLI32_U(a, b)
SRLI32.u (SIMD 32bit Rounding Shift Right Logical Immediate)
Type: SIMD (RV64 Only)
Syntax:
SRLI32 Rd, Rs1, imm5u SRLI32.u Rd, Rs1, imm5u
Purpose
:
Do 32bit elements logical right shift operations simultaneously. The shift amount is an immediate value. The
.u
form performs additional rounding up operations on the shifted results.Description
:
The 32bit data elements in Rs1 are rightshifted logically, that is, the shifted out bits are filled with zero. The shift amount is specified by the imm5u constant. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 32bit data to calculate the final results. And the results are written to Rd.Operations:
sa = imm5u[4:0]; if (sa > 0) { if (`.u` form) { // SRLI32.u res[31:1] = ZE33(Rs1.W[x][31:sa1]) + 1; Rd.W[x] = res[31:0]; else { // SRLI32 Rd.W[x] = ZE32(Rs1.W[x][31:sa]); } } else { Rd = Rs1; } for RV64: x=1...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type
Functions
 __STATIC_FORCEINLINE unsigned long __RV_KSLL32 (unsigned long a, unsigned int b)
KSLL32 (SIMD 32bit Saturating Shift Left Logical)
Type: SIMD (RV64 Only)
Syntax:
KSLL32 Rd, Rs1, Rs2
Purpose
:
Do 32bit elements logical left shift operations with saturation simultaneously. The shift amount is a variable from a GPR.
Description
:
The 32bit data elements in Rs1 are leftshifted logically. The shifted out bits are filled with zero and the shift amount is specified by the loworder 5bits of the value in the Rs2 register. Any shifted value greater than 2^311 is saturated to 2^311. Any shifted value smaller than 2^31 is saturated to 2^31. And the saturated results are written to Rd. If any saturation is performed, set OV bit to 1.
Operations:
sa = Rs2[4:0]; if (sa != 0) { res[(31+sa):0] = Rs1.W[x] << sa; if (res > (2^31)1) { res = 0x7fffffff; OV = 1; } else if (res < 2^31) { res = 0x80000000; OV = 1; } Rd.W[x] = res[31:0]; } else { Rd = Rs1; } for RV64: x=1...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type
 __STATIC_FORCEINLINE unsigned long __RV_KSLRA32 (unsigned long a, int b)
KSLRA32 (SIMD 32bit Shift Left Logical with Saturation or Shift Right Arithmetic)
Type: SIMD (RV64 Only)
Syntax:
KSLRA32 Rd, Rs1, Rs2 KSLRA32.u Rd, Rs1, Rs2
Purpose
:
Do 32bit elements logical left (positive) or arithmetic right (negative) shift operation with Q31 saturation for the left shift. The
.u
form performs additional rounding up operations for the right shift.Description
:
The 32bit data elements of Rs1 are leftshifted logically or rightshifted arithmetically based on the value of Rs2[5:0]. Rs2[5:0] is in the signed range of [25, 251]. A positive Rs2[5:0] means logical left shift and a negative Rs2[5:0] means arithmetic right shift. The shift amount is the absolute value of Rs2[5:0]. However, the behavior of
Rs2[5:0]==25 (0x20)
is defined to be equivalent to the behavior ofRs2[5:0]==(251) (0x21)
. The leftshifted results are saturated to the 32bit signed integer range of [2^31, 2^311]. For the.u
form of the instruction, the rightshifted results are added a 1 to the most significant discarded bit position for rounding effect. After the shift, saturation, or rounding, the final results are written to Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:6] will not affect this instruction.Operations:
if (Rs2[5:0] < 0) { sa = Rs2[5:0]; sa = (sa == 32)? 31 : sa; if (`.u` form) { res[31:1] = SE33(Rs1.W[x][31:sa1]) + 1; Rd.W[x] = res[31:0]; } else { Rd.W[x] = SE32(Rs1.W[x][31:sa]); } } else { sa = Rs2[4:0]; res[(31+sa):0] = Rs1.W[x] <<(logic) sa; if (res > (2^31)1) { res[31:0] = 0x7fffffff; OV = 1; } else if (res < 2^31) { res[31:0] = 0x80000000; OV = 1; } Rd.W[x] = res[31:0]; } for RV64: x=1...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] int type of value stored in b
 Returns
value stored in unsigned long type
 __STATIC_FORCEINLINE unsigned long __RV_KSLRA32_U (unsigned long a, int b)
KSLRA32.u (SIMD 32bit Shift Left Logical with Saturation or Rounding Shift Right Arithmetic)
Type: SIMD (RV64 Only)
Syntax:
KSLRA32 Rd, Rs1, Rs2 KSLRA32.u Rd, Rs1, Rs2
Purpose
:
Do 32bit elements logical left (positive) or arithmetic right (negative) shift operation with Q31 saturation for the left shift. The
.u
form performs additional rounding up operations for the right shift.Description
:
The 32bit data elements of Rs1 are leftshifted logically or rightshifted arithmetically based on the value of Rs2[5:0]. Rs2[5:0] is in the signed range of [25, 251]. A positive Rs2[5:0] means logical left shift and a negative Rs2[5:0] means arithmetic right shift. The shift amount is the absolute value of Rs2[5:0]. However, the behavior of
Rs2[5:0]==25 (0x20)
is defined to be equivalent to the behavior ofRs2[5:0]==(251) (0x21)
. The leftshifted results are saturated to the 32bit signed integer range of [2^31, 2^311]. For the.u
form of the instruction, the rightshifted results are added a 1 to the most significant discarded bit position for rounding effect. After the shift, saturation, or rounding, the final results are written to Rd. If any saturation happens, this instruction sets the OV flag. The value of Rs2[31:6] will not affect this instruction.Operations:
if (Rs2[5:0] < 0) { sa = Rs2[5:0]; sa = (sa == 32)? 31 : sa; if (`.u` form) { res[31:1] = SE33(Rs1.W[x][31:sa1]) + 1; Rd.W[x] = res[31:0]; } else { Rd.W[x] = SE32(Rs1.W[x][31:sa]); } } else { sa = Rs2[4:0]; res[(31+sa):0] = Rs1.W[x] <<(logic) sa; if (res > (2^31)1) { res[31:0] = 0x7fffffff; OV = 1; } else if (res < 2^31) { res[31:0] = 0x80000000; OV = 1; } Rd.W[x] = res[31:0]; } for RV64: x=1...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] int type of value stored in b
 Returns
value stored in unsigned long type
 __STATIC_FORCEINLINE unsigned long __RV_SLL32 (unsigned long a, unsigned int b)
SLL32 (SIMD 32bit Shift Left Logical)
Type: SIMD (RV64 Only)
Syntax:
SLL32 Rd, Rs1, Rs2
Purpose
:
Do 32bit elements logical left shift operations simultaneously. The shift amount is a variable from a GPR.
Description
:
The 32bit elements in Rs1 are leftshifted logically. And the results are written to Rd. The shifted out bits are filled with zero and the shift amount is specified by the loworder 5bits of the value in the Rs2 register.
Operations:
sa = Rs2[4:0]; Rd.W[x] = Rs1.W[x] << sa; for RV64: x=1...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type
 __STATIC_FORCEINLINE unsigned long __RV_SRA32 (unsigned long a, unsigned int b)
SRA32 (SIMD 32bit Shift Right Arithmetic)
Type: SIMD (RV64 Only)
Syntax:
SRA32 Rd, Rs1, Rs2 SRA32.u Rd, Rs1, Rs2
Purpose
:
Do 32bit element arithmetic right shift operations simultaneously. The shift amount is a variable from a GPR. The
.u
form performs additional rounding up operations on the shifted results.Description
:
The 32bit data elements in Rs1 are rightshifted arithmetically, that is, the shifted out bits are filled with the signbit of the data elements. The shift amount is specified by the loworder 5bits of the value in the Rs2 register. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 32bit data element to calculate the final results. And the results are written to Rd.Operations:
sa = Rs2[4:0]; if (sa > 0) { if (`.u` form) { // SRA32.u res[31:1] = SE33(Rs1.W[x][31:sa1]) + 1; Rd.W[x] = res[31:0]; else { // SRA32 Rd.W[x] = SE32(Rs1.W[x][31:sa]) } } else { Rd = Rs1; } for RV64: x=1...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type
 __STATIC_FORCEINLINE unsigned long __RV_SRA32_U (unsigned long a, unsigned int b)
SRA32.u (SIMD 32bit Rounding Shift Right Arithmetic)
Type: SIMD (RV64 Only)
Syntax:
SRA32 Rd, Rs1, Rs2 SRA32.u Rd, Rs1, Rs2
Purpose
:
Do 32bit element arithmetic right shift operations simultaneously. The shift amount is a variable from a GPR. The
.u
form performs additional rounding up operations on the shifted results.Description
:
The 32bit data elements in Rs1 are rightshifted arithmetically, that is, the shifted out bits are filled with the signbit of the data elements. The shift amount is specified by the loworder 5bits of the value in the Rs2 register. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 32bit data element to calculate the final results. And the results are written to Rd.Operations:
sa = Rs2[4:0]; if (sa > 0) { if (`.u` form) { // SRA32.u res[31:1] = SE33(Rs1.W[x][31:sa1]) + 1; Rd.W[x] = res[31:0]; else { // SRA32 Rd.W[x] = SE32(Rs1.W[x][31:sa]) } } else { Rd = Rs1; } for RV64: x=1...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type
 __STATIC_FORCEINLINE unsigned long __RV_SRL32 (unsigned long a, unsigned int b)
SRL32 (SIMD 32bit Shift Right Logical)
Type: SIMD (RV64 Only)
Syntax:
SRL32 Rd, Rs1, Rs2 SRL32.u Rd, Rs1, Rs2
Purpose
:
Do 32bit element logical right shift operations simultaneously. The shift amount is a variable from a GPR. The
.u
form performs additional rounding up operations on the shifted results.Description
:
The 32bit data elements in Rs1 are rightshifted logically, that is, the shifted out bits are filled with zero. The shift amount is specified by the loworder 5bits of the value in the Rs2 register. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 32bit data element to calculate the final results. And the results are written to Rd.Operations:
sa = Rs2[4:0]; if (sa > 0) { if (`.u` form) { // SRA32.u res[31:1] = ZE33(Rs1.W[x][31:sa1]) + 1; Rd.W[x] = res[31:0]; else { // SRA32 Rd.W[x] = ZE32(Rs1.W[x][31:sa]) } } else { Rd = Rs1; } for RV64: x=1...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type
 __STATIC_FORCEINLINE unsigned long __RV_SRL32_U (unsigned long a, unsigned int b)
SRL32.u (SIMD 32bit Rounding Shift Right Logical)
Type: SIMD (RV64 Only)
Syntax:
SRL32 Rd, Rs1, Rs2 SRL32.u Rd, Rs1, Rs2
Purpose
:
Do 32bit element logical right shift operations simultaneously. The shift amount is a variable from a GPR. The
.u
form performs additional rounding up operations on the shifted results.Description
:
The 32bit data elements in Rs1 are rightshifted logically, that is, the shifted out bits are filled with zero. The shift amount is specified by the loworder 5bits of the value in the Rs2 register. For the rounding operation of the
.u
form, a value of 1 is added to the most significant discarded bit of each 32bit data element to calculate the final results. And the results are written to Rd.Operations:
sa = Rs2[4:0]; if (sa > 0) { if (`.u` form) { // SRA32.u res[31:1] = ZE33(Rs1.W[x][31:sa1]) + 1; Rd.W[x] = res[31:0]; else { // SRA32 Rd.W[x] = ZE32(Rs1.W[x][31:sa]) } } else { Rd = Rs1; } for RV64: x=1...0
 Parameters
a – [in] unsigned long type of value stored in a
b – [in] unsigned int type of value stored in b
 Returns
value stored in unsigned long type

__RV_KSLLI32(a, b)