NMSIS-Core  Version 1.6.0
NMSIS-Core support for Nuclei processor-based devices
Macros | Functions
ECC Functions

Functions that related to the ECC feature. More...

Macros

#define ECC_ERROR_RAMID_MASK_ICACHE   1U
 
#define ECC_ERROR_RAMID_MASK_DCACHE   2U
 
#define ECC_ERROR_RAMID_MASK_TLB   4U
 
#define ECC_ERROR_RAMID_MASK_ILM   8U
 
#define ECC_ERROR_RAMID_MASK_DLM   16U
 

Functions

__STATIC_FORCEINLINE int32_t ECC_IsGlobalSupportECC (void)
 Check if the core globally supports ECC. More...
 
__STATIC_FORCEINLINE int32_t ECC_IsICacheSupportECC (void)
 Check if I-Cache supports ECC. More...
 
__STATIC_FORCEINLINE int32_t ECC_IsDCacheSupportECC (void)
 Check if D-Cache supports ECC. More...
 
__STATIC_FORCEINLINE int32_t ECC_IsTLBSupportECC (void)
 Check if TLB supports ECC. More...
 
__STATIC_FORCEINLINE int32_t ECC_IsILMSupportECC (void)
 Check if ILM supports ECC. More...
 
__STATIC_FORCEINLINE int32_t ECC_IsDLMSupportECC (void)
 Check if DLM supports ECC. More...
 
__STATIC_FORCEINLINE int32_t ECC_IsXorErrorInjectMode (void)
 Check if XOR error injection mode is supported. More...
 
__STATIC_FORCEINLINE void ECC_EnableICacheECC (void)
 Enable ECC for I-Cache. More...
 
__STATIC_FORCEINLINE void ECC_DisableICacheECC (void)
 Disable ECC for I-Cache. More...
 
__STATIC_FORCEINLINE void ECC_EnableICacheECCExcp (void)
 Enable ECC exception for I-Cache. More...
 
__STATIC_FORCEINLINE void ECC_DisableICacheECCExcp (void)
 Disable ECC exception for I-Cache. More...
 
__STATIC_FORCEINLINE void ECC_EnableICacheECCCheck (void)
 Enable ECC checking for I-Cache. More...
 
__STATIC_FORCEINLINE void ECC_DisableICacheECCCheck (void)
 Disable ECC checking for I-Cache. More...
 
__STATIC_FORCEINLINE void ECC_EnableDCacheECC (void)
 Enable ECC for D-Cache. More...
 
__STATIC_FORCEINLINE void ECC_DisableDCacheECC (void)
 Disable ECC for D-Cache. More...
 
__STATIC_FORCEINLINE void ECC_EnableDCacheECCExcp (void)
 Enable ECC exception for D-Cache. More...
 
__STATIC_FORCEINLINE void ECC_DisableDCacheECCExcp (void)
 Disable ECC exception for D-Cache. More...
 
__STATIC_FORCEINLINE void ECC_EnableDCacheECCCheck (void)
 Enable ECC checking for D-Cache. More...
 
__STATIC_FORCEINLINE void ECC_DisableDCacheECCCheck (void)
 Disable ECC checking for D-Cache. More...
 
__STATIC_FORCEINLINE void ECC_ICacheTRamErrInject (uint32_t ecc_code, void *addr)
 Inject error into I-Cache Tag RAM. More...
 
__STATIC_FORCEINLINE void ECC_ICacheDRamErrInject (uint32_t ecc_code, void *addr)
 Inject error into I-Cache Data RAM. More...
 
__STATIC_FORCEINLINE void ECC_ICacheErrRestore (void *addr)
 Restore I-Cache error at specified address. More...
 
__STATIC_FORCEINLINE void ECC_DCacheTRamErrInject (uint32_t ecc_code, void *addr)
 Inject error into D-Cache Tag RAM. More...
 
__STATIC_FORCEINLINE void ECC_DCacheDRamErrInject (uint32_t ecc_code, void *addr)
 Inject error into D-Cache Data RAM. More...
 
__STATIC_FORCEINLINE void ECC_DCacheErrRestore (void *addr)
 Restore D-Cache error at specified address. More...
 
__STATIC_FORCEINLINE void ECC_EnableILM (void)
 Enable ILM. More...
 
__STATIC_FORCEINLINE void ECC_DisableILM (void)
 Disable ILM. More...
 
__STATIC_FORCEINLINE void ECC_EnableILMECC (void)
 Enable ECC for ILM. More...
 
__STATIC_FORCEINLINE void ECC_DisableILMECC (void)
 Disable ECC for ILM. More...
 
__STATIC_FORCEINLINE void ECC_EnableILMECCExcp (void)
 Enable ECC exception for ILM. More...
 
__STATIC_FORCEINLINE void ECC_DisableILMECCExcp (void)
 Disable ECC exception for ILM. More...
 
__STATIC_FORCEINLINE void ECC_EnableILMECCCheck (void)
 Enable ECC checking for ILM. More...
 
__STATIC_FORCEINLINE void ECC_DisableILMECCCheck (void)
 Disable ECC checking for ILM. More...
 
__STATIC_FORCEINLINE void ECC_ILMErrInject (uint32_t ecc_code, void *addr)
 Inject error into ILM. More...
 
__STATIC_FORCEINLINE void ECC_ILMErrRestore (void *addr)
 Restore ILM error at specified address. More...
 
__STATIC_FORCEINLINE void ECC_EnableDLM (void)
 Enable DLM. More...
 
__STATIC_FORCEINLINE void ECC_DisableDLM (void)
 Disable DLM. More...
 
__STATIC_FORCEINLINE void ECC_EnableDLMECC (void)
 Enable ECC for DLM. More...
 
__STATIC_FORCEINLINE void ECC_DisableDLMECC (void)
 Disable ECC for DLM. More...
 
__STATIC_FORCEINLINE void ECC_EnableDLMECCExcp (void)
 Enable ECC exception for DLM. More...
 
__STATIC_FORCEINLINE void ECC_DisableDLMECCExcp (void)
 Disable ECC exception for DLM. More...
 
__STATIC_FORCEINLINE void ECC_EnableDLMECCCheck (void)
 Enable ECC checking for DLM. More...
 
__STATIC_FORCEINLINE void ECC_DisableDLMECCCheck (void)
 Disable ECC checking for DLM. More...
 
__STATIC_FORCEINLINE void ECC_DLMErrInject (uint32_t ecc_code, void *addr)
 Inject error into DLM. More...
 
__STATIC_FORCEINLINE void ECC_DLMErrRestore (void *addr)
 Restore DLM error at specified address. More...
 
__STATIC_FORCEINLINE int32_t ECC_IsAnySingleBitErrorOccured (void)
 Check if any single-bit error has occurred. More...
 
__STATIC_FORCEINLINE int32_t ECC_IsICacheSingleBitErrorOccured (void)
 Check if I-Cache single-bit error has occurred. More...
 
__STATIC_FORCEINLINE int32_t ECC_IsDCacheSingleBitErrorOccured (void)
 Check if D-Cache single-bit error has occurred. More...
 
__STATIC_FORCEINLINE int32_t ECC_IsTLBSingleBitErrorOccured (void)
 Check if TLB single-bit error has occurred. More...
 
__STATIC_FORCEINLINE int32_t ECC_IsILMSingleBitErrorOccured (void)
 Check if ILM single-bit error has occurred. More...
 
__STATIC_FORCEINLINE int32_t ECC_IsDLMSingleBitErrorOccured (void)
 Check if DLM single-bit error has occurred. More...
 
__STATIC_FORCEINLINE void ECC_ClearAllSingleBitError (void)
 Clear all single-bit errors. More...
 
__STATIC_FORCEINLINE void ECC_ClearICacheSingleBitError (void)
 Clear I-Cache single-bit error. More...
 
__STATIC_FORCEINLINE void ECC_ClearDCacheSingleBitError (void)
 Clear D-Cache single-bit error. More...
 
__STATIC_FORCEINLINE void ECC_ClearTLBSingleBitError (void)
 Clear TLB single-bit error. More...
 
__STATIC_FORCEINLINE void ECC_ClearILMSingleBitError (void)
 Clear ILM single-bit error. More...
 
__STATIC_FORCEINLINE void ECC_ClearDLMSingleBitError (void)
 Clear DLM single-bit error. More...
 
__STATIC_FORCEINLINE int32_t ECC_IsAnyDoubleBitErrorOccured (void)
 Check if any double-bit error has occurred. More...
 
__STATIC_FORCEINLINE int32_t ECC_IsICacheDoubleBitErrorOccured (void)
 Check if I-Cache double-bit error has occurred. More...
 
__STATIC_FORCEINLINE int32_t ECC_IsDCacheDoubleBitErrorOccured (void)
 Check if D-Cache double-bit error has occurred. More...
 
__STATIC_FORCEINLINE int32_t ECC_IsTLBDoubleBitErrorOccured (void)
 Check if TLB double-bit error has occurred. More...
 
__STATIC_FORCEINLINE int32_t ECC_IsILMDoubleBitErrorOccured (void)
 Check if ILM double-bit error has occurred. More...
 
__STATIC_FORCEINLINE int32_t ECC_IsDLMDoubleBitErrorOccured (void)
 Check if DLM double-bit error has occurred. More...
 
__STATIC_FORCEINLINE void ECC_ClearAllDoubleBitError (void)
 Clear all double-bit errors. More...
 
__STATIC_FORCEINLINE void ECC_ClearICacheDoubleBitError (void)
 Clear I-Cache double-bit error. More...
 
__STATIC_FORCEINLINE void ECC_ClearDCacheDoubleBitError (void)
 Clear D-Cache double-bit error. More...
 
__STATIC_FORCEINLINE void ECC_ClearTLBDoubleBitError (void)
 Clear TLB double-bit error. More...
 
__STATIC_FORCEINLINE void ECC_ClearILMDoubleBitError (void)
 Clear ILM double-bit error. More...
 
__STATIC_FORCEINLINE void ECC_ClearDLMDoubleBitError (void)
 Clear DLM double-bit error. More...
 
static uint8_t ECC_GenerateECCCodeU32 (uint32_t a)
 Generate ECC code for a 32-bit value. More...
 
static uint8_t ECC_GenerateECCCodeU64 (uint64_t a)
 Generate ECC code for a 64-bit value. More...
 

Detailed Description

Functions that related to the ECC feature.

These functions provide access to the Error Correction Code (ECC) feature available in Nuclei N/NX processor cores. ECC is a memory protection mechanism that can detect and correct single-bit errors and detect double-bit errors in memory systems such as caches and local memories.

The ECC feature includes:

Macro Definition Documentation

◆ ECC_ERROR_RAMID_MASK_DCACHE

#define ECC_ERROR_RAMID_MASK_DCACHE   2U

Definition at line 652 of file core_feature_ecc.h.

◆ ECC_ERROR_RAMID_MASK_DLM

#define ECC_ERROR_RAMID_MASK_DLM   16U

Definition at line 655 of file core_feature_ecc.h.

◆ ECC_ERROR_RAMID_MASK_ICACHE

#define ECC_ERROR_RAMID_MASK_ICACHE   1U

Definition at line 651 of file core_feature_ecc.h.

◆ ECC_ERROR_RAMID_MASK_ILM

#define ECC_ERROR_RAMID_MASK_ILM   8U

Definition at line 654 of file core_feature_ecc.h.

◆ ECC_ERROR_RAMID_MASK_TLB

#define ECC_ERROR_RAMID_MASK_TLB   4U

Definition at line 653 of file core_feature_ecc.h.

Function Documentation

◆ ECC_ClearAllDoubleBitError()

__STATIC_FORCEINLINE void ECC_ClearAllDoubleBitError ( void  )

Clear all double-bit errors.

This function clears all double-bit errors by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 885 of file core_feature_ecc.h.

886 {
887  __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_RAMID);
888 }

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_RAMID.

◆ ECC_ClearAllSingleBitError()

__STATIC_FORCEINLINE void ECC_ClearAllSingleBitError ( void  )

Clear all single-bit errors.

This function clears all single-bit errors by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 741 of file core_feature_ecc.h.

742 {
743  __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_SRAMID);
744 }

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_SRAMID.

◆ ECC_ClearDCacheDoubleBitError()

__STATIC_FORCEINLINE void ECC_ClearDCacheDoubleBitError ( void  )

Clear D-Cache double-bit error.

This function clears the double-bit error in the D-Cache by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 907 of file core_feature_ecc.h.

908 {
909  __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_RAMID_DC);
910 }

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_RAMID_DC.

◆ ECC_ClearDCacheSingleBitError()

__STATIC_FORCEINLINE void ECC_ClearDCacheSingleBitError ( void  )

Clear D-Cache single-bit error.

This function clears the single-bit error in the D-Cache by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 763 of file core_feature_ecc.h.

764 {
765  __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_SRAMID_DC);
766 }

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_SRAMID_DC.

◆ ECC_ClearDLMDoubleBitError()

__STATIC_FORCEINLINE void ECC_ClearDLMDoubleBitError ( void  )

Clear DLM double-bit error.

This function clears the double-bit error in the DLM by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 940 of file core_feature_ecc.h.

941 {
942  __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_RAMID_DLM);
943 }

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_RAMID_DLM.

◆ ECC_ClearDLMSingleBitError()

__STATIC_FORCEINLINE void ECC_ClearDLMSingleBitError ( void  )

Clear DLM single-bit error.

This function clears the single-bit error in the DLM by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 796 of file core_feature_ecc.h.

797 {
798  __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_SRAMID_DLM);
799 }

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_SRAMID_DLM.

◆ ECC_ClearICacheDoubleBitError()

__STATIC_FORCEINLINE void ECC_ClearICacheDoubleBitError ( void  )

Clear I-Cache double-bit error.

This function clears the double-bit error in the I-Cache by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 896 of file core_feature_ecc.h.

897 {
898  __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_RAMID_IC);
899 }

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_RAMID_IC.

◆ ECC_ClearICacheSingleBitError()

__STATIC_FORCEINLINE void ECC_ClearICacheSingleBitError ( void  )

Clear I-Cache single-bit error.

This function clears the single-bit error in the I-Cache by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 752 of file core_feature_ecc.h.

753 {
754  __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_SRAMID_IC);
755 }

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_SRAMID_IC.

◆ ECC_ClearILMDoubleBitError()

__STATIC_FORCEINLINE void ECC_ClearILMDoubleBitError ( void  )

Clear ILM double-bit error.

This function clears the double-bit error in the ILM by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 929 of file core_feature_ecc.h.

930 {
931  __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_RAMID_ILM);
932 }

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_RAMID_ILM.

◆ ECC_ClearILMSingleBitError()

__STATIC_FORCEINLINE void ECC_ClearILMSingleBitError ( void  )

Clear ILM single-bit error.

This function clears the single-bit error in the ILM by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 785 of file core_feature_ecc.h.

786 {
787  __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_SRAMID_ILM);
788 }

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_SRAMID_ILM.

◆ ECC_ClearTLBDoubleBitError()

__STATIC_FORCEINLINE void ECC_ClearTLBDoubleBitError ( void  )

Clear TLB double-bit error.

This function clears the double-bit error in the TLB by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 918 of file core_feature_ecc.h.

919 {
920  __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_RAMID_TLB);
921 }

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_RAMID_TLB.

◆ ECC_ClearTLBSingleBitError()

__STATIC_FORCEINLINE void ECC_ClearTLBSingleBitError ( void  )

Clear TLB single-bit error.

This function clears the single-bit error in the TLB by clearing the appropriate bits in the machine ECC code CSR.

Definition at line 774 of file core_feature_ecc.h.

775 {
776  __RV_CSR_CLEAR(CSR_MECC_CODE, MECC_CODE_SRAMID_TLB);
777 }

References __RV_CSR_CLEAR, CSR_MECC_CODE, and MECC_CODE_SRAMID_TLB.

◆ ECC_DCacheDRamErrInject()

__STATIC_FORCEINLINE void ECC_DCacheDRamErrInject ( uint32_t  ecc_code,
void *  addr 
)

Inject error into D-Cache Data RAM.

This function injects an error into the D-Cache Data RAM at the specified address with the given ECC code.

Parameters
[in]ecc_codeECC code to inject
[in]addrAddress where error should be injected

Definition at line 386 of file core_feature_ecc.h.

387 {
388  /* Write ecc_code into mecc_code csr also clear all error status */
389  __RV_CSR_WRITE(CSR_MECC_CODE, ecc_code);
390  ECC_DisableDCacheECCCheck();
391  MFlushInvalDCacheLine((unsigned long)addr);
392  __RWMB();
393  __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_DC_DRAM_ECC_INJ_EN);
394  __LW(addr);
395  __RWMB();
396  __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_DC_DRAM_ECC_INJ_EN);
397  __RWMB();
398  ECC_EnableDCacheECCCheck();
399 }

References __LW(), __RV_CSR_CLEAR, __RV_CSR_SET, __RV_CSR_WRITE, __RWMB, CSR_MCACHE_CTL, CSR_MECC_CODE, ECC_DisableDCacheECCCheck(), ECC_EnableDCacheECCCheck(), MCACHE_CTL_DC_DRAM_ECC_INJ_EN, and MFlushInvalDCacheLine().

◆ ECC_DCacheErrRestore()

__STATIC_FORCEINLINE void ECC_DCacheErrRestore ( void *  addr)

Restore D-Cache error at specified address.

This function restores the correct ECC code for the D-Cache line at the specified address.

Parameters
[in]addrAddress to restore

Definition at line 407 of file core_feature_ecc.h.

408 {
409  ECC_DisableDCacheECCCheck();
410  MFlushInvalDCacheLine((unsigned long)addr);
411  MLockDCacheLine((unsigned long)addr);
412  ECC_EnableDCacheECCCheck();
413 }

References ECC_DisableDCacheECCCheck(), ECC_EnableDCacheECCCheck(), MFlushInvalDCacheLine(), and MLockDCacheLine().

◆ ECC_DCacheTRamErrInject()

__STATIC_FORCEINLINE void ECC_DCacheTRamErrInject ( uint32_t  ecc_code,
void *  addr 
)

Inject error into D-Cache Tag RAM.

This function injects an error into the D-Cache Tag RAM at the specified address with the given ECC code.

Parameters
[in]ecc_codeECC code to inject
[in]addrAddress where error should be injected

Definition at line 363 of file core_feature_ecc.h.

364 {
365  /* Write ecc_code into mecc_code csr also clear all error status */
366  __RV_CSR_WRITE(CSR_MECC_CODE, ecc_code);
367  ECC_DisableDCacheECCCheck();
368  MFlushInvalDCacheLine((unsigned long)addr);
369  __RWMB();
370  __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_DC_TRAM_ECC_INJ_EN);
371  __LW(addr);
372  __RWMB();
373  __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_DC_TRAM_ECC_INJ_EN);
374  __RWMB();
375  ECC_EnableDCacheECCCheck();
376 }

References __LW(), __RV_CSR_CLEAR, __RV_CSR_SET, __RV_CSR_WRITE, __RWMB, CSR_MCACHE_CTL, CSR_MECC_CODE, ECC_DisableDCacheECCCheck(), ECC_EnableDCacheECCCheck(), MCACHE_CTL_DC_TRAM_ECC_INJ_EN, and MFlushInvalDCacheLine().

◆ ECC_DisableDCacheECC()

__STATIC_FORCEINLINE void ECC_DisableDCacheECC ( void  )

Disable ECC for D-Cache.

This function disables ECC for the data cache by clearing the appropriate bit in the machine cache control CSR.

Definition at line 249 of file core_feature_ecc.h.

250 {
251  __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_DC_ECC_EN);
252 }

References __RV_CSR_CLEAR, CSR_MCACHE_CTL, and MCACHE_CTL_DC_ECC_EN.

◆ ECC_DisableDCacheECCCheck()

__STATIC_FORCEINLINE void ECC_DisableDCacheECCCheck ( void  )

Disable ECC checking for D-Cache.

This function disables ECC checking for the data cache by clearing the appropriate bit in the machine cache control CSR.

Definition at line 293 of file core_feature_ecc.h.

294 {
295  __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_DC_ECC_CHK_EN);
296 }

References __RV_CSR_CLEAR, CSR_MCACHE_CTL, and MCACHE_CTL_DC_ECC_CHK_EN.

Referenced by ECC_DCacheDRamErrInject(), ECC_DCacheErrRestore(), and ECC_DCacheTRamErrInject().

◆ ECC_DisableDCacheECCExcp()

__STATIC_FORCEINLINE void ECC_DisableDCacheECCExcp ( void  )

Disable ECC exception for D-Cache.

This function disables ECC exception for the data cache by clearing the appropriate bit in the machine cache control CSR.

Definition at line 271 of file core_feature_ecc.h.

272 {
273  __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_DC_ECC_EXCP_EN);
274 }

References __RV_CSR_CLEAR, CSR_MCACHE_CTL, and MCACHE_CTL_DC_ECC_EXCP_EN.

◆ ECC_DisableDLM()

__STATIC_FORCEINLINE void ECC_DisableDLM ( void  )

Disable DLM.

This function disables DLM by clearing the appropriate bit in the machine DLM control CSR.

Definition at line 549 of file core_feature_ecc.h.

550 {
551  __RV_CSR_CLEAR(CSR_MDLM_CTL, MDLM_CTL_DLM_EN);
552 }

References __RV_CSR_CLEAR, CSR_MDLM_CTL, and MDLM_CTL_DLM_EN.

◆ ECC_DisableDLMECC()

__STATIC_FORCEINLINE void ECC_DisableDLMECC ( void  )

Disable ECC for DLM.

This function disables ECC for DLM by clearing the appropriate bit in the machine DLM control CSR.

Definition at line 569 of file core_feature_ecc.h.

570 {
571  __RV_CSR_CLEAR(CSR_MDLM_CTL, MDLM_CTL_DLM_ECC_EN);
572 }

References __RV_CSR_CLEAR, CSR_MDLM_CTL, and MDLM_CTL_DLM_ECC_EN.

◆ ECC_DisableDLMECCCheck()

__STATIC_FORCEINLINE void ECC_DisableDLMECCCheck ( void  )

Disable ECC checking for DLM.

This function disables ECC checking for DLM by clearing the appropriate bit in the machine DLM control CSR.

Definition at line 609 of file core_feature_ecc.h.

610 {
611  __RV_CSR_CLEAR(CSR_MDLM_CTL, MDLM_CTL_DLM_ECC_CHK_EN);
612 }

References __RV_CSR_CLEAR, CSR_MDLM_CTL, and MDLM_CTL_DLM_ECC_CHK_EN.

Referenced by ECC_DLMErrInject(), and ECC_DLMErrRestore().

◆ ECC_DisableDLMECCExcp()

__STATIC_FORCEINLINE void ECC_DisableDLMECCExcp ( void  )

Disable ECC exception for DLM.

This function disables ECC exception for DLM by clearing the appropriate bit in the machine DLM control CSR.

Definition at line 589 of file core_feature_ecc.h.

590 {
591  __RV_CSR_CLEAR(CSR_MDLM_CTL, MDLM_CTL_DLM_ECC_EXCP_EN);
592 }

References __RV_CSR_CLEAR, CSR_MDLM_CTL, and MDLM_CTL_DLM_ECC_EXCP_EN.

◆ ECC_DisableICacheECC()

__STATIC_FORCEINLINE void ECC_DisableICacheECC ( void  )

Disable ECC for I-Cache.

This function disables ECC for the instruction cache by clearing the appropriate bit in the machine cache control CSR.

Definition at line 183 of file core_feature_ecc.h.

184 {
185  __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_IC_ECC_EN);
186 }

References __RV_CSR_CLEAR, CSR_MCACHE_CTL, and MCACHE_CTL_IC_ECC_EN.

◆ ECC_DisableICacheECCCheck()

__STATIC_FORCEINLINE void ECC_DisableICacheECCCheck ( void  )

Disable ECC checking for I-Cache.

This function disables ECC checking for the instruction cache by clearing the appropriate bit in the machine cache control CSR.

Definition at line 227 of file core_feature_ecc.h.

228 {
229  __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_IC_ECC_CHK_EN);
230 }

References __RV_CSR_CLEAR, CSR_MCACHE_CTL, and MCACHE_CTL_IC_ECC_CHK_EN.

◆ ECC_DisableICacheECCExcp()

__STATIC_FORCEINLINE void ECC_DisableICacheECCExcp ( void  )

Disable ECC exception for I-Cache.

This function disables ECC exception for the instruction cache by clearing the appropriate bit in the machine cache control CSR.

Definition at line 205 of file core_feature_ecc.h.

206 {
207  __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_IC_ECC_EXCP_EN);
208 }

References __RV_CSR_CLEAR, CSR_MCACHE_CTL, and MCACHE_CTL_IC_ECC_EXCP_EN.

◆ ECC_DisableILM()

__STATIC_FORCEINLINE void ECC_DisableILM ( void  )

Disable ILM.

This function disables ILM by clearing the appropriate bit in the machine ILM control CSR.

Definition at line 432 of file core_feature_ecc.h.

433 {
434  __RV_CSR_CLEAR(CSR_MILM_CTL, MILM_CTL_ILM_EN);
435 }

References __RV_CSR_CLEAR, CSR_MILM_CTL, and MILM_CTL_ILM_EN.

◆ ECC_DisableILMECC()

__STATIC_FORCEINLINE void ECC_DisableILMECC ( void  )

Disable ECC for ILM.

This function disables ECC for ILM by clearing the appropriate bit in the machine ILM control CSR.

Definition at line 452 of file core_feature_ecc.h.

453 {
454  __RV_CSR_CLEAR(CSR_MILM_CTL, MILM_CTL_ILM_ECC_EN);
455 }

References __RV_CSR_CLEAR, CSR_MILM_CTL, and MILM_CTL_ILM_ECC_EN.

◆ ECC_DisableILMECCCheck()

__STATIC_FORCEINLINE void ECC_DisableILMECCCheck ( void  )

Disable ECC checking for ILM.

This function disables ECC checking for ILM by clearing the appropriate bit in the machine ILM control CSR.

Definition at line 492 of file core_feature_ecc.h.

493 {
494  __RV_CSR_CLEAR(CSR_MILM_CTL, MILM_CTL_ILM_ECC_CHK_EN);
495 }

References __RV_CSR_CLEAR, CSR_MILM_CTL, and MILM_CTL_ILM_ECC_CHK_EN.

Referenced by ECC_ILMErrInject(), and ECC_ILMErrRestore().

◆ ECC_DisableILMECCExcp()

__STATIC_FORCEINLINE void ECC_DisableILMECCExcp ( void  )

Disable ECC exception for ILM.

This function disables ECC exception for ILM by clearing the appropriate bit in the machine ILM control CSR.

Definition at line 472 of file core_feature_ecc.h.

473 {
474  __RV_CSR_CLEAR(CSR_MILM_CTL, MILM_CTL_ILM_ECC_EXCP_EN);
475 }

References __RV_CSR_CLEAR, CSR_MILM_CTL, and MILM_CTL_ILM_ECC_EXCP_EN.

◆ ECC_DLMErrInject()

__STATIC_FORCEINLINE void ECC_DLMErrInject ( uint32_t  ecc_code,
void *  addr 
)

Inject error into DLM.

This function injects an error into the DLM at the specified address with the given ECC code.

Parameters
[in]ecc_codeECC code to inject
[in]addrAddress where error should be injected

Definition at line 621 of file core_feature_ecc.h.

622 {
623  /* Write ecc_code into mecc_code csr also clear all error status */
624  __RV_CSR_WRITE(CSR_MECC_CODE, ecc_code);
625  ECC_DisableDLMECCCheck();
626  uint32_t val = __LW(addr);
627  __RWMB(); // make sure setting the ECC_INJ_EN bit before any other memory access
628  __RV_CSR_SET(CSR_MDLM_CTL, MDLM_CTL_DLM_ECC_INJ_EN);
629  __SW(addr, val);
630  __RWMB(); // make sure the error injection is finished
631  __RV_CSR_CLEAR(CSR_MDLM_CTL, MDLM_CTL_DLM_ECC_INJ_EN);
632  __RWMB(); // make sure clearing the ECC_INJ_EN bit before any other memory access
633  ECC_EnableDLMECCCheck();
634 }

References __LW(), __RV_CSR_CLEAR, __RV_CSR_SET, __RV_CSR_WRITE, __RWMB, __SW(), CSR_MDLM_CTL, CSR_MECC_CODE, ECC_DisableDLMECCCheck(), ECC_EnableDLMECCCheck(), and MDLM_CTL_DLM_ECC_INJ_EN.

◆ ECC_DLMErrRestore()

__STATIC_FORCEINLINE void ECC_DLMErrRestore ( void *  addr)

Restore DLM error at specified address.

This function restores the correct ECC code for the DLM at the specified address.

Parameters
[in]addrAddress to restore

Definition at line 642 of file core_feature_ecc.h.

643 {
644  ECC_DisableDLMECCCheck();
645  __RWMB();
646  __SW(addr, __LW(addr));
647  __RWMB();
648  ECC_EnableDLMECCCheck();
649 }

References __LW(), __RWMB, __SW(), ECC_DisableDLMECCCheck(), and ECC_EnableDLMECCCheck().

◆ ECC_EnableDCacheECC()

__STATIC_FORCEINLINE void ECC_EnableDCacheECC ( void  )

Enable ECC for D-Cache.

This function enables ECC for the data cache by setting the appropriate bit in the machine cache control CSR.

Definition at line 238 of file core_feature_ecc.h.

239 {
240  __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_DC_ECC_EN);
241 }

References __RV_CSR_SET, CSR_MCACHE_CTL, and MCACHE_CTL_DC_ECC_EN.

◆ ECC_EnableDCacheECCCheck()

__STATIC_FORCEINLINE void ECC_EnableDCacheECCCheck ( void  )

Enable ECC checking for D-Cache.

This function enables ECC checking for the data cache by setting the appropriate bit in the machine cache control CSR.

Definition at line 282 of file core_feature_ecc.h.

283 {
284  __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_DC_ECC_CHK_EN);
285 }

References __RV_CSR_SET, CSR_MCACHE_CTL, and MCACHE_CTL_DC_ECC_CHK_EN.

Referenced by ECC_DCacheDRamErrInject(), ECC_DCacheErrRestore(), and ECC_DCacheTRamErrInject().

◆ ECC_EnableDCacheECCExcp()

__STATIC_FORCEINLINE void ECC_EnableDCacheECCExcp ( void  )

Enable ECC exception for D-Cache.

This function enables ECC exception for the data cache by setting the appropriate bit in the machine cache control CSR.

Definition at line 260 of file core_feature_ecc.h.

261 {
262  __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_DC_ECC_EXCP_EN);
263 }

References __RV_CSR_SET, CSR_MCACHE_CTL, and MCACHE_CTL_DC_ECC_EXCP_EN.

◆ ECC_EnableDLM()

__STATIC_FORCEINLINE void ECC_EnableDLM ( void  )

Enable DLM.

This function enables DLM by setting the appropriate bit in the machine DLM control CSR.

Definition at line 539 of file core_feature_ecc.h.

540 {
541  __RV_CSR_SET(CSR_MDLM_CTL, MDLM_CTL_DLM_EN);
542 }

References __RV_CSR_SET, CSR_MDLM_CTL, and MDLM_CTL_DLM_EN.

◆ ECC_EnableDLMECC()

__STATIC_FORCEINLINE void ECC_EnableDLMECC ( void  )

Enable ECC for DLM.

This function enables ECC for DLM by setting the appropriate bit in the machine DLM control CSR.

Definition at line 559 of file core_feature_ecc.h.

560 {
561  __RV_CSR_SET(CSR_MDLM_CTL, MDLM_CTL_DLM_ECC_EN);
562 }

References __RV_CSR_SET, CSR_MDLM_CTL, and MDLM_CTL_DLM_ECC_EN.

◆ ECC_EnableDLMECCCheck()

__STATIC_FORCEINLINE void ECC_EnableDLMECCCheck ( void  )

Enable ECC checking for DLM.

This function enables ECC checking for DLM by setting the appropriate bit in the machine DLM control CSR.

Definition at line 599 of file core_feature_ecc.h.

600 {
601  __RV_CSR_SET(CSR_MDLM_CTL, MDLM_CTL_DLM_ECC_CHK_EN);
602 }

References __RV_CSR_SET, CSR_MDLM_CTL, and MDLM_CTL_DLM_ECC_CHK_EN.

Referenced by ECC_DLMErrInject(), and ECC_DLMErrRestore().

◆ ECC_EnableDLMECCExcp()

__STATIC_FORCEINLINE void ECC_EnableDLMECCExcp ( void  )

Enable ECC exception for DLM.

This function enables ECC exception for DLM by setting the appropriate bit in the machine DLM control CSR.

Definition at line 579 of file core_feature_ecc.h.

580 {
581  __RV_CSR_SET(CSR_MDLM_CTL, MDLM_CTL_DLM_ECC_EXCP_EN);
582 }

References __RV_CSR_SET, CSR_MDLM_CTL, and MDLM_CTL_DLM_ECC_EXCP_EN.

◆ ECC_EnableICacheECC()

__STATIC_FORCEINLINE void ECC_EnableICacheECC ( void  )

Enable ECC for I-Cache.

This function enables ECC for the instruction cache by setting the appropriate bit in the machine cache control CSR.

Definition at line 172 of file core_feature_ecc.h.

173 {
174  __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_IC_ECC_EN);
175 }

References __RV_CSR_SET, CSR_MCACHE_CTL, and MCACHE_CTL_IC_ECC_EN.

◆ ECC_EnableICacheECCCheck()

__STATIC_FORCEINLINE void ECC_EnableICacheECCCheck ( void  )

Enable ECC checking for I-Cache.

This function enables ECC checking for the instruction cache by setting the appropriate bit in the machine cache control CSR.

Definition at line 216 of file core_feature_ecc.h.

217 {
218  __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_IC_ECC_CHK_EN);
219 }

References __RV_CSR_SET, CSR_MCACHE_CTL, and MCACHE_CTL_IC_ECC_CHK_EN.

◆ ECC_EnableICacheECCExcp()

__STATIC_FORCEINLINE void ECC_EnableICacheECCExcp ( void  )

Enable ECC exception for I-Cache.

This function enables ECC exception for the instruction cache by setting the appropriate bit in the machine cache control CSR.

Definition at line 194 of file core_feature_ecc.h.

195 {
196  __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_IC_ECC_EXCP_EN);
197 }

References __RV_CSR_SET, CSR_MCACHE_CTL, and MCACHE_CTL_IC_ECC_EXCP_EN.

◆ ECC_EnableILM()

__STATIC_FORCEINLINE void ECC_EnableILM ( void  )

Enable ILM.

This function enables ILM by setting the appropriate bit in the machine ILM control CSR.

Definition at line 422 of file core_feature_ecc.h.

423 {
424  __RV_CSR_SET(CSR_MILM_CTL, MILM_CTL_ILM_EN);
425 }

References __RV_CSR_SET, CSR_MILM_CTL, and MILM_CTL_ILM_EN.

◆ ECC_EnableILMECC()

__STATIC_FORCEINLINE void ECC_EnableILMECC ( void  )

Enable ECC for ILM.

This function enables ECC for ILM by setting the appropriate bit in the machine ILM control CSR.

Definition at line 442 of file core_feature_ecc.h.

443 {
444  __RV_CSR_SET(CSR_MILM_CTL, MILM_CTL_ILM_ECC_EN);
445 }

References __RV_CSR_SET, CSR_MILM_CTL, and MILM_CTL_ILM_ECC_EN.

◆ ECC_EnableILMECCCheck()

__STATIC_FORCEINLINE void ECC_EnableILMECCCheck ( void  )

Enable ECC checking for ILM.

This function enables ECC checking for ILM by setting the appropriate bit in the machine ILM control CSR.

Definition at line 482 of file core_feature_ecc.h.

483 {
484  __RV_CSR_SET(CSR_MILM_CTL, MILM_CTL_ILM_ECC_CHK_EN);
485 }

References __RV_CSR_SET, CSR_MILM_CTL, and MILM_CTL_ILM_ECC_CHK_EN.

Referenced by ECC_ILMErrInject(), and ECC_ILMErrRestore().

◆ ECC_EnableILMECCExcp()

__STATIC_FORCEINLINE void ECC_EnableILMECCExcp ( void  )

Enable ECC exception for ILM.

This function enables ECC exception for ILM by setting the appropriate bit in the machine ILM control CSR.

Definition at line 462 of file core_feature_ecc.h.

463 {
464  __RV_CSR_SET(CSR_MILM_CTL, MILM_CTL_ILM_ECC_EXCP_EN);
465 }

References __RV_CSR_SET, CSR_MILM_CTL, and MILM_CTL_ILM_ECC_EXCP_EN.

◆ ECC_GenerateECCCodeU32()

static uint8_t ECC_GenerateECCCodeU32 ( uint32_t  a)
static

Generate ECC code for a 32-bit value.

This function calculates the ECC code for a 32-bit input value using Hamming code algorithm. It generates a 7-bit ECC code that can be used to detect and correct single-bit errors and detect double-bit errors.

Parameters
[in]a32-bit value for which ECC code is to be generated
Returns
8-bit ECC code (7 bits used, 1 bit unused)

Definition at line 954 of file core_feature_ecc.h.

955 {
956  uint8_t ecc_bits = 0;
957  uint8_t ecc_bit_0 = ((a >> 0) & 1) ^ ((a >> 1) & 1) ^ ((a >> 3) & 1) ^ ((a >> 4) & 1) ^
958  ((a >> 6) & 1) ^ ((a >> 8) & 1) ^ ((a >> 10) & 1) ^ ((a >> 12) & 1) ^
959  ((a >> 14) & 1) ^ ((a >> 17) & 1) ^ ((a >> 19) & 1) ^ ((a >> 20) & 1) ^
960  ((a >> 24) & 1) ^ ((a >> 28) & 1);
961  uint8_t ecc_bit_1 = ((a >> 0) & 1) ^ ((a >> 2) & 1) ^ ((a >> 3) & 1) ^ ((a >> 5) & 1) ^
962  ((a >> 6) & 1) ^ ((a >> 9) & 1) ^ ((a >> 11) & 1) ^ ((a >> 12) & 1) ^
963  ((a >> 15) & 1) ^ ((a >> 20) & 1) ^ ((a >> 22) & 1) ^ ((a >> 25) & 1) ^
964  ((a >> 29) & 1);
965  uint8_t ecc_bit_2 = ((a >> 1) & 1) ^ ((a >> 2) & 1) ^ ((a >> 3) & 1) ^ ((a >> 7) & 1) ^
966  ((a >> 8) & 1) ^ ((a >> 9) & 1) ^ ((a >> 13) & 1) ^ ((a >> 14) & 1) ^
967  ((a >> 15) & 1) ^ ((a >> 18) & 1) ^ ((a >> 21) & 1) ^ ((a >> 22) & 1) ^
968  ((a >> 26) & 1) ^ ((a >> 30) & 1);
969  uint8_t ecc_bit_3 = ((a >> 4) & 1) ^ ((a >> 5) & 1) ^ ((a >> 6) & 1) ^ ((a >> 7) & 1) ^
970  ((a >> 8) & 1) ^ ((a >> 9) & 1) ^ ((a >> 16) & 1) ^ ((a >> 17) & 1) ^
971  ((a >> 18) & 1) ^ ((a >> 23) & 1) ^ ((a >> 24) & 1) ^ ((a >> 25) & 1) ^
972  ((a >> 26) & 1) ^ ((a >> 31) & 1);
973  uint8_t ecc_bit_4 = ((a >> 10) & 1) ^ ((a >> 11) & 1) ^ ((a >> 12) & 1) ^ ((a >> 13) & 1) ^
974  ((a >> 14) & 1) ^ ((a >> 15) & 1) ^ ((a >> 16) & 1) ^ ((a >> 17) & 1) ^
975  ((a >> 18) & 1) ^ ((a >> 27) & 1) ^ ((a >> 28) & 1) ^ ((a >> 29) & 1) ^
976  ((a >> 30) & 1) ^ ((a >> 31) & 1);
977  uint8_t ecc_bit_5 = ((a >> 19) & 1) ^ ((a >> 20) & 1) ^ ((a >> 21) & 1) ^ ((a >> 22) & 1) ^
978  ((a >> 23) & 1) ^ ((a >> 24) & 1) ^ ((a >> 25) & 1) ^ ((a >> 26) & 1) ^
979  ((a >> 27) & 1) ^ ((a >> 28) & 1) ^ ((a >> 29) & 1) ^ ((a >> 30) & 1) ^
980  ((a >> 31) & 1);
981  uint8_t ecc_bit_6 = ((a >> 0) & 1) ^ ((a >> 1) & 1) ^ ((a >> 2) & 1) ^ ((a >> 4) & 1) ^
982  ((a >> 5) & 1) ^ ((a >> 7) & 1) ^ ((a >> 10) & 1) ^ ((a >> 11) & 1) ^
983  ((a >> 13) & 1) ^ ((a >> 16) & 1) ^ ((a >> 19) & 1) ^ ((a >> 21) & 1) ^
984  ((a >> 23) & 1) ^ ((a >> 27) & 1);
985  ecc_bits = (ecc_bit_6 << 6) | (ecc_bit_5 << 5) | (ecc_bit_4 << 4) | (ecc_bit_3 << 3) |
986  (ecc_bit_2 << 2) | (ecc_bit_1 << 1) | ecc_bit_0;
987  return ecc_bits;
988 }

◆ ECC_GenerateECCCodeU64()

static uint8_t ECC_GenerateECCCodeU64 ( uint64_t  a)
static

Generate ECC code for a 64-bit value.

This function calculates the ECC for a 64-bit input value using Hamming code algorithm. It generates an 8-bit ECC code that can be used to detect and correct single-bit errors and detect double-bit errors.

Parameters
[in]a64-bit value for which ECC code is to be generated
Returns
8-bit ECC code

Definition at line 999 of file core_feature_ecc.h.

1000 {
1001  uint8_t ecc_bits = 0;
1002  uint8_t ecc_bit_0 =
1003  (((a >> 0) & 1) ^ ((a >> 1) & 1) ^ ((a >> 3) & 1) ^ ((a >> 4) & 1) ^ ((a >> 6) & 1) ^
1004  ((a >> 8) & 1) ^ ((a >> 10) & 1) ^ ((a >> 12) & 1) ^ ((a >> 14) & 1) ^ ((a >> 17) & 1) ^
1005  ((a >> 20) & 1) ^ ((a >> 22) & 1) ^ ((a >> 24) & 1) ^ ((a >> 27) & 1) ^ ((a >> 30) & 1) ^
1006  ((a >> 32) & 1) ^ ((a >> 36) & 1) ^ ((a >> 37) & 1) ^ ((a >> 38) & 1) ^ ((a >> 40) & 1) ^
1007  ((a >> 42) & 1) ^ ((a >> 45) & 1) ^ ((a >> 47) & 1) ^ ((a >> 51) & 1) ^ ((a >> 54) & 1) ^
1008  ((a >> 57) & 1));
1009  uint8_t ecc_bit_1 =
1010  (((a >> 0) & 1) ^ ((a >> 2) & 1) ^ ((a >> 3) & 1) ^ ((a >> 5) & 1) ^ ((a >> 6) & 1) ^
1011  ((a >> 9) & 1) ^ ((a >> 11) & 1) ^ ((a >> 12) & 1) ^ ((a >> 15) & 1) ^ ((a >> 18) & 1) ^
1012  ((a >> 21) & 1) ^ ((a >> 22) & 1) ^ ((a >> 25) & 1) ^ ((a >> 28) & 1) ^ ((a >> 30) & 1) ^
1013  ((a >> 33) & 1) ^ ((a >> 37) & 1) ^ ((a >> 39) & 1) ^ ((a >> 40) & 1) ^ ((a >> 43) & 1) ^
1014  ((a >> 46) & 1) ^ ((a >> 47) & 1) ^ ((a >> 49) & 1) ^ ((a >> 52) & 1) ^ ((a >> 58) & 1) ^
1015  ((a >> 63) & 1));
1016  uint8_t ecc_bit_2 =
1017  (((a >> 1) & 1) ^ ((a >> 2) & 1) ^ ((a >> 3) & 1) ^ ((a >> 7) & 1) ^ ((a >> 8) & 1) ^
1018  ((a >> 9) & 1) ^ ((a >> 13) & 1) ^ ((a >> 14) & 1) ^ ((a >> 15) & 1) ^ ((a >> 19) & 1) ^
1019  ((a >> 23) & 1) ^ ((a >> 24) & 1) ^ ((a >> 25) & 1) ^ ((a >> 29) & 1) ^ ((a >> 30) & 1) ^
1020  ((a >> 34) & 1) ^ ((a >> 41) & 1) ^ ((a >> 42) & 1) ^ ((a >> 43) & 1) ^ ((a >> 48) & 1) ^
1021  ((a >> 49) & 1) ^ ((a >> 53) & 1) ^ ((a >> 54) & 1) ^ ((a >> 59) & 1) ^ ((a >> 62) & 1) ^
1022  ((a >> 63) & 1));
1023  uint8_t ecc_bit_3 =
1024  (((a >> 4) & 1) ^ ((a >> 5) & 1) ^ ((a >> 6) & 1) ^ ((a >> 7) & 1) ^ ((a >> 8) & 1) ^
1025  ((a >> 9) & 1) ^ ((a >> 16) & 1) ^ ((a >> 17) & 1) ^ ((a >> 18) & 1) ^ ((a >> 19) & 1) ^
1026  ((a >> 26) & 1) ^ ((a >> 27) & 1) ^ ((a >> 28) & 1) ^ ((a >> 29) & 1) ^ ((a >> 30) & 1) ^
1027  ((a >> 35) & 1) ^ ((a >> 36) & 1) ^ ((a >> 37) & 1) ^ ((a >> 44) & 1) ^ ((a >> 45) & 1) ^
1028  ((a >> 46) & 1) ^ ((a >> 47) & 1) ^ ((a >> 48) & 1) ^ ((a >> 49) & 1) ^ ((a >> 55) & 1) ^
1029  ((a >> 60) & 1));
1030  uint8_t ecc_bit_4 =
1031  (((a >> 10) & 1) ^ ((a >> 11) & 1) ^ ((a >> 12) & 1) ^ ((a >> 13) & 1) ^ ((a >> 14) & 1) ^
1032  ((a >> 15) & 1) ^ ((a >> 16) & 1) ^ ((a >> 17) & 1) ^ ((a >> 18) & 1) ^ ((a >> 19) & 1) ^
1033  ((a >> 31) & 1) ^ ((a >> 32) & 1) ^ ((a >> 33) & 1) ^ ((a >> 34) & 1) ^ ((a >> 35) & 1) ^
1034  ((a >> 36) & 1) ^ ((a >> 37) & 1) ^ ((a >> 50) & 1) ^ ((a >> 51) & 1) ^ ((a >> 52) & 1) ^
1035  ((a >> 53) & 1) ^ ((a >> 54) & 1) ^ ((a >> 55) & 1) ^ ((a >> 61) & 1) ^ ((a >> 62) & 1) ^
1036  ((a >> 63) & 1));
1037  uint8_t ecc_bit_5 =
1038  (((a >> 20) & 1) ^ ((a >> 21) & 1) ^ ((a >> 22) & 1) ^ ((a >> 23) & 1) ^ ((a >> 24) & 1) ^
1039  ((a >> 25) & 1) ^ ((a >> 26) & 1) ^ ((a >> 27) & 1) ^ ((a >> 28) & 1) ^ ((a >> 29) & 1) ^
1040  ((a >> 30) & 1) ^ ((a >> 31) & 1) ^ ((a >> 32) & 1) ^ ((a >> 33) & 1) ^ ((a >> 34) & 1) ^
1041  ((a >> 35) & 1) ^ ((a >> 36) & 1) ^ ((a >> 37) & 1) ^ ((a >> 56) & 1) ^ ((a >> 57) & 1) ^
1042  ((a >> 58) & 1) ^ ((a >> 59) & 1) ^ ((a >> 60) & 1) ^ ((a >> 61) & 1) ^ ((a >> 62) & 1) ^
1043  ((a >> 63) & 1));
1044  uint8_t ecc_bit_6 =
1045  (((a >> 38) & 1) ^ ((a >> 39) & 1) ^ ((a >> 40) & 1) ^ ((a >> 41) & 1) ^ ((a >> 42) & 1) ^
1046  ((a >> 43) & 1) ^ ((a >> 44) & 1) ^ ((a >> 45) & 1) ^ ((a >> 46) & 1) ^ ((a >> 47) & 1) ^
1047  ((a >> 48) & 1) ^ ((a >> 49) & 1) ^ ((a >> 50) & 1) ^ ((a >> 51) & 1) ^ ((a >> 52) & 1) ^
1048  ((a >> 53) & 1) ^ ((a >> 54) & 1) ^ ((a >> 55) & 1) ^ ((a >> 56) & 1) ^ ((a >> 57) & 1) ^
1049  ((a >> 58) & 1) ^ ((a >> 59) & 1) ^ ((a >> 60) & 1) ^ ((a >> 61) & 1) ^ ((a >> 62) & 1) ^
1050  ((a >> 63) & 1));
1051  uint8_t ecc_bit_7 =
1052  (((a >> 0) & 1) ^ ((a >> 1) & 1) ^ ((a >> 2) & 1) ^ ((a >> 4) & 1) ^ ((a >> 5) & 1) ^
1053  ((a >> 7) & 1) ^ ((a >> 10) & 1) ^ ((a >> 11) & 1) ^ ((a >> 13) & 1) ^ ((a >> 16) & 1) ^
1054  ((a >> 20) & 1) ^ ((a >> 21) & 1) ^ ((a >> 23) & 1) ^ ((a >> 26) & 1) ^ ((a >> 31) & 1) ^
1055  ((a >> 36) & 1) ^ ((a >> 38) & 1) ^ ((a >> 39) & 1) ^ ((a >> 41) & 1) ^ ((a >> 44) & 1) ^
1056  ((a >> 47) & 1) ^ ((a >> 49) & 1) ^ ((a >> 50) & 1) ^ ((a >> 54) & 1) ^ ((a >> 56) & 1) ^
1057  ((a >> 62) & 1));
1058  ecc_bits = (ecc_bit_7 << 7) | (ecc_bit_6 << 6) | (ecc_bit_5 << 5) | (ecc_bit_4 << 4) |
1059  (ecc_bit_3 << 3) | (ecc_bit_2 << 2) | (ecc_bit_1 << 1) | ecc_bit_0;
1060  return ecc_bits;
1061 }

◆ ECC_ICacheDRamErrInject()

__STATIC_FORCEINLINE void ECC_ICacheDRamErrInject ( uint32_t  ecc_code,
void *  addr 
)

Inject error into I-Cache Data RAM.

This function injects an error into the I-Cache Data RAM at the specified address with the given ECC code.

Parameters
[in]ecc_codeECC code to inject
[in]addrAddress where error should be injected

Definition at line 328 of file core_feature_ecc.h.

329 {
330  /* Write ecc_code into mecc_code csr also clear all error status */
331  __RV_CSR_WRITE(CSR_MECC_CODE, ecc_code);
332  MInvalICacheLine((unsigned long)addr);
333  __RWMB();
334  __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_IC_DRAM_ECC_INJ_EN);
335  MLockICacheLine((unsigned long)addr);
336  __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_IC_DRAM_ECC_INJ_EN);
337  __RWMB();
338 }

References __RV_CSR_CLEAR, __RV_CSR_SET, __RV_CSR_WRITE, __RWMB, CSR_MCACHE_CTL, CSR_MECC_CODE, MCACHE_CTL_IC_DRAM_ECC_INJ_EN, MInvalICacheLine(), and MLockICacheLine().

◆ ECC_ICacheErrRestore()

__STATIC_FORCEINLINE void ECC_ICacheErrRestore ( void *  addr)

Restore I-Cache error at specified address.

This function restores the correct ECC code for the I-Cache line at the specified address.

Parameters
[in]addrAddress to restore

Definition at line 346 of file core_feature_ecc.h.

347 {
348  /* Re-lock cache to restore the correct ecc code */
349  MInvalICacheLine((unsigned long)addr);
350  MLockICacheLine((unsigned long)addr);
351 }

References MInvalICacheLine(), and MLockICacheLine().

◆ ECC_ICacheTRamErrInject()

__STATIC_FORCEINLINE void ECC_ICacheTRamErrInject ( uint32_t  ecc_code,
void *  addr 
)

Inject error into I-Cache Tag RAM.

This function injects an error into the I-Cache Tag RAM at the specified address with the given ECC code.

Parameters
[in]ecc_codeECC code to inject
[in]addrAddress where error should be injected

Definition at line 308 of file core_feature_ecc.h.

309 {
310  /* Write ecc_code into mecc_code csr also clear all error status */
311  __RV_CSR_WRITE(CSR_MECC_CODE, ecc_code);
312  MInvalICacheLine((unsigned long)addr);
313  __RWMB();
314  __RV_CSR_SET(CSR_MCACHE_CTL, MCACHE_CTL_IC_TRAM_ECC_INJ_EN);
315  MLockICacheLine((unsigned long)addr);
316  __RV_CSR_CLEAR(CSR_MCACHE_CTL, MCACHE_CTL_IC_TRAM_ECC_INJ_EN);
317  __RWMB();
318 }

References __RV_CSR_CLEAR, __RV_CSR_SET, __RV_CSR_WRITE, __RWMB, CSR_MCACHE_CTL, CSR_MECC_CODE, MCACHE_CTL_IC_TRAM_ECC_INJ_EN, MInvalICacheLine(), and MLockICacheLine().

◆ ECC_ILMErrInject()

__STATIC_FORCEINLINE void ECC_ILMErrInject ( uint32_t  ecc_code,
void *  addr 
)

Inject error into ILM.

This function injects an error into the ILM at the specified address with the given ECC code.

Parameters
[in]ecc_codeECC code to inject
[in]addrAddress where error should be injected

Definition at line 504 of file core_feature_ecc.h.

505 {
506  /* Write ecc_code into mecc_code csr also clear all error status */
507  __RV_CSR_WRITE(CSR_MECC_CODE, ecc_code);
508  ECC_DisableILMECCCheck();
509  uint32_t val = __LW(addr);
510  __RWMB(); // make sure setting the ECC_INJ_EN bit before any other memory access
511  __RV_CSR_SET(CSR_MILM_CTL, MILM_CTL_ILM_ECC_INJ_EN);
512  __SW(addr, val);
513  __RWMB(); // make sure the error injection is finished
514  __RV_CSR_CLEAR(CSR_MILM_CTL, MILM_CTL_ILM_ECC_INJ_EN);
515  __RWMB(); // make sure clearing the ECC_INJ_EN bit before any other memory access
516  ECC_EnableILMECCCheck();
517 }

References __LW(), __RV_CSR_CLEAR, __RV_CSR_SET, __RV_CSR_WRITE, __RWMB, __SW(), CSR_MECC_CODE, CSR_MILM_CTL, ECC_DisableILMECCCheck(), ECC_EnableILMECCCheck(), and MILM_CTL_ILM_ECC_INJ_EN.

◆ ECC_ILMErrRestore()

__STATIC_FORCEINLINE void ECC_ILMErrRestore ( void *  addr)

Restore ILM error at specified address.

This function restores the correct ECC code for the ILM at the specified address.

Parameters
[in]addrAddress to restore

Definition at line 525 of file core_feature_ecc.h.

526 {
527  ECC_DisableILMECCCheck();
528  __RWMB();
529  __SW(addr, __LW(addr));
530  __RWMB();
531  ECC_EnableILMECCCheck();
532 }

References __LW(), __RWMB, __SW(), ECC_DisableILMECCCheck(), and ECC_EnableILMECCCheck().

◆ ECC_IsAnyDoubleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsAnyDoubleBitErrorOccured ( void  )

Check if any double-bit error has occurred.

This function checks if any double-bit error has occurred by reading the machine ECC code CSR.

Returns
1 if any double-bit error has occurred, 0 otherwise

Definition at line 807 of file core_feature_ecc.h.

808 {
809  CSR_MECC_CODE_Type mecc_code;
810  mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
811  return mecc_code.b.ramid;
812 }

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, and CSR_MECCCODE_Type::ramid.

◆ ECC_IsAnySingleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsAnySingleBitErrorOccured ( void  )

Check if any single-bit error has occurred.

This function checks if any single-bit error has occurred by reading the machine ECC code CSR.

Returns
1 if any single-bit error has occurred, 0 otherwise

Definition at line 663 of file core_feature_ecc.h.

664 {
665  CSR_MECC_CODE_Type mecc_code;
666  mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
667  return mecc_code.b.sramid;
668 }

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, and CSR_MECCCODE_Type::sramid.

◆ ECC_IsDCacheDoubleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsDCacheDoubleBitErrorOccured ( void  )

Check if D-Cache double-bit error has occurred.

This function checks if a double-bit error has occurred in the D-Cache.

Returns
1 if D-Cache double-bit error has occurred, 0 otherwise

Definition at line 833 of file core_feature_ecc.h.

834 {
835  CSR_MECC_CODE_Type mecc_code;
836  mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
837  return mecc_code.b.ramid & ECC_ERROR_RAMID_MASK_DCACHE;
838 }

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, ECC_ERROR_RAMID_MASK_DCACHE, and CSR_MECCCODE_Type::ramid.

◆ ECC_IsDCacheSingleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsDCacheSingleBitErrorOccured ( void  )

Check if D-Cache single-bit error has occurred.

This function checks if a single-bit error has occurred in the D-Cache.

Returns
1 if D-Cache single-bit error has occurred, 0 otherwise

Definition at line 689 of file core_feature_ecc.h.

690 {
691  CSR_MECC_CODE_Type mecc_code;
692  mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
693  return mecc_code.b.sramid & ECC_ERROR_RAMID_MASK_DCACHE;
694 }

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, ECC_ERROR_RAMID_MASK_DCACHE, and CSR_MECCCODE_Type::sramid.

◆ ECC_IsDCacheSupportECC()

__STATIC_FORCEINLINE int32_t ECC_IsDCacheSupportECC ( void  )

Check if D-Cache supports ECC.

This function checks if both D-Cache and ECC are supported in the core.

Returns
1 if D-Cache supports ECC, 0 otherwise

Definition at line 101 of file core_feature_ecc.h.

102 {
103  CSR_MCFGINFO_Type mcfginfo;
104  CSR_MDCFGINFO_Type mdcfginfo;
105  mcfginfo.d = __RV_CSR_READ(CSR_MCFG_INFO);
106  mdcfginfo.d = __RV_CSR_READ(CSR_MDCFG_INFO);
107  return mcfginfo.b.dcache && mdcfginfo.b.ecc;
108 }

References __RV_CSR_READ, CSR_MCFGINFO_Type::b, CSR_MDCFGINFO_Type::b, CSR_MCFG_INFO, CSR_MDCFG_INFO, CSR_MCFGINFO_Type::d, CSR_MDCFGINFO_Type::d, CSR_MCFGINFO_Type::dcache, and CSR_MDCFGINFO_Type::ecc.

◆ ECC_IsDLMDoubleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsDLMDoubleBitErrorOccured ( void  )

Check if DLM double-bit error has occurred.

This function checks if a double-bit error has occurred in the DLM.

Returns
1 if DLM double-bit error has occurred, 0 otherwise

Definition at line 872 of file core_feature_ecc.h.

873 {
874  CSR_MECC_CODE_Type mecc_code;
875  mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
876  return mecc_code.b.ramid & ECC_ERROR_RAMID_MASK_DLM;
877 }

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, ECC_ERROR_RAMID_MASK_DLM, and CSR_MECCCODE_Type::ramid.

◆ ECC_IsDLMSingleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsDLMSingleBitErrorOccured ( void  )

Check if DLM single-bit error has occurred.

This function checks if a single-bit error has occurred in the DLM.

Returns
1 if DLM single-bit error has occurred, 0 otherwise

Definition at line 728 of file core_feature_ecc.h.

729 {
730  CSR_MECC_CODE_Type mecc_code;
731  mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
732  return mecc_code.b.sramid & ECC_ERROR_RAMID_MASK_DLM;
733 }

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, ECC_ERROR_RAMID_MASK_DLM, and CSR_MECCCODE_Type::sramid.

◆ ECC_IsDLMSupportECC()

__STATIC_FORCEINLINE int32_t ECC_IsDLMSupportECC ( void  )

Check if DLM supports ECC.

This function checks if both DLM and ECC are supported in the core.

Returns
1 if DLM supports ECC, 0 otherwise

Definition at line 144 of file core_feature_ecc.h.

145 {
146  CSR_MCFGINFO_Type mcfginfo;
147  CSR_MDCFGINFO_Type mdcfginfo;
148  mcfginfo.d = __RV_CSR_READ(CSR_MCFG_INFO);
149  mdcfginfo.d = __RV_CSR_READ(CSR_MDCFG_INFO);
150  return mcfginfo.b.dlm && mdcfginfo.b.lm_ecc;
151 }

References __RV_CSR_READ, CSR_MCFGINFO_Type::b, CSR_MDCFGINFO_Type::b, CSR_MCFG_INFO, CSR_MDCFG_INFO, CSR_MCFGINFO_Type::d, CSR_MDCFGINFO_Type::d, CSR_MCFGINFO_Type::dlm, and CSR_MDCFGINFO_Type::lm_ecc.

◆ ECC_IsGlobalSupportECC()

__STATIC_FORCEINLINE int32_t ECC_IsGlobalSupportECC ( void  )

Check if the core globally supports ECC.

This function reads the machine configuration info CSR and checks if ECC is supported globally in the core.

Returns
1 if ECC is globally supported, 0 otherwise

Definition at line 73 of file core_feature_ecc.h.

74 {
75  CSR_MCFGINFO_Type mcfginfo;
76  mcfginfo.d = __RV_CSR_READ(CSR_MCFG_INFO);
77  return mcfginfo.b.ecc;
78 }

References __RV_CSR_READ, CSR_MCFGINFO_Type::b, CSR_MCFG_INFO, CSR_MCFGINFO_Type::d, and CSR_MCFGINFO_Type::ecc.

◆ ECC_IsICacheDoubleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsICacheDoubleBitErrorOccured ( void  )

Check if I-Cache double-bit error has occurred.

This function checks if a double-bit error has occurred in the I-Cache.

Returns
1 if I-Cache double-bit error has occurred, 0 otherwise

Definition at line 820 of file core_feature_ecc.h.

821 {
822  CSR_MECC_CODE_Type mecc_code;
823  mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
824  return mecc_code.b.ramid & ECC_ERROR_RAMID_MASK_ICACHE;
825 }

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, ECC_ERROR_RAMID_MASK_ICACHE, and CSR_MECCCODE_Type::ramid.

◆ ECC_IsICacheSingleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsICacheSingleBitErrorOccured ( void  )

Check if I-Cache single-bit error has occurred.

This function checks if a single-bit error has occurred in the I-Cache.

Returns
1 if I-Cache single-bit error has occurred, 0 otherwise

Definition at line 676 of file core_feature_ecc.h.

677 {
678  CSR_MECC_CODE_Type mecc_code;
679  mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
680  return mecc_code.b.sramid & ECC_ERROR_RAMID_MASK_ICACHE;
681 }

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, ECC_ERROR_RAMID_MASK_ICACHE, and CSR_MECCCODE_Type::sramid.

◆ ECC_IsICacheSupportECC()

__STATIC_FORCEINLINE int32_t ECC_IsICacheSupportECC ( void  )

Check if I-Cache supports ECC.

This function checks if both I-Cache and ECC are supported in the core.

Returns
1 if I-Cache supports ECC, 0 otherwise

Definition at line 86 of file core_feature_ecc.h.

87 {
88  CSR_MCFGINFO_Type mcfginfo;
89  CSR_MICFGINFO_Type micfginfo;
90  mcfginfo.d = __RV_CSR_READ(CSR_MCFG_INFO);
91  micfginfo.d = __RV_CSR_READ(CSR_MICFG_INFO);
92  return mcfginfo.b.icache && micfginfo.b.ecc;
93 }

References __RV_CSR_READ, CSR_MCFGINFO_Type::b, CSR_MICFGINFO_Type::b, CSR_MCFG_INFO, CSR_MICFG_INFO, CSR_MCFGINFO_Type::d, CSR_MICFGINFO_Type::d, CSR_MICFGINFO_Type::ecc, and CSR_MCFGINFO_Type::icache.

◆ ECC_IsILMDoubleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsILMDoubleBitErrorOccured ( void  )

Check if ILM double-bit error has occurred.

This function checks if a double-bit error has occurred in the ILM.

Returns
1 if ILM double-bit error has occurred, 0 otherwise

Definition at line 859 of file core_feature_ecc.h.

860 {
861  CSR_MECC_CODE_Type mecc_code;
862  mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
863  return mecc_code.b.ramid & ECC_ERROR_RAMID_MASK_ILM;
864 }

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, ECC_ERROR_RAMID_MASK_ILM, and CSR_MECCCODE_Type::ramid.

◆ ECC_IsILMSingleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsILMSingleBitErrorOccured ( void  )

Check if ILM single-bit error has occurred.

This function checks if a single-bit error has occurred in the ILM.

Returns
1 if ILM single-bit error has occurred, 0 otherwise

Definition at line 715 of file core_feature_ecc.h.

716 {
717  CSR_MECC_CODE_Type mecc_code;
718  mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
719  return mecc_code.b.sramid & ECC_ERROR_RAMID_MASK_ILM;
720 }

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, ECC_ERROR_RAMID_MASK_ILM, and CSR_MECCCODE_Type::sramid.

◆ ECC_IsILMSupportECC()

__STATIC_FORCEINLINE int32_t ECC_IsILMSupportECC ( void  )

Check if ILM supports ECC.

This function checks if both ILM and ECC are supported in the core.

Returns
1 if ILM supports ECC, 0 otherwise

Definition at line 129 of file core_feature_ecc.h.

130 {
131  CSR_MCFGINFO_Type mcfginfo;
132  CSR_MICFGINFO_Type micfginfo;
133  mcfginfo.d = __RV_CSR_READ(CSR_MCFG_INFO);
134  micfginfo.d = __RV_CSR_READ(CSR_MICFG_INFO);
135  return mcfginfo.b.ilm && micfginfo.b.lm_ecc;
136 }

References __RV_CSR_READ, CSR_MCFGINFO_Type::b, CSR_MICFGINFO_Type::b, CSR_MCFG_INFO, CSR_MICFG_INFO, CSR_MCFGINFO_Type::d, CSR_MICFGINFO_Type::d, CSR_MCFGINFO_Type::ilm, and CSR_MICFGINFO_Type::lm_ecc.

◆ ECC_IsTLBDoubleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsTLBDoubleBitErrorOccured ( void  )

Check if TLB double-bit error has occurred.

This function checks if a double-bit error has occurred in the TLB.

Returns
1 if TLB double-bit error has occurred, 0 otherwise

Definition at line 846 of file core_feature_ecc.h.

847 {
848  CSR_MECC_CODE_Type mecc_code;
849  mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
850  return mecc_code.b.ramid & ECC_ERROR_RAMID_MASK_TLB;
851 }

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, ECC_ERROR_RAMID_MASK_TLB, and CSR_MECCCODE_Type::ramid.

◆ ECC_IsTLBSingleBitErrorOccured()

__STATIC_FORCEINLINE int32_t ECC_IsTLBSingleBitErrorOccured ( void  )

Check if TLB single-bit error has occurred.

This function checks if a single-bit error has occurred in the TLB.

Returns
1 if TLB single-bit error has occurred, 0 otherwise

Definition at line 702 of file core_feature_ecc.h.

703 {
704  CSR_MECC_CODE_Type mecc_code;
705  mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
706  return mecc_code.b.sramid & ECC_ERROR_RAMID_MASK_TLB;
707 }

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, ECC_ERROR_RAMID_MASK_TLB, and CSR_MECCCODE_Type::sramid.

◆ ECC_IsTLBSupportECC()

__STATIC_FORCEINLINE int32_t ECC_IsTLBSupportECC ( void  )

Check if TLB supports ECC.

This function checks if TLB ECC is supported in the core.

Returns
1 if TLB supports ECC, 0 otherwise

Definition at line 116 of file core_feature_ecc.h.

117 {
118  CSR_MTLBCFGINFO_Type mtlbcfginfo;
119  mtlbcfginfo.d = __RV_CSR_READ(CSR_MTLBCFG_INFO);
120  return mtlbcfginfo.b.ecc;
121 }

References __RV_CSR_READ, CSR_MTLBCFGINFO_Type::b, CSR_MTLBCFG_INFO, CSR_MTLBCFGINFO_Type::d, and CSR_MTLBCFGINFO_Type::ecc.

◆ ECC_IsXorErrorInjectMode()

__STATIC_FORCEINLINE int32_t ECC_IsXorErrorInjectMode ( void  )

Check if XOR error injection mode is supported.

This function reads the machine ECC code CSR and checks if error injection mode is supported.

Returns
1 if XOR error injection mode is enabled, 0 otherwise

Definition at line 159 of file core_feature_ecc.h.

160 {
161  CSR_MECC_CODE_Type mecc_code;
162  mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
163  return mecc_code.b.ecc_inj_mode;
164 }

References __RV_CSR_READ, CSR_MECCCODE_Type::b, CSR_MECC_CODE, CSR_MECCCODE_Type::d, and CSR_MECCCODE_Type::ecc_inj_mode.

CSR_MDCFGINFO_Type::d
rv_csr_t d
Type used for csr data access.
Definition: core_feature_base.h:465
ECC_ERROR_RAMID_MASK_DCACHE
#define ECC_ERROR_RAMID_MASK_DCACHE
Definition: core_feature_ecc.h:652
CSR_MICFGINFO_Type::ecc
rv_csr_t ecc
bit: 10 I-Cache ECC support
Definition: core_feature_base.h:438
MDLM_CTL_DLM_ECC_EN
#define MDLM_CTL_DLM_ECC_EN
Definition: riscv_encoding.h:256
MECC_CODE_SRAMID_DLM
#define MECC_CODE_SRAMID_DLM
Definition: riscv_encoding.h:378
CSR_MECCCODE_Type::sramid
rv_csr_t sramid
bit: 24..28 The ID of RAM that has 1bit ECC error, software can clear these bits
Definition: core_feature_base.h:559
MCACHE_CTL_IC_DRAM_ECC_INJ_EN
#define MCACHE_CTL_IC_DRAM_ECC_INJ_EN
Definition: riscv_encoding.h:296
MCACHE_CTL_DC_ECC_EXCP_EN
#define MCACHE_CTL_DC_ECC_EXCP_EN
Definition: riscv_encoding.h:303
MILM_CTL_ILM_ECC_CHK_EN
#define MILM_CTL_ILM_ECC_CHK_EN
Definition: riscv_encoding.h:244
CSR_MCFGINFO_Type::b
struct CSR_MCFGINFO_Type::@14 b
Structure used for bit access.
CSR_MCFGINFO_Type::dcache
rv_csr_t dcache
bit: 10 DCache present
Definition: core_feature_base.h:408
__RV_CSR_CLEAR
#define __RV_CSR_CLEAR(csr, val)
CSR operation Macro for csrc instruction.
Definition: core_feature_base.h:799
MInvalICacheLine
__STATIC_INLINE void MInvalICacheLine(unsigned long addr)
Invalidate one I-Cache line specified by address in M-Mode.
Definition: core_feature_cache.h:651
ECC_EnableDLMECCCheck
__STATIC_FORCEINLINE void ECC_EnableDLMECCCheck(void)
Enable ECC checking for DLM.
Definition: core_feature_ecc.h:599
CSR_MECCCODE_Type
Union type to access MECC_CODE CSR register.
Definition: core_feature_base.h:553
CSR_MICFGINFO_Type
Union type to access MICFG_INFO CSR register.
Definition: core_feature_base.h:433
MFlushInvalDCacheLine
__STATIC_INLINE void MFlushInvalDCacheLine(unsigned long addr)
Flush and invalidate one D-Cache line specified by address in M-Mode.
Definition: core_feature_cache.h:1699
CSR_MDCFGINFO_Type::ecc
rv_csr_t ecc
bit: 10 D-Cache ECC support
Definition: core_feature_base.h:459
CSR_MCFGINFO_Type
Union type to access MCFG_INFO CSR register.
Definition: core_feature_base.h:396
MECC_CODE_RAMID_DC
#define MECC_CODE_RAMID_DC
Definition: riscv_encoding.h:370
CSR_MTLBCFGINFO_Type::d
rv_csr_t d
Type used for csr data access.
Definition: core_feature_base.h:501
MILM_CTL_ILM_ECC_EXCP_EN
#define MILM_CTL_ILM_ECC_EXCP_EN
Definition: riscv_encoding.h:247
MECC_CODE_RAMID_IC
#define MECC_CODE_RAMID_IC
Definition: riscv_encoding.h:369
MECC_CODE_SRAMID_TLB
#define MECC_CODE_SRAMID_TLB
Definition: riscv_encoding.h:376
CSR_MDCFGINFO_Type
Union type to access MDCFG_INFO CSR register.
Definition: core_feature_base.h:454
MECC_CODE_SRAMID_ILM
#define MECC_CODE_SRAMID_ILM
Definition: riscv_encoding.h:377
CSR_MICFGINFO_Type::d
rv_csr_t d
Type used for csr data access.
Definition: core_feature_base.h:446
CSR_MCFG_INFO
#define CSR_MCFG_INFO
Definition: riscv_encoding.h:1111
MDLM_CTL_DLM_ECC_INJ_EN
#define MDLM_CTL_DLM_ECC_INJ_EN
Definition: riscv_encoding.h:254
CSR_MECCCODE_Type::ecc_inj_mode
rv_csr_t ecc_inj_mode
bit: 31 ECC injection mode
Definition: core_feature_base.h:561
__RV_CSR_WRITE
#define __RV_CSR_WRITE(csr, val)
CSR operation Macro for csrw instruction.
Definition: core_feature_base.h:725
MLockDCacheLine
__STATIC_INLINE unsigned long MLockDCacheLine(unsigned long addr)
Lock one D-Cache line specified by address in M-Mode.
Definition: core_feature_cache.h:2012
CSR_MCFGINFO_Type::d
rv_csr_t d
Type used for csr data access.
Definition: core_feature_base.h:425
MILM_CTL_ILM_ECC_INJ_EN
#define MILM_CTL_ILM_ECC_INJ_EN
Definition: riscv_encoding.h:246
__LW
__STATIC_FORCEINLINE uint32_t __LW(volatile void *addr)
Load 32bit value from address (32 bit)
Definition: core_feature_base.h:2236
ECC_DisableILMECCCheck
__STATIC_FORCEINLINE void ECC_DisableILMECCCheck(void)
Disable ECC checking for ILM.
Definition: core_feature_ecc.h:492
MDLM_CTL_DLM_ECC_EXCP_EN
#define MDLM_CTL_DLM_ECC_EXCP_EN
Definition: riscv_encoding.h:255
CSR_MDCFGINFO_Type::lm_ecc
rv_csr_t lm_ecc
bit: 21 DLM ECC present
Definition: core_feature_base.h:462
MCACHE_CTL_IC_ECC_EXCP_EN
#define MCACHE_CTL_IC_ECC_EXCP_EN
Definition: riscv_encoding.h:292
CSR_MTLBCFGINFO_Type::b
struct CSR_MTLBCFGINFO_Type::@17 b
Structure used for bit access.
CSR_MCFGINFO_Type::icache
rv_csr_t icache
bit: 9 ICache present
Definition: core_feature_base.h:407
ECC_ERROR_RAMID_MASK_TLB
#define ECC_ERROR_RAMID_MASK_TLB
Definition: core_feature_ecc.h:653
CSR_MCFGINFO_Type::ilm
rv_csr_t ilm
bit: 7 ILM present
Definition: core_feature_base.h:405
CSR_MDLM_CTL
#define CSR_MDLM_CTL
Definition: riscv_encoding.h:1015
ECC_ERROR_RAMID_MASK_ICACHE
#define ECC_ERROR_RAMID_MASK_ICACHE
Definition: core_feature_ecc.h:651
MDLM_CTL_DLM_ECC_CHK_EN
#define MDLM_CTL_DLM_ECC_CHK_EN
Definition: riscv_encoding.h:252
CSR_MICFGINFO_Type::lm_ecc
rv_csr_t lm_ecc
bit: 22 ILM ECC support
Definition: core_feature_base.h:442
CSR_MTLBCFGINFO_Type
Union type to access MTLBCFG_INFO CSR register.
Definition: core_feature_base.h:477
CSR_MECCCODE_Type::d
rv_csr_t d
Type used for csr data access.
Definition: core_feature_base.h:566
MILM_CTL_ILM_EN
#define MILM_CTL_ILM_EN
Definition: riscv_encoding.h:249
ECC_EnableDCacheECCCheck
__STATIC_FORCEINLINE void ECC_EnableDCacheECCCheck(void)
Enable ECC checking for D-Cache.
Definition: core_feature_ecc.h:282
CSR_MCACHE_CTL
#define CSR_MCACHE_CTL
Definition: riscv_encoding.h:1020
MLockICacheLine
__STATIC_INLINE unsigned long MLockICacheLine(unsigned long addr)
Lock one I-Cache line specified by address in M-Mode.
Definition: core_feature_cache.h:917
MCACHE_CTL_DC_ECC_EN
#define MCACHE_CTL_DC_ECC_EN
Definition: riscv_encoding.h:302
CSR_MICFGINFO_Type::b
struct CSR_MICFGINFO_Type::@15 b
Structure used for bit access.
CSR_MICFG_INFO
#define CSR_MICFG_INFO
Definition: riscv_encoding.h:1109
__RV_CSR_READ
#define __RV_CSR_READ(csr)
CSR operation Macro for csrr instruction.
Definition: core_feature_base.h:707
CSR_MTLBCFG_INFO
#define CSR_MTLBCFG_INFO
Definition: riscv_encoding.h:1112
MECC_CODE_RAMID_DLM
#define MECC_CODE_RAMID_DLM
Definition: riscv_encoding.h:373
MCACHE_CTL_IC_TRAM_ECC_INJ_EN
#define MCACHE_CTL_IC_TRAM_ECC_INJ_EN
Definition: riscv_encoding.h:293
ECC_DisableDCacheECCCheck
__STATIC_FORCEINLINE void ECC_DisableDCacheECCCheck(void)
Disable ECC checking for D-Cache.
Definition: core_feature_ecc.h:293
ECC_ERROR_RAMID_MASK_DLM
#define ECC_ERROR_RAMID_MASK_DLM
Definition: core_feature_ecc.h:655
CSR_MTLBCFGINFO_Type::ecc
rv_csr_t ecc
bit: 10 Main TLB supports ECC or not
Definition: core_feature_base.h:482
ECC_EnableILMECCCheck
__STATIC_FORCEINLINE void ECC_EnableILMECCCheck(void)
Enable ECC checking for ILM.
Definition: core_feature_ecc.h:482
__RV_CSR_SET
#define __RV_CSR_SET(csr, val)
CSR operation Macro for csrs instruction.
Definition: core_feature_base.h:762
MECC_CODE_SRAMID_DC
#define MECC_CODE_SRAMID_DC
Definition: riscv_encoding.h:375
CSR_MDCFGINFO_Type::b
struct CSR_MDCFGINFO_Type::@16 b
Structure used for bit access.
CSR_MECCCODE_Type::b
struct CSR_MECCCODE_Type::@22 b
Structure used for bit access.
MECC_CODE_RAMID_ILM
#define MECC_CODE_RAMID_ILM
Definition: riscv_encoding.h:372
MECC_CODE_SRAMID_IC
#define MECC_CODE_SRAMID_IC
Definition: riscv_encoding.h:374
MECC_CODE_SRAMID
#define MECC_CODE_SRAMID
Definition: riscv_encoding.h:368
MECC_CODE_RAMID
#define MECC_CODE_RAMID
Definition: riscv_encoding.h:367
MILM_CTL_ILM_ECC_EN
#define MILM_CTL_ILM_ECC_EN
Definition: riscv_encoding.h:248
MCACHE_CTL_DC_DRAM_ECC_INJ_EN
#define MCACHE_CTL_DC_DRAM_ECC_INJ_EN
Definition: riscv_encoding.h:307
CSR_MDCFG_INFO
#define CSR_MDCFG_INFO
Definition: riscv_encoding.h:1110
MCACHE_CTL_DC_ECC_CHK_EN
#define MCACHE_CTL_DC_ECC_CHK_EN
Definition: riscv_encoding.h:308
MCACHE_CTL_IC_ECC_EN
#define MCACHE_CTL_IC_ECC_EN
Definition: riscv_encoding.h:291
MECC_CODE_RAMID_TLB
#define MECC_CODE_RAMID_TLB
Definition: riscv_encoding.h:371
CSR_MCFGINFO_Type::dlm
rv_csr_t dlm
bit: 8 DLM present
Definition: core_feature_base.h:406
__SW
__STATIC_FORCEINLINE void __SW(volatile void *addr, uint32_t val)
Write 32bit value to address (32 bit)
Definition: core_feature_base.h:2288
ECC_DisableDLMECCCheck
__STATIC_FORCEINLINE void ECC_DisableDLMECCCheck(void)
Disable ECC checking for DLM.
Definition: core_feature_ecc.h:609
CSR_MECCCODE_Type::ramid
rv_csr_t ramid
bit: 16..20 The ID of RAM that has 2bit ECC error, software can clear these bits
Definition: core_feature_base.h:557
__RWMB
#define __RWMB()
Read & Write Memory barrier.
Definition: core_feature_base.h:850
CSR_MCFGINFO_Type::ecc
rv_csr_t ecc
bit: 1 ECC present
Definition: core_feature_base.h:399
ECC_ERROR_RAMID_MASK_ILM
#define ECC_ERROR_RAMID_MASK_ILM
Definition: core_feature_ecc.h:654
MCACHE_CTL_DC_TRAM_ECC_INJ_EN
#define MCACHE_CTL_DC_TRAM_ECC_INJ_EN
Definition: riscv_encoding.h:304
MDLM_CTL_DLM_EN
#define MDLM_CTL_DLM_EN
Definition: riscv_encoding.h:257
CSR_MECC_CODE
#define CSR_MECC_CODE
Definition: riscv_encoding.h:1016
CSR_MILM_CTL
#define CSR_MILM_CTL
Definition: riscv_encoding.h:1014
MCACHE_CTL_IC_ECC_CHK_EN
#define MCACHE_CTL_IC_ECC_CHK_EN
Definition: riscv_encoding.h:299