Nuclei ISA SPEC

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Nuclei RISC-V ISA

Nuclei RISC-V ISA Documentation

• 1. Introduction
• 2. Nuclei RISC-V Instruction Set Overview
  • 2.1. RISC-V ISA Modules supported by Nuclei Core
  • 2.2. Nuclei Processor Core Classes: N, NX and UX
• 3. Nuclei RISC-V Privileged Architecture
  • 3.1. RISC-V Privileged Architecture supported by Nuclei Core
  • 3.2. Privilege Modes
  • 3.3. Debug Mode
  • 3.4. Machine Sub-Mode added by Nuclei
• 4. Exception Handling in Nuclei processor core
  • 4.1. Exception Overview
  • 4.2. Exception Masking
  • 4.3. Priority of Exception
  • 4.4. Entering Exception Handling Mode
    • 4.4.1. Update the Machine Sub-Mode
  • 4.5. Exit the Exception Handling Mode
    • 4.5.1. Update the Machine Sub-Mode
  • 4.6. Exception Service Routine
  • 4.7. Exception Nesting
• 5. NMI Handling in Nuclei processor core
  • 5.1. NMI Overview
  • 5.2. NMI Masking
  • 5.3. Entering NMI Handling Mode
    • 5.3.1. Execute from the PC Defined by mnvec
    • 5.3.2. Update the CSR mcause
    • 5.3.3. Update the Privilege Mode
    • 5.3.4. Update the Machine Sub-Mode
  • 5.4. Exit the NMI Handling Mode
    • 5.4.1. Update the Machine Sub-Mode
  • 5.5. NMI Service Routine
  • 5.6. NMI Nesting
• 6. Interrupt Handling in Nuclei processor core
  • 6.1. Interrupt Overview
  • 6.2. CLIC mode and CLINT mode
    • 6.2.1. Setting CLINT or CLIC mode
    • 6.2.2. CLINT mode
    • 6.2.3. CLIC mode
  • 6.3. Interrupt Type
    • 6.3.1. External Interrupt
    • 6.3.2. Internal Interrupt
  • 6.4. Interrupt Masking
    • 6.4.1. Global Interrupt Masking
    • 6.4.2. Individual Interrupt Masking
  • 6.5. Interrupt Levels, Priorities and Arbitration
  • 6.6. (CLIC mode) Entering Interrupt Handling Mode
    • 6.6.1. Execute from a new PC
    • 6.6.2. Update the Privilege Mode
    • 6.6.3. Update the Machine Sub-Mode
    • 6.6.4. Update the CSR mepc
    • 6.6.5. Update the CSRs mcause and mstatus
  • 6.7. (CLIC mode) Exit the Interrupt Handling Mode
    • 6.7.1. Executing from the Address Defined by mepc
    • 6.7.2. Update the CSRs mcause and mstatus
    • 6.7.3. Update the Privilege Mode
    • 6.7.4. Update the Machine Sub-Mode
  • 6.8. (CLIC mode) Interrupt Vector Table
  • 6.9. Context Saving and Restoring
  • 6.10. Interrupt Response Latency
  • 6.11. (CLIC mode) Interrupt Preemption
  • 6.12. (CLIC mode) Interrupt Tail-Chaining
  • 6.13. (CLIC mode) Vectored and Non-Vectored Processing Mode of Interrupts
    • 6.13.1. Non-Vectored Processing Mode
    • 6.13.2. Vectored Processing Mode
• 7. Nesting of Interrupt, NMI and Exception
  • 7.1. Two Levels of NMI/Exception State Save Stacks
  • 7.2. Enter NMI/Exception Preemption
  • 7.3. Exit NMI/Exception Preemption
• 8. TIMER Unit Introduction
  • 8.1. TIMER Overview
  • 8.2. TIMER Registers
    • 8.2.1. Time Counter Register mtime
    • 8.2.2. Generate the Timer Interrupt through mtime and mtimecmp
    • 8.2.3. Control the Timer Counter through mtimectl
    • 8.2.4. Generating the Software Interrupt through msip
    • 8.2.5. Generating the Soft-Reset Request
• 9. PLIC Unit Introduction
  • 9.1. PLIC Overview
  • 9.2. PLIC Registers
• 10. ECLIC Unit Introduction
  • 10.1. ECLIC Overview
  • 10.2. ECLIC interrupt target
  • 10.3. ECLIC Interrupt Source
  • 10.4. ECLIC Interrupt Source ID
  • 10.5. ECLIC Registers
    • 10.5.1. cliccfg
    • 10.5.2. clicinfo
    • 10.5.3. mth
    • 10.5.4. clicintip[i]
    • 10.5.5. clicintie[i]
    • 10.5.6. clicintattr[i]
    • 10.5.7. clicintctl[i]
  • 10.6. ECLIC Interrupt Enable Bit (IE)
  • 10.7. ECLIC Interrupt Pending Bit (IP)
  • 10.8. ECLIC Interrupt Source Level or Edge-Triggered Attribute
  • 10.9. ECLIC Interrupt Level and Priority
  • 10.10. ECLIC Interrupt Vectored and Non-Vectored Processing Mode
  • 10.11. ECLIC Interrupt Threshold Level
  • 10.12. ECLIC Interrupt Arbitration Mechanism
  • 10.13. ECLIC Interrupt Taken, Preemption and Tail-Chaining
• 11. ECLIC and PLIC Connection Diagram
  • 11.1. Single-core with ECLIC configured only
  • 11.2. Single-core with PLIC/ECLIC configured and PLIC enabled
  • 11.3. Single-core with PLIC/ECLIC configured and ECLIC enabled
  • 11.4. Multi-core with PLIC configured only
• 12. PMP Introduction
  • 12.1. PMP Overview
  • 12.2. PMP Specific Features to Nuclei Core
    • 12.2.1. Configurable PMP Entries Number
    • 12.2.2. No support to TOR mode in A field of pmpcfg<x> registers
    • 12.2.3. Corner cases for Boundary Crossing
• 13. MMU Introduction
  • 13.1. MMU Overview
  • 13.2. MMU Specific Features to Nuclei Core
    • 13.2.1. Configurable TLB Entries Number
• 14. Nuclei CCM Mechanism
• 15. WFI/WFE Low-Power Mechanism
  • 15.1. Enter the Sleep Mode
  • 15.2. Wait for Interrupt
  • 15.3. Wait for Event
  • 15.4. Exit the Sleep Mode
    • 15.4.1. Wake Up by NMI
    • 15.4.2. Wake Up by Interrupt
    • 15.4.3. Wake Up by Event
    • 15.4.4. Wake Up by Debug Request
• 16. Nuclei processor core CSRs Descriptions
  • 16.1. CSR Overview
  • 16.2. Nuclei processor core CSRs List
  • 16.3. Accessibility of CSRs in the Nuclei processor core
  • 16.4. RISC-V Standard CSRs Supported in the Nuclei processor core
    • 16.4.1. mie
    • 16.4.2. mip
    • 16.4.3. mhartid
    • 16.4.4. mepc
    • 16.4.5. mtvec
    • 16.4.6. mcause
    • 16.4.7. mcycle and mcycleh
    • 16.4.8. minstret and minstreth
  • 16.5. Nuclei processor core Customized CSR
    • 16.5.1. mcountinhibit
    • 16.5.2. milm_ctl
    • 16.5.3. mdlm_ctl
    • 16.5.4. mnvec
    • 16.5.5. msubm
    • 16.5.6. mdcause
    • 16.5.7. mcache_ctl
    • 16.5.8. mmisc_ctl
    • 16.5.9. msavestatus
    • 16.5.10. msaveepc1 and msaveepc2
    • 16.5.11. msavecause1 and msavecause2
    • 16.5.12. msavedcause1 and msavedcause2
    • 16.5.13. mtvt
    • 16.5.14. mnxti
    • 16.5.15. mintstatus
    • 16.5.16. mtvt2
    • 16.5.17. jalmnxti
    • 16.5.18. pushmsubm
    • 16.5.19. pushmcause
    • 16.5.20. pushmepc
    • 16.5.21. mscratchcsw
    • 16.5.22. mscratchcswl
    • 16.5.23. sleepvalue
    • 16.5.24. txevt
    • 16.5.25. wfe
    • 16.5.26. ucode
    • 16.5.27. mcfg_info
    • 16.5.28. micfg_info
    • 16.5.29. mdcfg_info
    • 16.5.30. mtlbcfg_info
    • 16.5.31. mppicfg_info
    • 16.5.32. mfiocfg_info
    • 16.5.33. mecc_lock
    • 16.5.34. mecc_code
    • 16.5.35. mtlb_ctl
• 17. ECC Introduction
  • 17.1. Nuclei ECC mechanism
  • 17.2. Nuclei ECC CSRs
• 18. TEE Introduction
• 19. Packed-SIMD DSP Introduction
• 20. User Extended Introduction
• 21. Revision History
  • 21.1. 2.0.3
  • 21.2. 2.0
  • 21.3. 1.5

Miscellaneous

Miscellaneous Documentation

• 1. Appendix
• 2. Glossary

Indices and tables

• Index

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