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Nuclei RISC-V ISA Documentation

  • 1. Introduction
  • 2. Nuclei RISC-V Instruction Set Overview
  • 3. Nuclei RISC-V Privileged Architecture
  • 4. Exception Handling in Nuclei processor core
  • 5. NMI Handling in Nuclei processor core
  • 6. Interrupt Handling in Nuclei processor core
  • 7. Nesting of Interrupt, NMI and Exception
  • 8. TIMER Unit Introduction
  • 9. PLIC Unit Introduction
  • 10. ECLIC Unit Introduction
  • 11. ECLIC and PLIC Connection Diagram
  • 12. PMP Introduction
  • 13. MMU Introduction
  • 14. Nuclei CCM Mechanism
  • 15. WFI/WFE Low-Power Mechanism
  • 16. Nuclei processor core CSRs Descriptions
  • 17. ECC Introduction
  • 18. TEE Introduction
  • 19. Packed-SIMD DSP Introduction
  • 20. User Extended Introduction
  • 21. Revision History

Miscellaneous Documentation

  • 1. Appendix
  • 2. Glossary
Nuclei Spec 2021
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  • 1. Appendix
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1. Appendix

  • Nuclei SDK: https://github.com/Nuclei-Software/nuclei-sdk

  • NMSIS: https://github.com/Nuclei-Software/NMSIS

  • Nuclei RISC-V IP Products: https://www.nucleisys.com/product.php

  • RISC-V MCU Community Website: http://www.riscv-mcu.com/

  • CLIC Specification: https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc

  • PLIC Specification: https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc

  • RISC-V Specifications: https://riscv.org/technical/specifications/

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