13. MMU Introduction

13.1. MMU Overview

Nuclei processor UX class core can have MMU (Memory Management Unit) configured for Linux capable applications, which implements the SV39 mode defined in RISC-V privileged specification, to support Page-Based 39-bit Virtual-Memory System, which can be used for converting Virtual-Address to Physical-Address and corresponding Permission Checking. MMU is part of RISC-V standard privileged architecture specification. User can easily get the original copy from Nuclei User Center website or from other public channels.

13.2. MMU Specific Features to Nuclei Core

In order to simplify the hardware implementation, or there are some features are intrinsically hardware implementation relevant, Nuclei processor core have some MMU specific features, which is detailed at next sections.

13.2.1. Configurable TLB Entries Number

MMU has two level TLB (Translation Lookaside Buffer) implemented to cache the page tables for fast subsequent accessing: jTLB and i/d-tlb; jTLB is the joint TLB for both instruction and data page table, jTLB can be configured as 32, 64 or 128 entries; i/d-tlb is dedicate for instruction/data page table, each has 8 entries; i/d-tlb will be accessed first, if miss then jTLB will be accessed.

MMU supports 4KB, 2MB and 1GB page types, which uses Hardware Translation Table Walk mechanism to fetch page tables from memory when TLB miss without software handling.