9. PLIC Unit Introduction

9.1. PLIC Overview

For the Linux capable applications or symmetric multi-processor (SMP) applications, Nuclei processor core have been equipped with a Platform-Level Interrupt Controller (PLIC), which is part of RISC-V standard privileged architecture specification (riscv-privileged-v1.10.pdf), user can easily get the original copy (riscv-privileged-v1.10.pdf) from Nuclei User Center website or from other public channels.

Note

9.2. PLIC Registers

The RISC-V standard privileged architecture specification does not specify the exact register offset for PLIC. The Nuclei processor core implements PLIC as a memory-mapped unit:

Table 9.1 The address offset of registers in the PLIC unit

Offset

Permission

Register

Default Value

0x0000

R

Interrupt Source Number

N/A

0x0004

RW

Source 1 priority

0x0

0x0008

RW

Source 2 priority

0x0

0x0FFC

RW

Source 1023 priority

0x0

0x1000

R

Start of pending array

0x0

0x107C

R

End of pending array

0x0

0x1100

RW

Source enables

0x0

0x1200

RW

Priority threshold

0x0

0x1204

RW

Claim/Complete

0x0

0x1208

R

EIP

0x0

Note

  • PLIC registers only support aligned access which is the size of word.

  • The above R means read-only, and any write to this read-only register will be ignored without generating bus error.

  • The PLIC unit may not be configured to support 1024 interrupt sources. If an interrupt is not present in the hardware, the corresponding registers of memory locations appear hardwired to zero.

  • The address space of PLIC registers is the range from 0x0000 to 0x1FFF. The value in an address other than the address listed in the above table is constant 0.