3. Nuclei RISC-V Privileged Architecture

3.1. RISC-V Privileged Architecture supported by Nuclei Core

Nuclei processor core follows the RISC-V privileged architecture standard (riscv-privileged-v1.10.pdf), user can easily get the original copy (riscv-privileged-v1.10.pdf) from Nuclei User Center website or from other public channels.

Basically, Nuclei processor core are following and compatible to RISC-V standard privileged architecture, but there might be some additions and enhancements to the original standard spec.

To respect the RISC-V standard, this document may not repeat the contents of original RISC-V standard, but will highlight the additions and enhancements of Nuclei defined.

3.2. Privilege Modes

Following the RISC-V privileged architecture standard, Nuclei processor core support following Privilege Modes:

  • Machine Mode

  • Supervisor Mode

  • User Mode

Note: According to the RISC-V standard privileged architecture, there is no way for the software to check current privileged mode (e.g., machine mode or user mode).

Please refer to RISC-V standard privileged architecture for more details.

3.3. Debug Mode

Nuclei processor core also support debug mode to support off-chip debugging.

Nuclei processor core follows the RISC-V debug standard (riscv-debug-spec-0.13.pdf), user can easily get the original copy (riscv-debug-spec-0.13.pdf) from Nuclei User Center website or from other public channels.

3.4. Machine Sub-Mode added by Nuclei

Besides the above mentioned standard Privilege Modes, Nuclei processor core further defined 4 types of sub-mode, to differentiate the exact machine mode status, called Machine Sub-Mode:

  • Normal Machine Mode

    • The processor core will be under this default sub-mode when out of reset.

    • If the processor core does not encounter exception, NMI, interrupt, debug request, or does not switch mode explicitly, then it will remain in this sub-mode.

  • Exception Handling Mode

  • NMI Handling Mode

  • Interrupt Handling Mode

Nuclei defined a CSR register msubm to reflect processor core’s current machine sub-mode (msubm.TYP) and previous machine sub-mode (msubm.PTYP). Please refer to msubm for more details of CSR register msubm.