11. ECLIC and PLIC Connection Diagram
The ECLIC and PLIC are independently configurable, so they can be co-existed or not, depends on configurations. The key points are as followings:
For the single-core real-time or micro-controller applications, it is recommended to just have ECLIC configured, as depicted in Interrupt Connection (for single-core with ECLIC configured only).
For the single-core Linux capable applications, it is recommended to configure PLIC. But in this case, the ECLIC can also be configured, hence, PLIC and ECLIC become coexisting.
If the ECLIC is enabled by software, then the interrupts will be handled by ECLIC, and the PLIC will be bypassed, as depicted in Interrupt Connection (for single-core with PLIC/ECLIC configured and PLIC enabled).
In this mode, the hardware of UX class core can also worked as microcontroller, i.e., Nuclei UX class core is downward-compatible to Nuclei NX class core.
If the ECLIC is disabled by software, then the interrupts will be handled by PLIC, and the ECLIC will be bypassed, as depicted in Interrupt Connection (for single-core with PLIC/ECLIC configured and ECLIC enabled).
For the symmetric multi-processor (SMP) Linux capable applications, it is recommended to just have PLIC configured only, as depicted in Interrupt Connection (for multi-core with PLIC configured only).
11.1. Single-core with ECLIC configured only
The following figure Interrupt Connection (for single-core with ECLIC configured only) is for single-core with ECLIC unit configured only.

Fig. 11.1 Interrupt Connection (for single-core with ECLIC configured only)
11.2. Single-core with PLIC/ECLIC configured and PLIC enabled
The following figure Interrupt Connection (for single-core with PLIC/ECLIC configured and PLIC enabled) is for single-core with PLIC/ECLIC configured and PLIC enabled.

Fig. 11.2 Interrupt Connection (for single-core with PLIC/ECLIC configured and PLIC enabled)
11.3. Single-core with PLIC/ECLIC configured and ECLIC enabled
The following figure Interrupt Connection (for single-core with PLIC/ECLIC configured and ECLIC enabled) is for single-core with PLIC/ECLIC configured and ECLIC enabled.

Fig. 11.3 Interrupt Connection (for single-core with PLIC/ECLIC configured and ECLIC enabled)
11.4. Multi-core with PLIC configured only
The following figure Interrupt Connection (for multi-core with PLIC configured only) is for Multi-core with PLIC configured only.

Fig. 11.4 Interrupt Connection (for multi-core with PLIC configured only)