17. ECC Introduction
Nuclei processor core can optionally support the ECC protection on ILM, DLM, I-Cache, D-Cache and TLB, if configured.
17.1. Nuclei ECC mechanism
SECDED: Single Error Correction, Double Error Detection
For RV32/64, ECC protection granularity:
DLM and D-Cache Data-Ram: 32-bit;
ILM and I-Cache Data-Ram: 64-bit;
I/D-Cache Tag-Ram and TLB: their Actual Size;
ECC update policy:
Full Write: 32/64-bit data/instruction and corresponding ECC code will be updated simultaneously;
Partial Write: Read-Modify-Write sequency will be triggered when 8/16-bit data write operation;
ECC control policy:
ECC and ECC Exception can be enable/disable separately on ILM, DLM, I-Cache, D-Cache and TLB;
1-bit ECC error will be corrected automatically by HW and will not trigger ECC exception when ECC is enabled;
2-bit ECC error will trigger ECC exception only when both ECC is enabled and ECC Exception is also enabled, or 2-bit ECC error exception will not be triggered;
2-bit ECC error exception cases:
Pipeline: IFU instruction fetch will report precise exception, LSU load/store data will report imprecise exception;
I-Cache CCM (Control and Maintenance): for by-ADDR operation, store access fault will be reported, mecc_code.RAMID will be set to 1, mtval/stval will be cleared to 0; for INV_ALL operation, I-Cache will be invalidated directly without checking ECC error;
D-Cache CCM (Control and Maintenance): for by-ADDR operation, store access fault will be reported, mecc_code. RAMID will be set to 1 (RAMID.tlb will be set if in VA-PA translation stage, or RAMID.dcache will be set if in D-Cache accessing stage), mtval/stval will be cleared to 0; the by-ALL operation will be abort if any cacheline has 2-bit ECC error, store access fault will be reported and mecc_code.RAMID.dcache will be set to 1, mtval/stval will be cleared to 0;
D-Cache eviction (cpbk): imprecise exception will be reported, mecc_code.RAMID.dcache will be set to 1;
Slave Port: 2-bit ECC error will be reported as Bus Error;
Debug SBA: 2-bit ECC error will be reported as Bus Error;
SFENCE: for by-ADDR operation, store access fault will be reported, mecc_code.RAMID.tlb will be set to 1 and mtval/stval will be cleared to 0; for by-ALL operation, TLB will be invalided directly without checking ECC error;
mecc_code.RAMID will set to 1 when 2-bit ECC error occurs on ILM/DLM/I-Cache/D-Cache/TLB; However RAMID is set to 1 does not indicate that ECC exception will be triggered, such as, 2-bit ECC error occurs in Slave Port or Debug SBA, or an instruction fetching has 2-bit ECC error but be flushed later in pipeline;
2-bit ECC error will be indicated in mecc_code.RAMID but not in mdcause, and ECC exception will be reported as access fault but not page fault, so the access fault handler needs to check the mecc_code.RAMID for 2-bit ECC error;
2-bit ECC error signals will be list as output in the CORE top module for SoC integration;
ECC exception will be reported if 2-bit ECC error occurs on any way of I-Cache/D-Cache/TLB when in Tag Ram comparing stage, even there is a hit way and this hit way has no 2-bit ECC error;
Access fault will be reported other than page fault when TLB has 2-bit ECC error, to make this ECC exception handled in M-mode;
1-bit ECC error cases:
1-bit ECC error will be corrected automatically by HW without triggering exception;
mecc_code.SRAMID will be set to 1 when 1-bit ECC error occurs on ILM/DLM/I-Cache/D-Cache/TLB;
1-bit ECC error signals will be list as output in the CORE top module for SoC integration;
ECC error injection:
mecc_code.Code can be selected to update the ILM (ILM is accessible by LSU) and DLM by STORE instruction, without using the ECC code generated by HW;
mecc_code.Code can be selected to update the I-Cache/D-Cache Tag Ram or Data Ram by Linefill when cache miss, without using the ECC code generated by HW;
mecc_code.Code can be selected to update the TLB Tag Ram or Data Ram by Refill when TLB miss, without using the ECC code generated by HW;
ECC lock:
ECC related CSRs cannot be modified after ECC is locked unless reset, for security;
17.2. Nuclei ECC CSRs
ECC CSRs are all Nuclei customized ones, see below:
Type |
CSR ADDR |
R/W |
Name |
Description |
---|---|---|---|---|
ECC CSRs |
0xFC0 |
MRO |
micfg_info |
ILM/I-Cache configuration info |
0xFC1 |
MRO |
mdcfg_info |
DLM/D-Cache configuration info |
|
0xFC2 |
MRO |
mcfg_info |
Core configuration info |
|
0xFC3 |
MRO |
mtlbcfg_info |
TLB configuration info |
|
0x7C0 |
MRW |
milm_ctl |
ILM control |
|
0x7C1 |
MRW |
mdlm_ctl |
DLM control |
|
0x7C2 |
MRW |
mecc_code |
ECC code injection |
|
0x7DD |
MRW |
mtlb_ctl |
TLB control |
|
0x7DE |
MRW |
mecc_lock |
ECC lock |
|
0x7CA |
MRW |
mcache_ctl |
Cache control |