PMA Functions

Functions that set/disable/enable different attribute type(Device/Non-Cacheable/Cacheable) memory regions, or get region info. More...

Data Structures
struct	pma_config

Macros
#define	PMA_REGION_TYPE_SECSHARE   (1UL << 3)
	Set this region shareable between secure world and non-secure world, or else default is invalid. More...
#define	PMA_REGION_TYPE_NC   (1UL << 2)
	Set this region Non-Cacheable, or else default is invalid. More...
#define	PMA_REGION_TYPE_DEV   (1UL << 1)
	Set this region Device, or else default is invalid. More...
#define	PMA_REGION_TYPE_CA   (0)
	Set this region Cacheable, which is default. More...
#define	PMA_REGION_ENA   (1UL << 0)
	Enable this region, then the region type will take effect. More...
#define	PMA_REGION_DIS   (0)
	Disable this region. More...

Functions
__STATIC_INLINE long	PMA_SetRegion (unsigned long entry_idx, pma_config *pma_cfg)
	Configure one region in machine mode. More...
__STATIC_INLINE long	PMA_GetRegion (unsigned long entry_idx, pma_config *pma_cfg)
	Get the region info in machine mode. More...
__STATIC_INLINE long	PMA_SetRegion_S (unsigned long entry_idx, pma_config *pma_cfg)
	Configure one region for Secure S-Mode world to share with Non-Secure S-Mode world. More...
__STATIC_INLINE long	PMA_GetRegion_S (unsigned long entry_idx, pma_config *pma_cfg)
	Get the region info of Secure S-Mode world sharing with Non-Secure S-Mode world. More...
__STATIC_FORCEINLINE void	PMA_EnableHwDevRegion (unsigned long entry_idx)
	Enable hardware defined Device regions. More...
__STATIC_FORCEINLINE void	PMA_DisableHwDevRegion (unsigned long entry_idx)
	Disable hardware defined Device regions. More...
__STATIC_FORCEINLINE void	PMA_EnableHwNCRegion (unsigned long entry_idx)
	Enable hardware defined Non-Cacheable regions. More...
__STATIC_FORCEINLINE void	PMA_DisableHwNCRegion (unsigned long entry_idx)
	Disable hardware defined Non-Cacheable regions. More...
__STATIC_FORCEINLINE void	PMA_EnableHwCARegion (unsigned long entry_idx)
	Enable hardware defined Cacheable regions. More...
__STATIC_FORCEINLINE void	PMA_DisableHwCARegion (unsigned long entry_idx)
	Disable hardware defined Cacheable regions. More...

Detailed Description

Functions that set/disable/enable different attribute type(Device/Non-Cacheable/Cacheable) memory regions, or get region info.

Nuclei provide Physical Memory Attribute(PMA) to define the attribute of memory.PMA will affect CPU access memory behavior.

PMA are split into three attributes:

• Device(abbreviated as 'DEV') Attribute
• Non-Cacheable(abbreviated as 'NC') Attribute
• Cacheable(abbreviated as 'CA') Attribute And correspondingly, the whole memory region are split into three regions: DEV Region/NC Region/CA Region

Hardware provide some software CSR to set the pma by mattri(n)_base/mattri(n)_mask/sattri(n)_base/sattri(n)_mask

Hardware defined PMA regions(up to 8 DEV/NC/CA regions) can be disable or enable by CSR mmacro_dev_en/mmacro_noc_en/mmacro_ca_en

Macro Definition Documentation

PMA_REGION_DIS

#define PMA_REGION_DIS   (0)

Disable this region.

Definition at line 58 of file core_feature_pma.h.

PMA_REGION_ENA

#define PMA_REGION_ENA   (1UL << 0)

Enable this region, then the region type will take effect.

Definition at line 57 of file core_feature_pma.h.

PMA_REGION_TYPE_CA

#define PMA_REGION_TYPE_CA   (0)

Set this region Cacheable, which is default.

Definition at line 56 of file core_feature_pma.h.

PMA_REGION_TYPE_DEV

#define PMA_REGION_TYPE_DEV   (1UL << 1)

Set this region Device, or else default is invalid.

Definition at line 55 of file core_feature_pma.h.

PMA_REGION_TYPE_NC

#define PMA_REGION_TYPE_NC   (1UL << 2)

Set this region Non-Cacheable, or else default is invalid.

Definition at line 54 of file core_feature_pma.h.

PMA_REGION_TYPE_SECSHARE

#define PMA_REGION_TYPE_SECSHARE   (1UL << 3)

Set this region shareable between secure world and non-secure world, or else default is invalid.

Definition at line 53 of file core_feature_pma.h.

Function Documentation

PMA_DisableHwCARegion()

__STATIC_FORCEINLINE void PMA_DisableHwCARegion

(

unsigned long

entry_idx

)

Disable hardware defined Cacheable regions.

Disable Cacheable region by corresponding index

Parameters

[in]

entry_idx

Index(0-7)

Remarks

• This function can be called in M-Mode only.
• When there is no entry_idx, this field is tied to 0
• For each region entry's address/size/attribute detail refers to RTL Configuration Stage
• The regions can be overlapped as the prority: Non-Cacheable > Cacheable > Device, but especially be careful not to overlap software's instruction/data sections by Device, or overlap Device(like uart) memory by Cacheable

See also

• PMA_EnableHwCARegion

Definition at line 351 of file core_feature_pma.h.

{
    __RV_CSR_CLEAR(CSR_MMACRO_CA_EN, 1UL << entry_idx);
}

References __RV_CSR_CLEAR, and CSR_MMACRO_CA_EN.

PMA_DisableHwDevRegion()

__STATIC_FORCEINLINE void PMA_DisableHwDevRegion

(

unsigned long

entry_idx

)

Disable hardware defined Device regions.

Disable Device region by corresponding index

Parameters

[in]

entry_idx

Index(0-7)

Remarks

• This function can be called in M-Mode only.
• When there is no entry_idx, this field is tied to 0
• For each region entry's address/size/attribute detail refers to RTL Configuration Stage
• The regions can be overlapped as the prority: Non-Cacheable > Cacheable > Device, but especially be careful not to overlap software's instruction/data sections by Device, or overlap Device(like uart) memory by Cacheable

See also

• PMA_EnableHwDevRegion

Definition at line 279 of file core_feature_pma.h.

{
    __RV_CSR_CLEAR(CSR_MMACRO_DEV_EN, 1UL << entry_idx);
}

References __RV_CSR_CLEAR, and CSR_MMACRO_DEV_EN.

PMA_DisableHwNCRegion()

__STATIC_FORCEINLINE void PMA_DisableHwNCRegion

(

unsigned long

entry_idx

)

Disable hardware defined Non-Cacheable regions.

Disable Non-Cacheable region by corresponding index

Parameters

[in]

entry_idx

Index(0-7)

Remarks

• This function can be called in M-Mode only.
• When there is no entry_idx, this field is tied to 0
• For each region entry's address/size/attribute detail refers to RTL Configuration Stage
• The regions can be overlapped as the prority: Non-Cacheable > Cacheable > Device, but especially be careful not to overlap software's instruction/data sections by Device, or overlap Device(like uart) memory by Cacheable

See also

• PMA_EnableHwNCRegion

Definition at line 315 of file core_feature_pma.h.

{
    __RV_CSR_CLEAR(CSR_MMACRO_NOC_EN, 1UL << entry_idx);
}

References __RV_CSR_CLEAR, and CSR_MMACRO_NOC_EN.

PMA_EnableHwCARegion()

__STATIC_FORCEINLINE void PMA_EnableHwCARegion

(

unsigned long

entry_idx

)

Enable hardware defined Cacheable regions.

Enable Cacheable region by corresponding index

Parameters

[in]

entry_idx

Index(0-7)

Remarks

• This function can be called in M-Mode only.
• When there is no entry_idx, this field is tied to 0
• For each region entry's address/size/attribute detail refers to RTL Configuration Stage
• The regions can be overlapped as the prority: Non-Cacheable > Cacheable > Device, but especially be careful not to overlap software's instruction/data sections by Device, or overlap Device(like uart) memory by Cacheable

See also

• PMA_DisableHwCARegion

Definition at line 333 of file core_feature_pma.h.

{
    __RV_CSR_SET(CSR_MMACRO_CA_EN, 1UL << entry_idx);
}

References __RV_CSR_SET, and CSR_MMACRO_CA_EN.

PMA_EnableHwDevRegion()

__STATIC_FORCEINLINE void PMA_EnableHwDevRegion

(

unsigned long

entry_idx

)

Enable hardware defined Device regions.

Enable Device region by corresponding index

Parameters

[in]

entry_idx

Index(0-7)

Remarks

• This function can be called in M-Mode only.
• When there is no entry_idx, this field is tied to 0
• For each region entry's address/size/attribute detail refers to RTL Configuration Stage
• The regions can be overlapped as the prority: Non-Cacheable > Cacheable > Device, but especially be careful not to overlap software's instruction/data sections by Device, or overlap Device(like uart) memory by Cacheable

See also

• PMA_DisableHwDevRegion

Definition at line 261 of file core_feature_pma.h.

{
    __RV_CSR_SET(CSR_MMACRO_DEV_EN, 1UL << entry_idx);
}

References __RV_CSR_SET, and CSR_MMACRO_DEV_EN.

PMA_EnableHwNCRegion()

__STATIC_FORCEINLINE void PMA_EnableHwNCRegion

(

unsigned long

entry_idx

)

Enable hardware defined Non-Cacheable regions.

Enable Non-Cacheable region by corresponding index

Parameters

[in]

entry_idx

Index(0-7)

Remarks

• This function can be called in M-Mode only.
• When there is no entry_idx, this field is tied to 0
• For each region entry's address/size/attribute detail refers to RTL Configuration Stage
• The regions can be overlapped as the prority: Non-Cacheable > Cacheable > Device, but especially be careful not to overlap software's instruction/data sections by Device, or overlap Device(like uart) memory by Cacheable

See also

• PMA_DisableHwNCRegion

Definition at line 297 of file core_feature_pma.h.

{
    __RV_CSR_SET(CSR_MMACRO_NOC_EN, 1UL << entry_idx);
}

References __RV_CSR_SET, and CSR_MMACRO_NOC_EN.

PMA_GetRegion()

__STATIC_INLINE long PMA_GetRegion	(	unsigned long	entry_idx,
		pma_config *	pma_cfg
	)

Get the region info in machine mode.

Read the region(0-n) info of base address/region type/region size/enable status

Parameters

[in]	entry_idx	Index(0-n) of paired mattri(n)_mask and mattri(n)_base
[out]	pma_cfg	Region info read

Returns

0 if success, else -1

Remarks

• entry_idx(0-n) depends on number of paired mattri(n)_mask and mattri(n)_base, refer to Nuclei ISA specifications
• Not all the entry_idx(0-n) could set to all the types freely, refer to Nuclei ISA specifications

Definition at line 139 of file core_feature_pma.h.

{
    rv_csr_t mask, base;
    uint32_t mpasize = *(uint32_t *)__IINFO_MPASIZE_ADDR;
 
    if ((entry_idx + 1) > __PMA_CSR_NUM) {
        return -1;
    }
 
    switch (entry_idx) {
        case 0: mask = __RV_CSR_READ(CSR_MATTRI0_MASK); base = __RV_CSR_READ(CSR_MATTRI0_BASE); break;
        case 1: mask = __RV_CSR_READ(CSR_MATTRI1_MASK); base = __RV_CSR_READ(CSR_MATTRI1_BASE); break;
        case 2: mask = __RV_CSR_READ(CSR_MATTRI2_MASK); base = __RV_CSR_READ(CSR_MATTRI2_BASE); break;
        case 3: mask = __RV_CSR_READ(CSR_MATTRI3_MASK); base = __RV_CSR_READ(CSR_MATTRI3_BASE); break;
        case 4: mask = __RV_CSR_READ(CSR_MATTRI4_MASK); base = __RV_CSR_READ(CSR_MATTRI4_BASE); break;
        case 5: mask = __RV_CSR_READ(CSR_MATTRI5_MASK); base = __RV_CSR_READ(CSR_MATTRI5_BASE); break;
        case 6: mask = __RV_CSR_READ(CSR_MATTRI6_MASK); base = __RV_CSR_READ(CSR_MATTRI6_BASE); break;
        case 7: mask = __RV_CSR_READ(CSR_MATTRI7_MASK); base = __RV_CSR_READ(CSR_MATTRI7_BASE); break;
        default: return -1;
    }
 
    pma_cfg->region_type = (unsigned long)(base & 0x0E);
    pma_cfg->region_base = (unsigned long)((base >> 12) << 12);
    pma_cfg->region_size = (unsigned long)(1UL << (mask == 0 ? mpasize : __CTZ(mask)));
    pma_cfg->region_enable = (uint16_t)(base & 0x01);
 
    return 0;
}

References __CTZ(), __RV_CSR_READ, CSR_MATTRI0_BASE, CSR_MATTRI0_MASK, CSR_MATTRI1_BASE, CSR_MATTRI1_MASK, CSR_MATTRI2_BASE, CSR_MATTRI2_MASK, CSR_MATTRI3_BASE, CSR_MATTRI3_MASK, CSR_MATTRI4_BASE, CSR_MATTRI4_MASK, CSR_MATTRI5_BASE, CSR_MATTRI5_MASK, CSR_MATTRI6_BASE, CSR_MATTRI6_MASK, CSR_MATTRI7_BASE, CSR_MATTRI7_MASK, pma_config::region_base, pma_config::region_enable, pma_config::region_size, and pma_config::region_type.

PMA_GetRegion_S()

__STATIC_INLINE long PMA_GetRegion_S	(	unsigned long	entry_idx,
		pma_config *	pma_cfg
	)

Get the region info of Secure S-Mode world sharing with Non-Secure S-Mode world.

Read the region(0-7) info of base address/region size/enable status

Parameters

[in]	entry_idx	Index(0-7) of paired sattri(n)_mask and sattri(n)_base
[out]	pma_cfg	Region info read

Returns

0 if success, else -1

Remarks

• Unlike mattri(n)_base, there's no DEV Region/NC Region/CA Region type

Definition at line 219 of file core_feature_pma.h.

{
    rv_csr_t mask, base;
    uint32_t mpasize = *(uint32_t *)__IINFO_MPASIZE_ADDR;
 
    if ((entry_idx + 1) > __PMA_SEC_CSR_NUM) {
        return -1;
    }
 
    switch (entry_idx) {
        case 0: mask = __RV_CSR_READ(CSR_SATTRI0_MASK); base = __RV_CSR_READ(CSR_SATTRI0_BASE); break;
        case 1: mask = __RV_CSR_READ(CSR_SATTRI1_MASK); base = __RV_CSR_READ(CSR_SATTRI1_BASE); break;
        case 2: mask = __RV_CSR_READ(CSR_SATTRI2_MASK); base = __RV_CSR_READ(CSR_SATTRI2_BASE); break;
        case 3: mask = __RV_CSR_READ(CSR_SATTRI3_MASK); base = __RV_CSR_READ(CSR_SATTRI3_BASE); break;
        case 4: mask = __RV_CSR_READ(CSR_SATTRI4_MASK); base = __RV_CSR_READ(CSR_SATTRI4_BASE); break;
        case 5: mask = __RV_CSR_READ(CSR_SATTRI5_MASK); base = __RV_CSR_READ(CSR_SATTRI5_BASE); break;
        case 6: mask = __RV_CSR_READ(CSR_SATTRI6_MASK); base = __RV_CSR_READ(CSR_SATTRI6_BASE); break;
        case 7: mask = __RV_CSR_READ(CSR_SATTRI7_MASK); base = __RV_CSR_READ(CSR_SATTRI7_BASE); break;
        default: return -1;
    }
 
    pma_cfg->region_base = (unsigned long)((base >> 12) << 12);
    pma_cfg->region_size = (unsigned long)(1UL << (mask == 0 ? mpasize : __CTZ(mask)));
    pma_cfg->region_enable = (uint16_t)(base & 0x01);
 
    return 0;
}

References __CTZ(), __RV_CSR_READ, CSR_SATTRI0_BASE, CSR_SATTRI0_MASK, CSR_SATTRI1_BASE, CSR_SATTRI1_MASK, CSR_SATTRI2_BASE, CSR_SATTRI2_MASK, CSR_SATTRI3_BASE, CSR_SATTRI3_MASK, CSR_SATTRI4_BASE, CSR_SATTRI4_MASK, CSR_SATTRI5_BASE, CSR_SATTRI5_MASK, CSR_SATTRI6_BASE, CSR_SATTRI6_MASK, CSR_SATTRI7_BASE, CSR_SATTRI7_MASK, pma_config::region_base, pma_config::region_enable, and pma_config::region_size.

PMA_SetRegion()

__STATIC_INLINE long PMA_SetRegion	(	unsigned long	entry_idx,
		pma_config *	pma_cfg
	)

Configure one region in machine mode.

Set the region(0-n) info of base address/region type/region size/enable status

Parameters

[in]	entry_idx	Index(0-n) of paired mattri(n)_mask and mattri(n)_base
[in]	pma_cfg	Region info to configure

Returns

-1 failure, else 0 success

Remarks

• The entry_idx(0-n) depends on number of paired mattri(n)_mask and mattri(n)_base, refer to Nuclei ISA specifications
• Not all the entry_idx(0-n) could set to all the types freely, refer to Nuclei ISA specifications
• The mattri(n)_mask must be written first, before mattri(n)_base, which the api takes care of.
• The higher bits of mattri(n)_mask should be continuously 1, the remaining lower bits should be all 0 and the number (N) of 0 means the size of this region(2^N bytes)
• Region granularity is 4KB, so the low 12-bits of mattri(n)_mask must be 0, which the api takes care of
• The regions can be overlapped as the prority: Non-Cacheable > Cacheable > Device, but especially be careful not to overlap software's instruction/data sections by Device, or overlap Device(like uart) memory by Cacheable

Definition at line 99 of file core_feature_pma.h.

{
    // 4KB aligned
    unsigned long size = (pma_cfg->region_size >> 12) << 12;
    unsigned long base_addr = (pma_cfg->region_base >> 12) << 12;
 
    if ((entry_idx + 1) > __PMA_CSR_NUM) {
        return -1;
    }
 
    rv_csr_t mask = (unsigned long)(~(size - 1));
    rv_csr_t base = pma_cfg->region_type | base_addr | pma_cfg->region_enable;
 
    switch (entry_idx) {
        // Bit[MXLEN-1:PA_SIZE] of mattri(n)_mask is reserved 0
        case 0: __RV_CSR_WRITE(CSR_MATTRI0_MASK, mask); __RV_CSR_WRITE(CSR_MATTRI0_BASE, base); break;
        case 1: __RV_CSR_WRITE(CSR_MATTRI1_MASK, mask); __RV_CSR_WRITE(CSR_MATTRI1_BASE, base); break;
        case 2: __RV_CSR_WRITE(CSR_MATTRI2_MASK, mask); __RV_CSR_WRITE(CSR_MATTRI2_BASE, base); break;
        case 3: __RV_CSR_WRITE(CSR_MATTRI3_MASK, mask); __RV_CSR_WRITE(CSR_MATTRI3_BASE, base); break;
        case 4: __RV_CSR_WRITE(CSR_MATTRI4_MASK, mask); __RV_CSR_WRITE(CSR_MATTRI4_BASE, base); break;
        case 5: __RV_CSR_WRITE(CSR_MATTRI5_MASK, mask); __RV_CSR_WRITE(CSR_MATTRI5_BASE, base); break;
        case 6: __RV_CSR_WRITE(CSR_MATTRI6_MASK, mask); __RV_CSR_WRITE(CSR_MATTRI6_BASE, base); break;
        case 7: __RV_CSR_WRITE(CSR_MATTRI7_MASK, mask); __RV_CSR_WRITE(CSR_MATTRI7_BASE, base); break;
        default: return -1;
    }
 
    return 0;
}

References __RV_CSR_WRITE, CSR_MATTRI0_BASE, CSR_MATTRI0_MASK, CSR_MATTRI1_BASE, CSR_MATTRI1_MASK, CSR_MATTRI2_BASE, CSR_MATTRI2_MASK, CSR_MATTRI3_BASE, CSR_MATTRI3_MASK, CSR_MATTRI4_BASE, CSR_MATTRI4_MASK, CSR_MATTRI5_BASE, CSR_MATTRI5_MASK, CSR_MATTRI6_BASE, CSR_MATTRI6_MASK, CSR_MATTRI7_BASE, CSR_MATTRI7_MASK, pma_config::region_base, pma_config::region_enable, pma_config::region_size, and pma_config::region_type.

PMA_SetRegion_S()

__STATIC_INLINE long PMA_SetRegion_S	(	unsigned long	entry_idx,
		pma_config *	pma_cfg
	)

Configure one region for Secure S-Mode world to share with Non-Secure S-Mode world.

Set the region(0-7) info of base address/region size/enable status

Parameters

[in]	entry_idx	Index(0-7) of paired sattri(n)_mask and sattri(n)_base
[in]	pma_cfg	Region info to configure

Returns

0 if success, else -1

Remarks

• sattri(n)_mask must be written first, before sattri(n)_base, which the api takes care of
• The higher bits of sattri(n)_mask should be continuously 1, the remaining lower bits should be all 0 and the number (N) of 0 means the size of this region(2^N bytes)
• Region granularity is 4KB, so the low 12-bits of sattri(n)_mask must be 0, which the api takes care of
• Unlike mattri(n)_base, there's no DEV Region/NC Region/CA Region type

Definition at line 181 of file core_feature_pma.h.

{
    // 4KB aligned
    unsigned long size = (pma_cfg->region_size >> 12) << 12;
    unsigned long base_addr = (pma_cfg->region_base >> 12) << 12;
 
    if ((entry_idx + 1) > __PMA_SEC_CSR_NUM) {
        return -1;
    }
 
    rv_csr_t mask = (unsigned long)(~(size - 1));
    rv_csr_t base = base_addr | pma_cfg->region_enable;
 
    switch (entry_idx) {
        // Bit[MXLEN-1:PA_SIZE] of sattri(n)_mask is reserved 0
        case 0: __RV_CSR_WRITE(CSR_SATTRI0_MASK, mask); __RV_CSR_WRITE(CSR_SATTRI0_BASE, base); break;
        case 1: __RV_CSR_WRITE(CSR_SATTRI1_MASK, mask); __RV_CSR_WRITE(CSR_SATTRI1_BASE, base); break;
        case 2: __RV_CSR_WRITE(CSR_SATTRI2_MASK, mask); __RV_CSR_WRITE(CSR_SATTRI2_BASE, base); break;
        case 3: __RV_CSR_WRITE(CSR_SATTRI3_MASK, mask); __RV_CSR_WRITE(CSR_SATTRI3_BASE, base); break;
        case 4: __RV_CSR_WRITE(CSR_SATTRI4_MASK, mask); __RV_CSR_WRITE(CSR_SATTRI4_BASE, base); break;
        case 5: __RV_CSR_WRITE(CSR_SATTRI5_MASK, mask); __RV_CSR_WRITE(CSR_SATTRI5_BASE, base); break;
        case 6: __RV_CSR_WRITE(CSR_SATTRI6_MASK, mask); __RV_CSR_WRITE(CSR_SATTRI6_BASE, base); break;
        case 7: __RV_CSR_WRITE(CSR_SATTRI7_MASK, mask); __RV_CSR_WRITE(CSR_SATTRI7_BASE, base); break;
        default: return -1;
    }
 
    return 0;
}

References __RV_CSR_WRITE, CSR_SATTRI0_BASE, CSR_SATTRI0_MASK, CSR_SATTRI1_BASE, CSR_SATTRI1_MASK, CSR_SATTRI2_BASE, CSR_SATTRI2_MASK, CSR_SATTRI3_BASE, CSR_SATTRI3_MASK, CSR_SATTRI4_BASE, CSR_SATTRI4_MASK, CSR_SATTRI5_BASE, CSR_SATTRI5_MASK, CSR_SATTRI6_BASE, CSR_SATTRI6_MASK, CSR_SATTRI7_BASE, CSR_SATTRI7_MASK, pma_config::region_base, pma_config::region_enable, and pma_config::region_size.