18 #ifndef __CORE_FEATURE_PMP_H__
19 #define __CORE_FEATURE_PMP_H__
35 #include "core_feature_base.h"
36 #include "core_compatiable.h"
38 #if defined(__PMP_PRESENT) && (__PMP_PRESENT == 1)
53 #ifndef __PMP_ENTRY_NUM
55 #error "__PMP_ENTRY_NUM is not defined, please check!"
58 typedef struct PMP_CONFIG {
132 uint8_t csr_cfg_num = 0;
133 uint16_t csr_idx = 0;
134 uint16_t cfg_shift = 0;
136 if (entry_idx >= __PMP_ENTRY_NUM)
return 0;
138 #if __RISCV_XLEN == 32
140 csr_idx = entry_idx >> 2;
141 #elif __RISCV_XLEN == 64
144 csr_idx = (entry_idx >> 2) & ~1;
154 cfg_shift = (entry_idx & (csr_cfg_num - 1)) << 3;
157 return (uint8_t)(__RV_EXTRACT_FIELD(pmpcfgx, 0xFF << cfg_shift));
172 uint8_t csr_cfg_num = 0;
173 uint16_t csr_idx = 0;
174 uint16_t cfg_shift = 0;
175 if (entry_idx >= __PMP_ENTRY_NUM)
return;
177 #if __RISCV_XLEN == 32
179 csr_idx = entry_idx >> 2;
180 #elif __RISCV_XLEN == 64
183 csr_idx = (entry_idx >> 2) & ~1;
194 cfg_shift = (entry_idx & (csr_cfg_num - 1)) << 3;
196 pmpcfgx = __RV_INSERT_FIELD(pmpcfgx, 0xFFUL << cfg_shift, pmpxcfg);
271 unsigned int cfg_shift, cfg_csr_idx, addr_csr_idx = 0;
272 unsigned long cfgmask, addrmask = 0;
273 unsigned long pmpcfg, pmpaddr = 0;
274 unsigned long protection, csr_cfg_num = 0;
279 #if __RISCV_XLEN == 32
281 cfg_csr_idx = (entry_idx >> 2);
282 #elif __RISCV_XLEN == 64
284 cfg_csr_idx = ((entry_idx >> 2)) & ~1;
293 cfg_shift = (entry_idx & (csr_cfg_num - 1)) << 3;
294 addr_csr_idx = entry_idx;
297 protection = (
unsigned long)pmp_cfg->
protection;
299 cfgmask = ~(0xFFUL << cfg_shift);
301 pmpcfg |= ((protection << cfg_shift) & ~cfgmask);
309 pmpaddr |= (addrmask >> 1);
332 unsigned int cfg_shift, cfg_csr_idx, addr_csr_idx = 0;
333 unsigned long cfgmask, pmpcfg, prot = 0;
334 unsigned long t1, addr, pmpaddr, len = 0;
335 uint8_t csr_cfg_num = 0;
337 if (entry_idx >= __PMP_ENTRY_NUM || !pmp_cfg)
return -1;
340 #if __RISCV_XLEN == 32
342 cfg_csr_idx = entry_idx >> 2;
343 #elif __RISCV_XLEN == 64
345 cfg_csr_idx = (entry_idx>> 2) & ~1;
351 cfg_shift = (entry_idx & (csr_cfg_num - 1)) << 3;
352 addr_csr_idx = entry_idx;
355 cfgmask = (0xFFUL << cfg_shift);
357 prot = pmpcfg >> cfg_shift;
362 t1 =
__CTZ(~pmpaddr);
363 addr = (pmpaddr & ~((1UL << t1) - 1)) <<
PMP_SHIFT;
373 pmp_cfg->
order = len;
__STATIC_FORCEINLINE unsigned long __CTZ(unsigned long data)
Count tailing zero.
#define __RV_CSR_READ(csr)
CSR operation Macro for csrr instruction.
#define __RV_CSR_WRITE(csr, val)
CSR operation Macro for csrw instruction.
#define __STATIC_INLINE
Define a static function that may be inlined by the compiler.
__STATIC_INLINE void __set_PMPCFGx(uint32_t csr_idx, rv_csr_t pmpcfg)
Set PMPCFGx by csr index.
__STATIC_INLINE void __set_PMPxCFG(uint32_t entry_idx, uint8_t pmpxcfg)
Set 8bit PMPxCFG by pmp entry index.
__STATIC_INLINE rv_csr_t __get_PMPCFGx(uint32_t csr_idx)
Get PMPCFGx Register by csr index.
__STATIC_INLINE rv_csr_t __get_PMPADDRx(uint32_t csr_idx)
Get PMPADDRx Register by CSR index.
__STATIC_INLINE void __set_PMPADDRx(uint32_t csr_idx, rv_csr_t pmpaddr)
Set PMPADDRx by CSR index.
__STATIC_INLINE int __get_PMPENTRYx(unsigned int entry_idx, pmp_config *pmp_cfg)
Get PMP entry by entry idx.
__STATIC_INLINE uint8_t __get_PMPxCFG(uint32_t entry_idx)
Get 8bit PMPxCFG Register by PMP entry index.
__STATIC_INLINE void __set_PMPENTRYx(uint32_t entry_idx, const pmp_config *pmp_cfg)
Set PMP entry by entry idx.
unsigned long rv_csr_t
Type of Control and Status Register(CSR), depends on the XLEN defined in RISC-V.
#define __RISCV_XLEN
Refer to the width of an integer register in bits(either 32 or 64)
unsigned long order
Size of memory region as power of 2, it has to be minimum 2 and maxium __RISCV_XLEN according to the ...
unsigned long base_addr
Base address of memory region It must be 2^order aligned address.
unsigned int protection
set locking bit, addressing mode, read, write, and instruction execution permissions,...