core_feature_smpcc.h

/*
 * Copyright (c) 2019 Nuclei Limited. All rights reserved.
 *
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
#ifndef __CORE_FEATURE_SMPCC_H__
#define __CORE_FEATURE_SMPCC_H__
 
/*
 * SMP & Cluster Cache Feature Configuration Macro:
 *
 * 1. __SMPCC_PRESENT:  Define whether SMP & Cluster Cache feature is present or not
 *   * 0: Not present
 *   * 1: Present
 * 2. __CCM_PRESENT:  Define whether Nuclei Cache Control and Maintainence(CCM) Unit is present or not.
 *   * 0: Not present
 *   * 1: Present
 * 3. __SMPCC_BASEADDR:  Base address of the SMP & Cluster Cache unit.
 *
 */
#ifdef __cplusplus
 extern "C" {
#endif
 
#include "core_feature_base.h"
#include "core_feature_iinfo.h"
 
#if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1)
 
typedef union
{
    struct {
        __IM uint32_t mic_ver:8;                
        __IM uint32_t min_ver:8;                
        __IM uint32_t maj_ver:8;                
        __IM uint32_t _reserved:8;              
    } b;                                        
    __IM uint32_t w;                            
} SMP_VER_Type;
 
typedef union
{
    struct {
        __IM uint32_t cc_present:1;             
        __IM uint32_t smp_core_num:6;           
        __IM uint32_t iocp_num:6;               
        __IM uint32_t pmon_num:6;               
        __IM uint32_t _reserved:13;             
    } b;                                        
    __IM uint32_t w;                            
} SMP_CFG_Type;
 
typedef union
{
    struct {
        __IM uint32_t cc_set:4;                 
        __IM uint32_t cc_way:4;                 
        __IM uint32_t cc_lsize:3;               
        __IM uint32_t cc_ecc:1;                 
        __IM uint32_t cc_tcycle:3;              
        __IM uint32_t cc_dcycle:3;              
        __IM uint32_t _reserved:14;             
    } b;                                        
    uint32_t w;                                 
} CC_CFG_Type;
 
typedef union
{
    struct {
        __IOM uint32_t smp_enable:16;           
        __IM uint32_t _reserved:16;             
    } b;                                        
    uint32_t w;                                 
} SMP_ENB_Type;
 
typedef union
{
    struct {
        __IOM uint32_t cc_en:1;                 
        __IOM uint32_t cc_ecc_en:1;             
        __IOM uint32_t ecc_excp_en:1;           
        __IOM uint32_t lock_ecc_cfg:1;          
        __IOM uint32_t lock_ecc_err_inj:1;      
        __IOM uint32_t recv_err_irq_en:1;       
        __IOM uint32_t fatal_err_irq_en:1;      
        __IOM uint32_t bus_err_pend:1;          
        __IOM uint32_t bus_err_irq_en:1;        
        __IOM uint32_t sup_cmd_en:1;            
        __IOM uint32_t use_cmd_en:1;            
        __IOM uint32_t ecc_chk_en:1;            
        __IOM uint32_t clm_ecc_en:1;            
        __IOM uint32_t clm_excp_en:1;           
        __IOM uint32_t clm_ecc_chk_en:1;        
        __IOM uint32_t pf_sh_cl_en:1;           
        __IOM uint32_t pf_l2_early_en:1;        
        __IOM uint32_t pf_biu_outs_en:1;        
        __IOM uint32_t i_snoop_d_en:1;          
        __IOM uint32_t iocc_err:1;              
        __IOM uint32_t early_wr_err:1;          
        __IOM uint32_t pf_no_wb:1;              
        __IM uint32_t _reserved:10;             
    } b;                                        
    uint32_t w;                                 
} CC_CTRL_Type;
 
#define SMPCC_CTRL_CC_EN_Pos                 0U                                          
#define SMPCC_CTRL_CC_EN_Msk                 (0x1UL << SMPCC_CTRL_CC_EN_Pos)             
#define SMPCC_CTRL_CC_EN_ENABLE              1U                                          
#define SMPCC_CTRL_CC_EN_DISABLE             0U                                          
#define SMPCC_CTRL_CC_ECC_EN_Pos             1U                                          
#define SMPCC_CTRL_CC_ECC_EN_Msk             (0x1UL << SMPCC_CTRL_CC_ECC_EN_Pos)         
#define SMPCC_CTRL_CC_ECC_EN_ENABLE          1U                                          
#define SMPCC_CTRL_CC_ECC_EN_DISABLE         0U                                          
#define SMPCC_CTRL_CC_ECC_EXCP_EN_Pos        2U                                          
#define SMPCC_CTRL_CC_ECC_EXCP_EN_Msk        (0x1UL << SMPCC_CTRL_CC_ECC_EXCP_EN_Pos)    
#define SMPCC_CTRL_CC_ECC_EXCP_EN_ENABLE     1U                                          
#define SMPCC_CTRL_CC_ECC_EXCP_EN_DISABLE    0U                                          
#define SMPCC_CTRL_LOCK_ECC_CFG_Pos          3U                                          
#define SMPCC_CTRL_LOCK_ECC_CFG_Msk          (0x1UL << SMPCC_CTRL_LOCK_ECC_CFG_Pos)      
#define SMPCC_CTRL_LOCK_ECC_CFG_LOCK         1U                                          
#define SMPCC_CTRL_LOCK_ECC_ERR_INJ_Pos      4U                                          
#define SMPCC_CTRL_LOCK_ECC_ERR_INJ_Msk      (0x1UL << SMPCC_CTRL_LOCK_ECC_ERR_INJ_Pos)  
#define SMPCC_CTRL_LOCK_ECC_ERR_INJ_LOCK     1U                                          
#define SMPCC_CTRL_RECV_ERR_IRQ_EN_Pos       5U                                          
#define SMPCC_CTRL_RECV_ERR_IRQ_EN_Msk       (0x1UL << SMPCC_CTRL_RECV_ERR_IRQ_EN_Pos)   
#define SMPCC_CTRL_RECV_ERR_IRQ_EN_ENABLE    1U                                          
#define SMPCC_CTRL_RECV_ERR_IRQ_EN_DISABLE   0U                                          
#define SMPCC_CTRL_FATAL_ERR_IRQ_EN_Pos      6U                                          
#define SMPCC_CTRL_FATAL_ERR_IRQ_EN_Msk      (0x1UL << SMPCC_CTRL_FATAL_ERR_IRQ_EN_Pos)  
#define SMPCC_CTRL_FATAL_ERR_IRQ_EN_ENABLE   1U                                          
#define SMPCC_CTRL_FATAL_ERR_IRQ_EN_DISABLE  0U                                          
#define SMPCC_CTRL_BUS_ERR_PEND_Pos          7U                                          
#define SMPCC_CTRL_BUS_ERR_PEND_Msk          (0x1UL << SMPCC_CTRL_BUS_ERR_PEND_Pos)      
#define SMPCC_CTRL_BUS_ERR_IRQ_EN_Pos        8U                                          
#define SMPCC_CTRL_BUS_ERR_IRQ_EN_Msk        (0x1UL << SMPCC_CTRL_BUS_ERR_IRQ_EN_Pos)    
#define SMPCC_CTRL_BUS_ERR_IRQ_EN_ENABLE     1U                                          
#define SMPCC_CTRL_BUS_ERR_IRQ_EN_DISABLE    0U                                          
#define SMPCC_CTRL_SUP_CMD_EN_Pos            9U                                          
#define SMPCC_CTRL_SUP_CMD_EN_Msk            (0x1UL << SMPCC_CTRL_SUP_CMD_EN_Pos)        
#define SMPCC_CTRL_SUP_CMD_EN_ENABLE         1U                                          
#define SMPCC_CTRL_SUP_CMD_EN_DISABLE        0U                                          
#define SMPCC_CTRL_USE_CMD_EN_Pos            10U                                         
#define SMPCC_CTRL_USE_CMD_EN_Msk            (0x1UL << SMPCC_CTRL_USE_CMD_EN_Pos)        
#define SMPCC_CTRL_USE_CMD_EN_ENABLE         1U                                          
#define SMPCC_CTRL_USE_CMD_EN_DISABLE        0U                                          
#define SMPCC_CTRL_ECC_CHK_EN_Pos            11U                                         
#define SMPCC_CTRL_ECC_CHK_EN_Msk            (0x1UL << SMPCC_CTRL_ECC_CHK_EN_Pos)        
#define SMPCC_CTRL_ECC_CHK_EN_ENABLE         1U                                          
#define SMPCC_CTRL_ECC_CHK_EN_DISABLE        0U                                          
#define SMPCC_CTRL_CLM_ECC_EN_Pos            12U                                         
#define SMPCC_CTRL_CLM_ECC_EN_Msk            (0x1UL << SMPCC_CTRL_CLM_ECC_EN_Pos)        
#define SMPCC_CTRL_CLM_ECC_EN_ENABLE         1U                                          
#define SMPCC_CTRL_CLM_ECC_EN_DISABLE        0U                                          
#define SMPCC_CTRL_CLM_EXCP_EN_Pos          13U                                         
#define SMPCC_CTRL_CLM_EXCP_EN_Msk          (0x1UL << SMPCC_CTRL_CLM_EXCP_EN_Pos)      
#define SMPCC_CTRL_CLM_EXCP_EN_ENABLE       1U                                          
#define SMPCC_CTRL_CLM_EXCP_EN_DISABLE      0U                                          
#define SMPCC_CTRL_CLM_ECC_CHK_EN_Pos        14U                                         
#define SMPCC_CTRL_CLM_ECC_CHK_EN_Msk        (0x1UL << SMPCC_CTRL_CLM_ECC_CHK_EN_Pos)    
#define SMPCC_CTRL_CLM_ECC_CHK_EN_ENABLE     1U                                          
#define SMPCC_CTRL_CLM_ECC_CHK_EN_DISABLE    0U                                          
#define SMPCC_CTRL_PF_SH_CL_EN_Pos           15U                                         
#define SMPCC_CTRL_PF_SH_CL_EN_Msk           (0x1UL << SMPCC_CTRL_PF_SH_CL_EN_Pos)       
#define SMPCC_CTRL_PF_SH_CL_EN_ENABLE        1U                                          
#define SMPCC_CTRL_PF_SH_CL_EN_DISABLE       0U                                          
#define SMPCC_CTRL_PF_L2_EARLY_EN_Pos        16U                                         
#define SMPCC_CTRL_PF_L2_EARLY_EN_Msk        (0x1UL << SMPCC_CTRL_PF_L2_EARLY_EN_Pos)    
#define SMPCC_CTRL_PF_L2_EARLY_EN_ENABLE     1U                                          
#define SMPCC_CTRL_PF_L2_EARLY_EN_DISABLE    0U                                          
#define SMPCC_CTRL_PF_BIU_OUTS_EN_Pos        17U                                         
#define SMPCC_CTRL_PF_BIU_OUTS_EN_Msk        (0x1UL << SMPCC_CTRL_PF_BIU_OUTS_EN_Pos)    
#define SMPCC_CTRL_PF_BIU_OUTS_EN_ENABLE     1U                                          
#define SMPCC_CTRL_PF_BIU_OUTS_EN_DISABLE    0U                                          
#define SMPCC_CTRL_I_SNOOP_D_EN_Pos          18U                                         
#define SMPCC_CTRL_I_SNOOP_D_EN_Msk          (0x1UL << SMPCC_CTRL_I_SNOOP_D_EN_Pos)      
#define SMPCC_CTRL_I_SNOOP_D_EN_ENABLE       1U                                          
#define SMPCC_CTRL_I_SNOOP_D_EN_DISABLE      0U                                          
#define SMPCC_CTRL_IOCC_ERR_Pos              19U                                         
#define SMPCC_CTRL_IOCC_ERR_Msk              (0x1UL << SMPCC_CTRL_IOCC_ERR_Pos)          
#define SMPCC_CTRL_EARLY_WR_ERR_Pos          20U                                         
#define SMPCC_CTRL_EARLY_WR_ERR_Msk          (0x1UL << SMPCC_CTRL_EARLY_WR_ERR_Pos)      
#define SMPCC_CTRL_PF_NO_WB_Pos              21U                                         
#define SMPCC_CTRL_PF_NO_WB_Msk              (0x1UL << SMPCC_CTRL_PF_NO_WB_Pos)          
#define SMPCC_CTRL_PF_NO_WB_ENABLE           1U                                          
#define SMPCC_CTRL_PF_NO_WB_DISABLE          0U                                          
typedef union
{
    struct {
        __IOM uint32_t cmd:5;                   
        __IM uint32_t _reserved:18;             
        __IOM uint32_t reisc:1;                 
        __IOM uint32_t feisc:1;                 
        __IOM uint32_t besc:1;                  
        __IM uint32_t result_code:5;            
        __IM uint32_t complete:1;               
    } b;                                        
    uint32_t w;                                 
} CC_CMD_Type;
 
typedef union
{
    struct {
        __IOM uint32_t inj_data:1;              
        __IOM uint32_t inj_tag:1;               
        __IOM uint32_t inj_clm:1;               
        __IOM uint32_t inj_mode:1;              
        __IOM uint32_t cs:1;                    
        __IM uint32_t _reserved0:19;            
        __IM uint32_t inj_ecc_code:8;
    } b;                                        
    uint32_t w;                                 
} CC_ERR_INJ_Type;
 
#define SMPCC_ERR_INJ_INJDATA_Pos             0U                                          
#define SMPCC_ERR_INJ_INJDATA_Msk             (0x1UL << SMPCC_ERR_INJ_INJDATA_Pos)        
#define SMPCC_ERR_INJ_INJDATA_ENABLE          1U                                          
#define SMPCC_ERR_INJ_INJDATA_DISABLE         0U                                          
#define SMPCC_ERR_INJ_INJTAG_Pos              1U                                          
#define SMPCC_ERR_INJ_INJTAG_Msk              (0x1UL << SMPCC_ERR_INJ_INJTAG_Pos)         
#define SMPCC_ERR_INJ_INJTAG_ENABLE           1U                                          
#define SMPCC_ERR_INJ_INJTAG_DISABLE          0U                                          
#define SMPCC_ERR_INJ_INJCLM_Pos              2U                                          
#define SMPCC_ERR_INJ_INJCLM_Msk              (0x1UL << SMPCC_ERR_INJ_INJCLM_Pos)         
#define SMPCC_ERR_INJ_INJCLM_ENABLE           1U                                          
#define SMPCC_ERR_INJ_INJCLM_DISABLE          0U                                          
#define SMPCC_ERR_INJ_INJMODE_Pos             3U                                          
#define SMPCC_ERR_INJ_INJMODE_Msk             (0x1UL << SMPCC_ERR_INJ_INJMODE_Pos)        
#define SMPCC_ERR_INJ_INJMODE_DIRECT          0U                                          
#define SMPCC_ERR_INJ_INJMODE_XOR             1U                                          
#define SMPCC_ERR_INJ_CS_Pos                  4U                                          
#define SMPCC_ERR_INJ_CS_Msk                  (0x1UL << SMPCC_ERR_INJ_CS_Pos)             
#define SMPCC_ERR_INJ_CS_START                1U                                          
#define SMPCC_ERR_INJ_INJECCCODE_Pos          24U                                         
#define SMPCC_ERR_INJ_INJECCCODE_Msk          (0xFFUL << SMPCC_ERR_INJ_INJECCCODE_Pos)    
typedef union
{
    struct {
        __IOM uint32_t cnt:16;                  
        __IM uint32_t _reserved:16;             
    } b;                                        
    uint32_t w;                                 
} CC_RECV_CNT_Type;
 
typedef union
{
    struct {
        __IOM uint32_t cnt:16;                  
        __IM uint32_t _reserved:16;             
    } b;                                        
    uint32_t w;                                 
} CC_FATAL_CNT_Type;
 
typedef union
{
    struct {
        __IOM uint32_t cnt:16;                  
        __IM uint32_t _reserved:16;             
    } b;                                        
    uint32_t w;                                 
} CC_RECV_THV_Type;
 
typedef union
{
    struct {
        __IOM uint32_t cnt:16;                  
        __IM uint32_t _reserved:16;             
    } b;                                        
    uint32_t w;                                 
} CC_FATAL_THV_Type;
 
typedef __IO uint64_t CC_BUS_ERR_ADDR_Type;
 
typedef union
{
    struct {
        __IOM uint32_t read_bus_err:1;          
        __IOM uint32_t write_bus_err:1;         
        __IOM uint32_t cc_scu_ecc_err:1;        
        __IOM uint32_t iocp_bus_err:1;          
        __IM uint32_t _reserved:28;             
    } b;                                        
    uint32_t w;                                 
} CLIENT_ERR_STATUS_Type;
 
#define SMPCC_CLIERRSTS_READ_BUS_ERR_Pos      0U                                            
#define SMPCC_CLIERRSTS_READ_BUS_ERR_Msk      (0x1UL << SMPCC_CLIERRSTS_READ_BUS_ERR_Pos)   
#define SMPCC_CLIERRSTS_WRITE_BUS_ERR_Pos     1U                                            
#define SMPCC_CLIERRSTS_WRITE_BUS_ERR_Msk     (0x1UL << SMPCC_CLIERRSTS_WRITE_BUS_ERR_Pos)  
#define SMPCC_CLIERRSTS_CC_SCU_ECC_ERR_Pos    2U                                            
#define SMPCC_CLIERRSTS_CC_SCU_ECC_ERR_Msk    (0x1UL << SMPCC_CLIERRSTS_CC_SCU_ECC_ERR_Pos) 
#define SMPCC_CLIERRSTS_IOCP_BUS_ERR_Pos      3U                                            
#define SMPCC_CLIERRSTS_IOCP_BUS_ERR_Msk      (0x1UL << SMPCC_CLIERRSTS_IOCP_BUS_ERR_Pos)   
typedef union
{
    struct {
        __IM uint32_t snoop_pending:16;         
        __IM uint32_t _reserved:16;             
    } b;                                        
    __IM uint32_t w;                            
} SNOOP_PENDING_Type;
 
typedef union
{
    struct {
        __IM uint32_t trans_pending:16;         
        __IM uint32_t _reserved:15;             
        __IM uint32_t ext_trans:1;              
    } b;                                        
    __IM uint32_t w;                            
} TRANS_PENDING_Type;
 
typedef union
{
    struct {
        __IOM uint32_t clm_base32;
        __IM uint32_t _reserved;
    } clm32;             
    uint64_t clm_base64; 
} CLM_ADDR_BASE_Type;
 
typedef union
{
    struct {
        __IOM uint32_t ena:16;                  
        __IM uint32_t _reserved:16;             
    } b;                                        
    uint32_t w;                                 
} CLM_WAY_EN_Type;
 
typedef union
{
    struct {
        __IOM uint32_t cs:1;                    
        __IM uint32_t _reserved:31;             
    } b;                                        
    uint32_t w;                                 
} CC_INVALID_ALL_Type;
 
typedef union
{
    struct {
        __IOM uint32_t rd_stm_en:1;             
        __IOM uint32_t wr_stm_en:1;             
        __IOM uint32_t trans_alloc:1;           
        __IOM uint32_t rd_merge_en:1;           
        __IOM uint32_t cross_en:1;              
        __IM uint32_t _reserved:27;             
    } b;                                        
    uint32_t w;                                 
} STM_CTRL_Type;
 
#define SMPCC_STMCTRL_RD_STM_EN_Pos        0U                                           
#define SMPCC_STMCTRL_RD_STM_EN_Msk        (0x1UL << SMPCC_STMCTRL_RD_STM_EN_Pos)       
#define SMPCC_STMCTRL_RD_STM_EN_ENABLE     1U                                           
#define SMPCC_STMCTRL_RD_STM_EN_DISABLE    0U                                           
#define SMPCC_STMCTRL_WR_STM_EN_Pos        1U                                           
#define SMPCC_STMCTRL_WR_STM_EN_Msk        (0x1UL << SMPCC_STMCTRL_WR_STM_EN_Pos)       
#define SMPCC_STMCTRL_WR_STM_EN_ENABLE     1U                                           
#define SMPCC_STMCTRL_WR_STM_EN_DISABLE    0U                                           
#define SMPCC_STMCTRL_TRANS_ALLOC_Pos      2U                                           
#define SMPCC_STMCTRL_TRANS_ALLOC_Msk      (0x1UL << SMPCC_STMCTRL_TRANS_ALLOC_Pos)     
#define SMPCC_STMCTRL_TRANS_ALLOC_ENABLE   1U                                           
#define SMPCC_STMCTRL_TRANS_ALLOC_DISABLE  0U                                           
#define SMPCC_STMCTRL_RD_MERGE_EN_Pos      3U                                           
#define SMPCC_STMCTRL_RD_MERGE_EN_Msk      (0x1UL << SMPCC_STMCTRL_RD_MERGE_EN_Pos)     
#define SMPCC_STMCTRL_RD_MERGE_EN_ENABLE   1U                                           
#define SMPCC_STMCTRL_RD_MERGE_EN_DISABLE  0U                                           
#define SMPCC_STMCTRL_CROSS_EN_Pos         4U                                           
#define SMPCC_STMCTRL_CROSS_EN_Msk         (0x1UL << SMPCC_STMCTRL_CROSS_EN_Pos)        
#define SMPCC_STMCTRL_CROSS_EN_ENABLE      1U                                           
#define SMPCC_STMCTRL_CROSS_EN_DISABLE     0U                                           
typedef union
{
    struct {
        __IOM uint32_t rd_byte_threshold:10;    
        __IM uint32_t _reserved0:2;             
        __IOM uint32_t rd_degree:3;             
        __IM uint32_t _reserved1:1;             
        __IOM uint32_t rd_distance:3;           
        __IM uint32_t _reserved2:1;             
        __IOM uint32_t wr_byte_threshold:10;    
        __IM uint32_t _reserved3:2;             
    } b;                                        
    uint32_t w;                                 
} STM_CFG_Type;
 
#define SMPCC_STMCFG_RD_BYTE_THRE_Pos     0U                                            
#define SMPCC_STMCFG_RD_BYTE_THRE_Msk     (0x3FFUL << SMPCC_STMCFG_RD_BYTE_THRE_Pos)    
#define SMPCC_STMCFG_RD_DEGREE_Pos        12U                                           
#define SMPCC_STMCFG_RD_DEGREE_Msk        (0x7UL << SMPCC_STMCFG_RD_DEGREE_Pos)         
#define SMPCC_STMCFG_RD_DISTANCE_Pos      16U                                           
#define SMPCC_STMCFG_RD_DISTANCE_Msk      (0x7UL << SMPCC_STMCFG_RD_DISTANCE_Pos)       
#define SMPCC_STMCFG_WR_BYTE_THRE_Pos     20U                                           
#define SMPCC_STMCFG_WR_BYTE_THRE_Msk     (0x7FFUL << SMPCC_STMCFG_WR_BYTE_THRE_Pos)    
typedef union
{
    struct {
        __IOM uint32_t timeout:11;              
        __IM uint32_t _reserved:21;             
    } b;                                        
    uint32_t w;                                 
} STM_TIMEOUT_Type;
 
typedef union
{
    struct {
        __IOM uint32_t chk_en:2;                
        __IM uint32_t _reserved:30;             
    } b;                                        
    uint32_t w;                                 
} DFF_PROT_Type;
 
#define SMPCC_DFF_PROT_CHK_EN_Pos      0U                                      
#define SMPCC_DFF_PROT_CHK_EN_Msk      (0x3UL << SMPCC_DFF_PROT_CHK_EN_Pos)    
#define SMPCC_DFF_PROT_CHK_EN_ENABLE   2U                                      
#define SMPCC_DFF_PROT_CHK_EN_DISABLE  1U                                      
typedef union
{
    struct {
        __IOM uint32_t cc_l2_err_msk:1;         
        __IOM uint32_t cc_core_err_mask:1;      
        __IM uint32_t _reserved:29;             
    } b;                                        
    uint32_t w;                                 
} ECC_ERR_MSK_Type;
 
typedef union
{
    struct {
        __IOM uint64_t cfg:2;                   
        __IOM uint64_t addr_hi:62;              
    } b;                                        
    __IOM uint64_t dw;                          
} NS_RG_Type;
 
#define SMPCC_NS_RG_CFG_Pos            0U                                       
#define SMPCC_NS_RG_CFG_Msk            (0x3UL << SMPCC_NS_RG_CFG_Pos)           
#define SMPCC_NS_RG_CFG_DISABLE        0x00U                                    
#define SMPCC_NS_RG_CFG_NACL           0x10U                                    
#define SMPCC_NS_RG_CFG_NAPOT          0x11U                                    
typedef union
{
    struct {
        __IOM uint32_t event_sel:16;            
        __IOM uint32_t client_sel:5;            
        __IM uint32_t _reserved:11;             
    } b;                                        
    uint32_t w;                                 
} SMP_PMON_SEL_Type;
 
#define SMPCC_PMON_EVENT_SEL_Pos                    0U                                       
#define SMPCC_PMON_EVENT_SEL_Msk                    (0xFFFFUL << SMPCC_PMON_EVENT_SEL_Pos)   
#define SMPCC_PMON_EVENT_DISABLE                    0U                                       
#define SMPCC_PMON_EVENT_DATA_READ_COUNT            1U                                       
#define SMPCC_PMON_EVENT_DATA_WRITE_COUNT           2U                                       
#define SMPCC_PMON_EVENT_INSTR_READ_COUNT           3U                                       
#define SMPCC_PMON_EVENT_DATA_READ_HIT_COUNT        4U                                       
#define SMPCC_PMON_EVENT_DATA_WRITE_REPLACE_COUNT   5U                                       
#define SMPCC_PMON_EVENT_DATA_READ_REPLACE_COUNT    6U                                       
#define SMPCC_PMON_EVENT_DATA_READ_MISS_COUNT       7U                                       
#define SMPCC_PMON_EVENT_INSTR_READ_HIT_COUNT       8U                                       
#define SMPCC_PMON_EVENT_INSTR_READ_MISS_COUNT      9U                                       
#define SMPCC_PMON_EVENT_INSTR_READ_REPLACE_COUNT   10U                                      
#define SMPCC_PMON_CLIENT_SEL_Pos                   16U                                      
#define SMPCC_PMON_CLIENT_SEL_Msk                   (0x1FUL << SMPCC_PMON_CLIENT_SEL_Pos)    
#define SMPCC_PMON_EVENT(event, client)                                        \
    (_VAL2FLD(SMPCC_PMON_EVENT_SEL, event) |                                   \
     _VAL2FLD(SMPCC_PMON_CLIENT_SEL, client))
 
typedef __IO uint64_t SMP_PMON_CNT_Type;
 
typedef __IO uint64_t CLIENT_ERR_ADDR_Type;
 
typedef union
{
    struct {
        __IOM uint32_t mask:16;                 
        __IM uint32_t _reserved:16;             
    } b;                                        
    uint32_t w;                                 
} CLIENT_WAY_MASK_Type;
 
typedef union
{
    struct {
        __IOM uint32_t cs:1;                    
        __IM uint32_t _reserved:31;             
    } b;                                        
    uint32_t w;                                 
} CC_INV_RANGE_Type;
 
typedef __IO uint64_t CC_INV_RANGE_START_Type;
 
typedef __IO uint64_t CC_INV_RANGE_END_Type;
 
typedef union
{
    struct {
        __IOM uint32_t num:16;                  
        __IM uint32_t _reserved:16;             
    } b;                                        
    uint32_t w;                                 
} CC_ECC_INJ_WAY_Type;
 
typedef __IO uint64_t CC_ECC_INJ_ADDR_Type;
 
typedef __IO uint32_t CC_ECC_INJ_DATA_Type;
 
typedef union
{
    struct {
        __IOM uint32_t wr_rmp_en:1;             
        __IOM uint32_t wr_attri:1;              
        __IOM uint32_t rd_rmp_en:1;             
        __IOM uint32_t rd_attri:1;              
        __IM uint32_t _reserved:28;             
    } b;                                        
    uint32_t w;                                 
} IOCP_ATTR_RMP_Type;
 
#pragma pack(4)
typedef struct {
    const SMP_VER_Type SMP_VER;                         
    __IM SMP_CFG_Type SMP_CFG;                          
    __IM CC_CFG_Type CC_CFG;                            
    __IOM SMP_ENB_Type SMP_ENB;                         
    __IOM CC_CTRL_Type CC_CTRL;                         
    __IOM CC_CMD_Type CC_mCMD;                          
    __IOM CC_ERR_INJ_Type CC_ERR_INJ;                   
    __IOM CC_RECV_CNT_Type CC_RECV_CNT;                 
    __IOM CC_FATAL_CNT_Type CC_FATAL_CNT;               
    __IOM CC_RECV_THV_Type CC_RECV_THV;                 
    __IOM CC_FATAL_THV_Type CC_FATAL_THV;               
    __IOM CC_BUS_ERR_ADDR_Type CC_BUS_ERR_ADDR;         
    __IM uint8_t RESERVED0[12];                         
    __IOM CLIENT_ERR_STATUS_Type CLIENT_ERR_STATUS[32]; 
    __IOM CC_CMD_Type CC_sCMD;                          
    __IOM CC_CMD_Type CC_uCMD;                          
    __IM SNOOP_PENDING_Type SNOOP_PENDING;              
    __IM TRANS_PENDING_Type TRANS_PENDING;              
    __IOM CLM_ADDR_BASE_Type CLM_ADDR_BASE;             
    __IOM uint32_t CLM_WAY_EN;                          
    __IOM CC_INVALID_ALL_Type CC_INVALID_ALL;           
    __IOM STM_CTRL_Type STM_CTRL;                       
    __IOM STM_CFG_Type STM_CFG;                         
    __IOM STM_TIMEOUT_Type STM_TIMEOUT;                 
    __IOM DFF_PROT_Type DFF_PROT;                       
    __IOM ECC_ERR_MSK_Type ECC_ERR_MSK;                 
    __IM uint8_t RESERVED1[12];                         
    __IOM NS_RG_Type NS_RG[16];                         
    __IOM SMP_PMON_SEL_Type SMP_PMON_SEL[16];           
    __IOM SMP_PMON_CNT_Type SMP_PMON_CNT[16];           
    __IM uint8_t RESERVED2[64];                         
    __IOM CLIENT_ERR_ADDR_Type CLIENT_ERR_ADDR[32];     
    __IOM CLIENT_WAY_MASK_Type CLIENT_WAY_MASK[32];     
    __IM uint8_t RESERVED3[800];                        
    __IOM CC_INV_RANGE_Type CC_INV_RANGE;               
    __IOM CC_INV_RANGE_START_Type CC_INV_RANGE_START;   
    __IOM CC_INV_RANGE_END_Type CC_INV_RANGE_END;       
    __IM uint8_t RESERVED4[12];                         
    __IOM CC_ECC_INJ_WAY_Type CC_ECC_INJ_WAY;           
    __IOM CC_ECC_INJ_ADDR_Type CC_ECC_INJ_ADDR;         
    __IOM CC_ECC_INJ_DATA_Type CC_ECC_INJ_DATA;         
    __IOM IOCP_ATTR_RMP_Type IOCP_ATTR_RMP;             
} SMPCC_Type;
#pragma pack()
 
#ifndef __SMPCC_BASEADDR
/* Base address of SMPCC(__SMPCC_BASEADDR) should be defined in <Device.h> */
#error "__SMPCC_BASEADDR is not defined, please check!"
#endif
 
/* SMPCC Memory mapping of Device */
#define SMPCC_BASE          __SMPCC_BASEADDR             
#define SMPCC               ((SMPCC_Type *)SMPCC_BASE)    /* end of group NMSIS_Core_SMPCC_Registers */
 
__STATIC_FORCEINLINE SMP_VER_Type SMPCC_GetVersion(void)
{
    return SMPCC->SMP_VER;
}
 
__STATIC_FORCEINLINE uint8_t SMPCC_IsCCachePresent(void)
{
    return SMPCC->SMP_CFG.b.cc_present;
}
 
__STATIC_FORCEINLINE uint8_t SMPCC_GetCoreNum(void)
{
    return SMPCC->SMP_CFG.b.smp_core_num + 1;
}
 
__STATIC_FORCEINLINE uint8_t SMPCC_GetIOCPNum(void)
{
    return SMPCC->SMP_CFG.b.iocp_num;
}
 
__STATIC_FORCEINLINE uint8_t SMPCC_GetPMONNum(void)
{
    return SMPCC->SMP_CFG.b.pmon_num;
}
 
__STATIC_FORCEINLINE uint32_t SMPCC_GetCCacheSetNum(void)
{
    return 1U << SMPCC->CC_CFG.b.cc_set;
}
 
__STATIC_FORCEINLINE uint32_t SMPCC_GetCCacheWayNum(void)
{
    return SMPCC->CC_CFG.b.cc_way + 1;
}
 
__STATIC_FORCEINLINE uint8_t SMPCC_GetCCacheLineSize(void)
{
    return 1 << (SMPCC->CC_CFG.b.cc_lsize + 2);
}
 
__STATIC_FORCEINLINE uint8_t SMPCC_IsCCacheSupportECC(void)
{
    return SMPCC->CC_CFG.b.cc_ecc;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableSnoop(uint16_t client_msk)
{
    SMPCC->SMP_ENB.b.smp_enable |= client_msk;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableSnoop(uint16_t client_msk)
{
    SMPCC->SMP_ENB.b.smp_enable &= ~client_msk;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableCCache(void)
{
    SMPCC->CC_CTRL.b.cc_en = SMPCC_CTRL_CC_EN_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableCCache(void)
{
    SMPCC->CC_CTRL.b.cc_en = SMPCC_CTRL_CC_EN_DISABLE;
}
 
__STATIC_FORCEINLINE int32_t SMPCC_IsCCacheEnabled(void)
{
    return SMPCC->CC_CTRL.b.cc_en;
}
 
__STATIC_FORCEINLINE uint8_t SMPCC_IsAnySnoopPending(uint32_t client_msk)
{
    return (SMPCC->SNOOP_PENDING.b.snoop_pending & client_msk) != 0;
}
 
__STATIC_FORCEINLINE uint8_t SMPCC_IsAnyTransactionPending(uint32_t client_msk)
{
    return (SMPCC->TRANS_PENDING.b.trans_pending & client_msk) != 0;
}
 
__STATIC_FORCEINLINE void SMPCC_SetCLMAllWays(uint64_t addr)
{
#if (__CPU_PA_SIZE > 32)
    SMPCC->CLM_ADDR_BASE.clm_base64 = addr;
#else
    SMPCC->CLM_ADDR_BASE.clm32.clm_base32 = (uint32_t)addr;
#endif
    SMPCC->CLM_WAY_EN = 0xFFFFU;
}
 
__STATIC_FORCEINLINE void SMPCC_SetCLMNWays(uint64_t addr, uint32_t way_msk)
{
#if (__CPU_PA_SIZE > 32)
    SMPCC->CLM_ADDR_BASE.clm_base64 = addr;
#else
    SMPCC->CLM_ADDR_BASE.clm32.clm_base32 = (uint32_t)addr;
#endif
    SMPCC->CLM_WAY_EN = way_msk;
}
 
__STATIC_FORCEINLINE void SMPCC_SetCLMNoWay(void)
{
    SMPCC->CLM_WAY_EN = 0x0000U;
}
 
__STATIC_FORCEINLINE void SMPCC_SetCCacheControl(uint32_t val)
{
     SMPCC->CC_CTRL.w = val;
}
 
__STATIC_FORCEINLINE uint32_t SMPCC_GetCCacheControl(void)
{
     return SMPCC->CC_CTRL.w;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableCCacheECC(void)
{
     SMPCC->CC_CTRL.b.cc_ecc_en = SMPCC_CTRL_CC_ECC_EN_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableCCacheECC(void)
{
     SMPCC->CC_CTRL.b.cc_ecc_en = SMPCC_CTRL_CC_ECC_EN_DISABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableCCacheECCExcp(void)
{
     SMPCC->CC_CTRL.b.ecc_excp_en = SMPCC_CTRL_CC_ECC_EXCP_EN_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableCCacheECCExcp(void)
{
     SMPCC->CC_CTRL.b.ecc_excp_en = SMPCC_CTRL_CC_ECC_EXCP_EN_DISABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_LockECCConfig(void)
{
     SMPCC->CC_CTRL.b.lock_ecc_cfg = SMPCC_CTRL_LOCK_ECC_CFG_LOCK;
}
 
__STATIC_FORCEINLINE void SMPCC_LockECCErrInjection(void)
{
     SMPCC->CC_CTRL.b.lock_ecc_err_inj = SMPCC_CTRL_LOCK_ECC_ERR_INJ_LOCK;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableRecvErrIrq(void)
{
     SMPCC->CC_CTRL.b.recv_err_irq_en = SMPCC_CTRL_RECV_ERR_IRQ_EN_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableRecvErrIrq(void)
{
     SMPCC->CC_CTRL.b.recv_err_irq_en = SMPCC_CTRL_RECV_ERR_IRQ_EN_DISABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableFatalErrIrq(void)
{
     SMPCC->CC_CTRL.b.fatal_err_irq_en = SMPCC_CTRL_FATAL_ERR_IRQ_EN_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_ClearBusErrPending(void)
{
    SMPCC->CC_CTRL.b.bus_err_pend = 0;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableFatalErrIrq(void)
{
     SMPCC->CC_CTRL.b.fatal_err_irq_en = SMPCC_CTRL_FATAL_ERR_IRQ_EN_DISABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableBusErrIrq(void)
{
     SMPCC->CC_CTRL.b.bus_err_irq_en = SMPCC_CTRL_BUS_ERR_IRQ_EN_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableBusErrIrq(void)
{
     SMPCC->CC_CTRL.b.bus_err_irq_en = SMPCC_CTRL_BUS_ERR_IRQ_EN_DISABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableSModeCmd(void)
{
     SMPCC->CC_CTRL.b.sup_cmd_en = SMPCC_CTRL_SUP_CMD_EN_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableSModeCmd(void)
{
     SMPCC->CC_CTRL.b.sup_cmd_en = SMPCC_CTRL_SUP_CMD_EN_DISABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableUModeCmd(void)
{
     SMPCC->CC_CTRL.b.use_cmd_en = SMPCC_CTRL_USE_CMD_EN_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableUModeCmd(void)
{
     SMPCC->CC_CTRL.b.use_cmd_en = SMPCC_CTRL_USE_CMD_EN_DISABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableCCacheECCCheck(void)
{
     SMPCC->CC_CTRL.b.ecc_chk_en = SMPCC_CTRL_ECC_CHK_EN_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableCCacheECCCheck(void)
{
     SMPCC->CC_CTRL.b.ecc_chk_en = SMPCC_CTRL_ECC_CHK_EN_DISABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableCLMECC(void)
{
     SMPCC->CC_CTRL.b.clm_ecc_en = SMPCC_CTRL_CLM_ECC_EN_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableCLMECC(void)
{
     SMPCC->CC_CTRL.b.clm_ecc_en = SMPCC_CTRL_CLM_ECC_EN_DISABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableCLMECCCheck(void)
{
     SMPCC->CC_CTRL.b.clm_ecc_chk_en = SMPCC_CTRL_CLM_ECC_CHK_EN_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableCLMECCCheck(void)
{
     SMPCC->CC_CTRL.b.clm_ecc_chk_en = SMPCC_CTRL_CLM_ECC_CHK_EN_DISABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableCLMECCExcp(void)
{
     SMPCC->CC_CTRL.b.clm_excp_en = SMPCC_CTRL_CLM_EXCP_EN_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableCLMECCExcp(void)
{
     SMPCC->CC_CTRL.b.clm_excp_en = SMPCC_CTRL_CLM_EXCP_EN_DISABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableL1PrefetchShareCacheline(void)
{
    SMPCC->CC_CTRL.b.pf_sh_cl_en = SMPCC_CTRL_PF_SH_CL_EN_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableL1PrefetchShareCacheline(void)
{
    SMPCC->CC_CTRL.b.pf_sh_cl_en = SMPCC_CTRL_PF_SH_CL_EN_DISABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableCCacheEarlyPrefetch(void)
{
    SMPCC->CC_CTRL.b.pf_l2_early_en = SMPCC_CTRL_PF_L2_EARLY_EN_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableCCacheEarlyPrefetch(void)
{
    SMPCC->CC_CTRL.b.pf_l2_early_en = SMPCC_CTRL_PF_L2_EARLY_EN_DISABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_LimitCCachePrefetchOutsNum(void)
{
    SMPCC->CC_CTRL.b.pf_biu_outs_en = SMPCC_CTRL_PF_BIU_OUTS_EN_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_UnlimitCCachePrefetchOutsNum(void)
{
    SMPCC->CC_CTRL.b.pf_biu_outs_en = SMPCC_CTRL_PF_BIU_OUTS_EN_DISABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableCCachePrefetchNoWb(void)
{
    SMPCC->CC_CTRL.b.pf_no_wb = SMPCC_CTRL_PF_NO_WB_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableCCachePrefetchNoWb(void)
{
    SMPCC->CC_CTRL.b.pf_no_wb = SMPCC_CTRL_PF_NO_WB_DISABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableICacheSnoopDCache(void)
{
    SMPCC->CC_CTRL.b.i_snoop_d_en = SMPCC_CTRL_I_SNOOP_D_EN_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableICacheSnoopDCache(void)
{
    SMPCC->CC_CTRL.b.i_snoop_d_en = SMPCC_CTRL_I_SNOOP_D_EN_DISABLE;
}
 
__STATIC_FORCEINLINE uint32_t SMPCC_GetRecvErrCount(void)
{
    return SMPCC->CC_RECV_CNT.b.cnt;
}
 
__STATIC_FORCEINLINE void SMPCC_ClearRecvErrCount(void)
{
    SMPCC->CC_RECV_CNT.w = 0;
}
 
__STATIC_FORCEINLINE uint32_t SMPCC_GetFatalErrCount(void)
{
    return SMPCC->CC_FATAL_CNT.b.cnt;
}
 
__STATIC_FORCEINLINE void SMPCC_ClearFatalErrCount(void)
{
    SMPCC->CC_FATAL_CNT.w = 0;
}
 
__STATIC_FORCEINLINE void SMPCC_SetRecvErrCntThreshold(uint16_t threshold)
{
    SMPCC->CC_RECV_THV.b.cnt = threshold;
}
 
__STATIC_FORCEINLINE uint16_t SMPCC_GetRecvErrCntThreshold(void)
{
    return SMPCC->CC_RECV_THV.b.cnt;
}
 
__STATIC_FORCEINLINE void SMPCC_SetFatalErrCntThreshold(uint16_t threshold)
{
    SMPCC->CC_FATAL_THV.b.cnt = threshold;
}
 
__STATIC_FORCEINLINE uint16_t SMPCC_GetFatalErrCntThreshold(void)
{
    return SMPCC->CC_FATAL_THV.b.cnt;
}
 
__STATIC_FORCEINLINE uint32_t SMPCC_GetClientErrStatus(uint8_t client_id)
{
    return SMPCC->CLIENT_ERR_STATUS[client_id].w;
}
 
__STATIC_FORCEINLINE void SMPCC_SetSTMControl(uint32_t val)
{
    SMPCC->STM_CTRL.w = val;
}
 
__STATIC_FORCEINLINE uint32_t SMPCC_GetSTMControl(void)
{
    return SMPCC->STM_CTRL.w;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableStreamRead(void)
{
    SMPCC->STM_CTRL.b.rd_stm_en = SMPCC_STMCTRL_RD_STM_EN_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableStreamRead(void)
{
    SMPCC->STM_CTRL.b.rd_stm_en = SMPCC_STMCTRL_RD_STM_EN_DISABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableStreamWrite(void)
{
    SMPCC->STM_CTRL.b.wr_stm_en = SMPCC_STMCTRL_WR_STM_EN_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableStreamWrite(void)
{
    SMPCC->STM_CTRL.b.wr_stm_en = SMPCC_STMCTRL_WR_STM_EN_DISABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableStreamTransAlloc(void)
{
    SMPCC->STM_CTRL.b.trans_alloc = SMPCC_STMCTRL_TRANS_ALLOC_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableStreamTransAlloc(void)
{
    SMPCC->STM_CTRL.b.trans_alloc = SMPCC_STMCTRL_TRANS_ALLOC_DISABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableStreamMergeNCRead(void)
{
    SMPCC->STM_CTRL.b.rd_merge_en = SMPCC_STMCTRL_RD_MERGE_EN_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableStreamMergeNCRead(void)
{
    SMPCC->STM_CTRL.b.rd_merge_en = SMPCC_STMCTRL_RD_MERGE_EN_DISABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_EnableStreamReadCross4K(void)
{
    SMPCC->STM_CTRL.b.cross_en = SMPCC_STMCTRL_CROSS_EN_ENABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableStreamReadCross4K(void)
{
    SMPCC->STM_CTRL.b.cross_en = SMPCC_STMCTRL_CROSS_EN_DISABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_SetNSRegionNACL(uint8_t region_id, uint64_t addr)
{
    SMPCC->NS_RG[region_id].dw = SMPCC_NS_RG_CFG_NACL | addr;
}
 
__STATIC_FORCEINLINE void SMPCC_SetNSRegionNAPOT(uint8_t region_id, uint64_t addr)
{
    SMPCC->NS_RG[region_id].dw = SMPCC_NS_RG_CFG_NAPOT | addr;
}
 
__STATIC_FORCEINLINE void SMPCC_DisableNSRegion(uint8_t region_id)
{
    SMPCC->NS_RG[region_id].dw = SMPCC_NS_RG_CFG_DISABLE;
}
 
__STATIC_FORCEINLINE void SMPCC_SetPMONEventSelect(uint8_t idx, uint8_t client_id, uint8_t event)
{
    SMPCC->SMP_PMON_SEL[idx].w = SMPCC_PMON_EVENT(event, client_id);
}
 
__STATIC_FORCEINLINE uint32_t SMPCC_GetPMONEventSelect(uint8_t idx)
{
    return SMPCC->SMP_PMON_SEL[idx].w;
}
 
__STATIC_FORCEINLINE uint64_t SMPCC_GetPMONCount(uint8_t idx)
{
    return SMPCC->SMP_PMON_CNT[idx];
}
 
__STATIC_FORCEINLINE void SMPCC_ClearPMONCount(uint8_t idx)
{
    SMPCC->SMP_PMON_CNT[idx] = 0;
}
 
__STATIC_FORCEINLINE uint64_t SMPCC_GetClientErrAddr(uint8_t client_id)
{
    return SMPCC->CLIENT_ERR_ADDR[client_id];
}
 
__STATIC_FORCEINLINE void SMPCC_MaskClientCCacheWays(uint8_t client_id, uint32_t way_msk)
{
    SMPCC->CLIENT_WAY_MASK[client_id].w = way_msk;
}
 
__STATIC_FORCEINLINE int32_t SMPCC_IsXorErrorInjectMode(void)
{
    return SMPCC->CC_ERR_INJ.b.inj_mode;
}
 
__STATIC_FORCEINLINE void SMPCC_SetECCCode(uint32_t ecc_code)
{
    SMPCC->CC_ERR_INJ.w = (SMPCC->CC_ERR_INJ.w & ~SMPCC_ERR_INJ_INJECCCODE_Msk) |
                          _VAL2FLD(SMPCC_ERR_INJ_INJECCCODE, ecc_code);
}
 
#if defined(__CCM_PRESENT) && (__CCM_PRESENT == 1)
 
__STATIC_FORCEINLINE void SMPCC_CCacheTramErrInject(uint32_t ecc_code, uint32_t *addr, uint16_t way)
{
    if (IINFO_IsPreciseECCInjSupported()) {
        SMPCC->CC_ECC_INJ_ADDR = (unsigned long)addr;
        SMPCC->CC_ECC_INJ_WAY.b.num = way;
        SMPCC->CC_ECC_INJ_DATA = *addr;
    }
    SMPCC_SetECCCode(ecc_code);
    SMPCC_DisableCCacheECCCheck();
    MInvalICacheLine((unsigned long)addr);
    MFlushInvalDCacheCCacheLine((unsigned long)addr);
    __RWMB();
    SMPCC->CC_ERR_INJ.b.inj_tag = SMPCC_ERR_INJ_INJTAG_ENABLE;
 
    if (IINFO_IsPreciseECCInjSupported()) {
        SMPCC->CC_ERR_INJ.b.cs = SMPCC_ERR_INJ_CS_START;
        /* Wait for the ECC injection to complete */
        while (SMPCC->CC_ERR_INJ.b.cs == SMPCC_ERR_INJ_CS_START);
    } else {
        MLockCCacheLine((unsigned long)addr);
    }
 
    SMPCC->CC_ERR_INJ.b.inj_tag = SMPCC_ERR_INJ_INJTAG_DISABLE;
    __RWMB(); // To ensure the ECC error injection is finished
    SMPCC_EnableCCacheECCCheck();
    __RWMB(); // To ensure the ECC check is enabled
}
 
__STATIC_FORCEINLINE void SMPCC_CCacheDramErrInject(uint32_t ecc_code, uint32_t *addr, uint16_t way)
{
    if (IINFO_IsPreciseECCInjSupported()) {
        SMPCC->CC_ECC_INJ_ADDR = (unsigned long)addr;
        SMPCC->CC_ECC_INJ_WAY.b.num = way;
        SMPCC->CC_ECC_INJ_DATA = *addr;
    }
    SMPCC_SetECCCode(ecc_code);
    SMPCC_DisableCCacheECCCheck();
    MInvalICacheLine((unsigned long)addr);
    MFlushInvalDCacheCCacheLine((unsigned long)addr);
    __RWMB();
    SMPCC->CC_ERR_INJ.b.inj_data = SMPCC_ERR_INJ_INJDATA_ENABLE;
 
    if (IINFO_IsPreciseECCInjSupported()) {
        SMPCC->CC_ERR_INJ.b.cs = SMPCC_ERR_INJ_CS_START;
        /* Wait for the ECC injection to complete */
        while (SMPCC->CC_ERR_INJ.b.cs == SMPCC_ERR_INJ_CS_START);
    } else {
        MLockCCacheLine((unsigned long)addr);
    }
 
    SMPCC->CC_ERR_INJ.b.inj_data = SMPCC_ERR_INJ_INJDATA_DISABLE;
    __RWMB(); // To ensure the ECC error injection is finished
    SMPCC_EnableCCacheECCCheck();
    __RWMB(); // To ensure the ECC check is enabled
}
 
__STATIC_FORCEINLINE void SMPCC_CLMErrInject(uint32_t ecc_code, uint32_t *addr)
{
    if (IINFO_IsPreciseECCInjSupported()) {
        SMPCC->CC_ECC_INJ_ADDR = (unsigned long)addr;
        /* The way number should be one-hot, but not used for CLM error injection. */
        SMPCC->CC_ECC_INJ_WAY.b.num = 1;
        SMPCC->CC_ECC_INJ_DATA = *addr;
    }
    SMPCC_SetECCCode(ecc_code);
    SMPCC_DisableCCacheECCCheck();
    MFlushInvalDCacheCCacheLine((unsigned long)addr);
    __RWMB();
    SMPCC->CC_ERR_INJ.b.inj_clm = SMPCC_ERR_INJ_INJCLM_ENABLE;
 
    if (IINFO_IsPreciseECCInjSupported()) {
        SMPCC->CC_ERR_INJ.b.cs = SMPCC_ERR_INJ_CS_START;
        /* Wait for the ECC injection to complete */
        while (SMPCC->CC_ERR_INJ.b.cs == SMPCC_ERR_INJ_CS_START);
    } else {
        MLockCCacheLine((unsigned long)addr);
    }
 
    SMPCC->CC_ERR_INJ.b.inj_clm = SMPCC_ERR_INJ_INJCLM_DISABLE;
    __RWMB(); // To ensure the ECC error injection is finished
    SMPCC_EnableCCacheECCCheck();
    __RWMB(); // To ensure the ECC check is enabled
}
 
__STATIC_FORCEINLINE void SMPCC_CCacheErrRestore(void *addr)
{
    SMPCC_DisableCCacheECCCheck();
    MInvalICacheLine((unsigned long)addr);
    MFlushInvalDCacheCCacheLine((unsigned long)addr);
    MLockCCacheLine((unsigned long)addr);
    SMPCC_EnableCCacheECCCheck();
}
#endif /* #if defined(__CCM_PRESENT) && (__CCM_PRESENT == 1) */
 /* End of Doxygen Group NMSIS_Core_SMPCC_Functions */
#endif /* #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1) */
 
#ifdef __cplusplus
}
#endif
#endif /* __CORE_FEATURE_SMPCC_H__ */