15. Sram_udma_wr_test

15.1. Function description:

This demo shows the function of SRAM Write & Read using UDMA.

Initialize & configure the GMC SRAM controller.
Timing configuration & enable GMC.
Writing the initial value to SRAM bank1 start address in word, half-word or byte.
Configure UDMA to move the data from SRAM bank1 start address to annother adress region in word, half-word or byte.
Waiting UDMA finish the transformation, verify the consistency of the value in two adress region.

Bank	Addr/Data multiplexing enable	Memory bank enable	Memory type	Flash access enable	Bank mapping	Data width	Write enable	Extened mode enable	Continuous clock enbale	Signale extend
bank 1	disable	enable	Nor-Flash	enable	SDRAM bank2 remapped	8 bits	enable	enable	enable	NOE

Addr setup time	Addr hold time	Data setup time	Bus turnaround	Data latency	Early time	Access mode	Clock divide ratio
4	0	4	10	0+2	1	mode B	1+1

Note

Only data latency’s unit is gmc clk cycle, others is bus clock cycle; gmc clk = bus clk / Clock Divide Ratio.

Mode	Buffer size	Des address mode	Src address mode	Transfer width
normal	64 bytes	increasing	increasing	8/16/32 bits

If the data read from SDRAM is same as the data writted to SDRAM by DMA, then print pass, if not print fail.

None