6. Sdram_udma_wr_test

6.1. Function description:

This demo shows the function of SDRAM Write & Read using UDMA.

Initialize & configure the GMC SDRAM controller.
Timing configuration.
Command mode configuration.
Refresh rate & misc configuration.
Writing the initial value to SDRAM start address in word, half-word or byte.
Configure UDMA to move the data from SDRAM start address to annother adress region in word, half-word or byte.
Waiting UDMA finish the transformation, verify the consistency of the value in two address region.

Column bit number	Row bit number	Memory data width	Internal bank Number	Write access enable	Clock divide ratio
9	13	32 bits	4	enable	2

Note

Column & row bit number according the SDRAM storage size to configure; sdc clock = gmc clock/clock divide ratio.

Load to active delay	Exit self-refresh delay	Active to pre-charge delay	Row active to active Delay	Write recovery Delay	Row pre-charge delay	Row to column delay	Delay after CKE asserted
2	4	4	4	2	2	2	2

Note

Only active to pre-charge delay’s unit is gmc clk cycle, others is sdc clock cycle;

Mode	Target bank	Refresh command number	Mode register content
normal	rank0/1	1	0x32

Note

According the refresh period of SDRAM chip’s datasheet to get propriate configure parameter.

Auto-refresh clocks	Power-down clocks	Address mapper mode
32	128	bank row column

Mode	Buffer size	Des address mode	Src address mode	Transfer width
normal	64 bytes	increasing	increasing	8/16/32 bits

If the data read from SDRAM is same as the data writted to SDRAM by DMA, then print pass, if not print fail.

None