8. Sram_bank1_wr_test
8.1. Function description:
This demo shows the function of SRAM Write & Read in BANK2, the memory data bus width is 8bits.
Initialize & configure the GMC SRAM controller.
Timing configuration & enable GMC.
Writing the initial value to SRAM bank2 address in word, half-word or byte, and then read out to compare, covering:
Write to SRAM and then read out to compare in a continue address range by word, half word and byte;
Set/Clear bit one by one step by word, half word and byte, and then read out to compare;
Align test, although the memory data bus width is 8bits, but also can noramlly access the address which the offset is 1/2/3 byte;
First write to 3 continue address regions from start, middle, and end address, then read out to compare for boundary test.
Note
The model is 2KB with 32bit width and memory data bus width is 8bits, so accessible maximux address is 2KB.
8.2. Detail configuration:
8.2.1. Sram controller
Bank |
Addr/Data multiplexing enable |
Memory bank enable |
Memory type |
Flash access enable |
Bank mapping |
Data width |
Write enable |
Extened mode enable |
Continuous clock enbale |
Signale extend |
bank 2 |
disable |
enable |
Nor-Flash |
enable |
SDRAM bank2 remapped |
8 bits |
enable |
enable |
enable |
NOE |
8.2.2. Timing configure
Addr setup time |
Addr hold time |
Data setup time |
Bus turnaround |
Data latency |
Early time |
Access mode |
Clock divide ratio |
4 |
0 |
4 |
10 |
0+2 |
1 |
mode B |
1+1 |
Note
Only data latency’s unit is gmc clk cycle, others is bus clock cycle; gmc clk = bus clk / clock divide ratio.
8.3. Test result:
If the data read from SDRAM is same as the data writted to SDRAM, then print pass, if not print fail.
8.4. IO connection:
None