5. Sdram_8Bit_wr_test

5.1. Function description:

This demo shows the function of SDRAM Write & Read, the memory data bus width is 8bits.

  • Initialize & configure the GMC SDRAM controller.

  • Timing configuration.

  • Command mode configuration.

  • Refresh rate & misc configuration.

  • Start & wait initiation done, then enable GMC.

  • Writing the initial value to SDRAM in word, half-word or byte, and then read out to compare, covering:

  1. Write to SDRAM and then read out to compare in a continue address range by word, half word and byte;

  2. Set/Clear bit one by one step by word, half word and byte, and then read out to compare;

  3. Align test, although the memory data bus width is 8bits, but also can noramlly access the address which the offset is 1/2/3 byte;

  4. First write to 3 continue address regions from start, middle, and end address, then read out to compare for boundary test.

Note

The model is 16MB*2 16bits-width combined into 32bit width, memory data width is 8it, so the max avaliable address range is 16MB.

5.2. Detail configuration:

5.2.1. Sdram controller

Column bit number

Row bit number

Memory data width

Internal bank Number

Write access enable

Clock divide ratio

9

13

8 bits

4

enable

2

Note

Column & row bit number according the SDRAM storage size to configure; sdc clock = gmc clock/clock divide ratio.

5.2.2. Timing configure

Load to active delay

Exit self-refresh delay

Active to pre-charge delay

Row active to active Delay

Write recovery Delay

Row pre-charge delay

Row to column delay

Delay after CKE asserted

2

4

4

4

2

2

2

2

Note

Only active to pre-charge delay’s unit is gmc clk cycle, others is sdc clock cycle;

5.2.3. Command mode

Mode

Target bank

Refresh command number

Mode register content

normal

rank0/1

1

0x32

5.2.4. Refresh rate

Note

According the refresh period of SDRAM chip’s datasheet to get propriate configure parameter.

5.2.5. Misc

Auto-refresh clocks

Power-down clocks

Address mapper mode

32

128

bank row column

5.3. Test result:

If the data read from SDRAM is same as the data writted to SDRAM, then print pass, if not print fail.

5.4. IO connection:

None