Functions that related to the RISC-V FPU (F and D extension). More...

Macros
#define	__RISCV_FLEN 64

#define	__get_FCSR() __RV_CSR_READ(CSR_FCSR)
	Get FCSR CSR Register. More...

#define	__set_FCSR(val) __RV_CSR_WRITE(CSR_FCSR, (val))
	Set FCSR CSR Register with val. More...

#define	__get_FRM() __RV_CSR_READ(CSR_FRM)
	Get FRM CSR Register. More...

#define	__set_FRM(val) __RV_CSR_WRITE(CSR_FRM, (val))
	Set FRM CSR Register with val. More...

#define	__get_FFLAGS() __RV_CSR_READ(CSR_FFLAGS)
	Get FFLAGS CSR Register. More...

#define	__set_FFLAGS(val) __RV_CSR_WRITE(CSR_FFLAGS, (val))
	Set FFLAGS CSR Register with val. More...

#define	__enable_FPU()
	Enable FPU Unit, and set state to initial. More...

#define	__disable_FPU() __RV_CSR_CLEAR(CSR_MSTATUS, MSTATUS_FS)
	Disable FPU Unit. More...

#define	__RV_FLW(freg, addr, ofs)
	Load a single-precision value from memory into float point register freg using flw instruction. More...

#define	__RV_FSW(freg, addr, ofs)
	Store a single-precision value from float point freg into memory using fsw instruction. More...

#define	__RV_FLD(freg, addr, ofs)
	Load a double-precision value from memory into float point register freg using fld instruction. More...

#define	__RV_FSD(freg, addr, ofs)
	Store a double-precision value from float point freg into memory using fsd instruction. More...

#define	__RV_FLOAD __RV_FLD
	Load a float point value from memory into float point register freg using flw/fld instruction. More...

#define	__RV_FSTORE __RV_FSD
	Store a float value from float point freg into memory using fsw/fsd instruction. More...

#define	SAVE_FPU_CONTEXT()
	Save FPU context into variables for interrupt nesting. More...

#define	RESTORE_FPU_CONTEXT()
	Restore necessary fpu registers from variables for interrupt nesting. More...

Typedefs
typedef uint64_t	rv_fpu_t
	Type of FPU register, depends on the FLEN defined in RISC-V. More...

Detailed Description

Functions that related to the RISC-V FPU (F and D extension).

Nuclei provided floating point unit by RISC-V F and D extension.

F extension adds single-precision floating-point computational instructions compliant with the IEEE 754-2008 arithmetic standard, __RISCV_FLEN = 32. The F extension adds 32 floating-point registers, f0-f31, each 32 bits wide, and a floating-point control and status register fcsr, which contains the operating mode and exception status of the floating-point unit.
D extension adds double-precision floating-point computational instructions compliant with the IEEE 754-2008 arithmetic standard. The D extension widens the 32 floating-point registers, f0-f31, to 64 bits, __RISCV_FLEN = 64

Macro Definition Documentation

◆ __disable_FPU

#define __disable_FPU ( ) __RV_CSR_CLEAR(CSR_MSTATUS, MSTATUS_FS)

Disable FPU Unit.

We can save power by disable FPU Unit.
When FPU Unit is disabled, any access to FPU related CSR registers and FPU instructions will cause illegal Instuction Exception.

Definition at line 90 of file core_feature_fpu.h.

◆ __enable_FPU

#define __enable_FPU ( )

Enable FPU Unit, and set state to initial.

Definition at line 80 of file core_feature_fpu.h.

◆ __get_FCSR

#define __get_FCSR ( ) __RV_CSR_READ(CSR_FCSR)

Get FCSR CSR Register.

Definition at line 67 of file core_feature_fpu.h.

◆ __get_FFLAGS

#define __get_FFLAGS ( ) __RV_CSR_READ(CSR_FFLAGS)

Get FFLAGS CSR Register.

Definition at line 75 of file core_feature_fpu.h.

◆ __get_FRM

#define __get_FRM ( ) __RV_CSR_READ(CSR_FRM)

Get FRM CSR Register.

Definition at line 71 of file core_feature_fpu.h.

◆ __RISCV_FLEN

#define __RISCV_FLEN 64

Definition at line 61 of file core_feature_fpu.h.

◆ __RV_FLD

#define __RV_FLD	(	freg,
		addr,
		ofs
	)

Load a double-precision value from memory into float point register freg using fld instruction.

The FLD instruction loads a double-precision floating point value from memory address (addr + ofs) into floating point register freg(f0-f31)

Parameters

[in]	freg	The floating point register, eg. FREG(0), f0
[in]	addr	The memory base address, 8 byte aligned required
[in]	ofs	a 12-bit immediate signed byte offset value, should be an const value

Attention

Function only available for double precision floating point unit, FLEN = 64

Remarks

FLD and FSD operations need to make sure the address is 8 bytes aligned, otherwise it will cause exception code 4(Load address misaligned) or 6 (Store/AMO address misaligned)
FLD and FSD do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.

Definition at line 151 of file core_feature_fpu.h.

◆ __RV_FLOAD

#define __RV_FLOAD __RV_FLD

Load a float point value from memory into float point register freg using flw/fld instruction.

For Single-Precison Floating-Point Mode(__FPU_PRESENT == 1, __RISCV_FLEN == 32): It will call __RV_FLW to load a single-precision floating point value from memory to floating point register
For Double-Precison Floating-Point Mode(__FPU_PRESENT == 2, __RISCV_FLEN == 64): It will call __RV_FLD to load a double-precision floating point value from memory to floating point register

Attention: Function behaviour is different for __FPU_PRESENT = 1 or 2, please see the real function this macro represent

Definition at line 212 of file core_feature_fpu.h.

◆ __RV_FLW

#define __RV_FLW	(	freg,
		addr,
		ofs
	)

Load a single-precision value from memory into float point register freg using flw instruction.

The FLW instruction loads a single-precision floating point value from memory address (addr + ofs) into floating point register freg(f0-f31)

Parameters

[in]	freg	The floating point register, eg. FREG(0), f0
[in]	addr	The memory base address, 4 byte aligned required
[in]	ofs	a 12-bit immediate signed byte offset value, should be an const value

Remarks

FLW and FSW operations need to make sure the address is 4 bytes aligned, otherwise it will cause exception code 4(Load address misaligned) or 6 (Store/AMO address misaligned)
FLW and FSW do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved

Definition at line 107 of file core_feature_fpu.h.

◆ __RV_FSD

#define __RV_FSD	(	freg,
		addr,
		ofs
	)

Store a double-precision value from float point freg into memory using fsd instruction.

The FSD instruction stores double-precision value from floating point register to memory

Parameters

[in]	freg	The floating point register(f0-f31), eg. FREG(0), f0
[in]	addr	The memory base address, 8 byte aligned required
[in]	ofs	a 12-bit immediate signed byte offset value, should be an const value

Attention

Function only available for double precision floating point unit, FLEN = 64

Remarks

FLD and FSD operations need to make sure the address is 8 bytes aligned, otherwise it will cause exception code 4(Load address misaligned) or 6 (Store/AMO address misaligned)
FLD and FSD do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved.

Definition at line 174 of file core_feature_fpu.h.

◆ __RV_FSTORE

#define __RV_FSTORE __RV_FSD

Store a float value from float point freg into memory using fsw/fsd instruction.

For Single-Precison Floating-Point Mode(__FPU_PRESENT == 1, __RISCV_FLEN == 32): It will call __RV_FSW to store floating point register into memory
For Double-Precison Floating-Point Mode(__FPU_PRESENT == 2, __RISCV_FLEN == 64): It will call __RV_FSD to store floating point register into memory

Attention: Function behaviour is different for __FPU_PRESENT = 1 or 2, please see the real function this macro represent

Definition at line 213 of file core_feature_fpu.h.

◆ __RV_FSW

#define __RV_FSW	(	freg,
		addr,
		ofs
	)

Store a single-precision value from float point freg into memory using fsw instruction.

The FSW instruction stores a single-precision value from floating point register to memory

Parameters

[in]	freg	The floating point register(f0-f31), eg. FREG(0), f0
[in]	addr	The memory base address, 4 byte aligned required
[in]	ofs	a 12-bit immediate signed byte offset value, should be an const value

Remarks

FLW and FSW operations need to make sure the address is 4 bytes aligned, otherwise it will cause exception code 4(Load address misaligned) or 6 (Store/AMO address misaligned)
FLW and FSW do not modify the bits being transferred; in particular, the payloads of non-canonical NaNs are preserved

Definition at line 128 of file core_feature_fpu.h.

◆ __set_FCSR

#define __set_FCSR ( val ) __RV_CSR_WRITE(CSR_FCSR, (val))

Set FCSR CSR Register with val.

Definition at line 69 of file core_feature_fpu.h.

◆ __set_FFLAGS

#define __set_FFLAGS ( val ) __RV_CSR_WRITE(CSR_FFLAGS, (val))

Set FFLAGS CSR Register with val.

Definition at line 77 of file core_feature_fpu.h.

◆ __set_FRM

#define __set_FRM ( val ) __RV_CSR_WRITE(CSR_FRM, (val))

Set FRM CSR Register with val.

Definition at line 73 of file core_feature_fpu.h.

◆ RESTORE_FPU_CONTEXT

#define RESTORE_FPU_CONTEXT ( )

Restore necessary fpu registers from variables for interrupt nesting.

This macro is used restore necessary fpu registers from pre-defined variables in SAVE_FPU_CONTEXT macro.

Remarks

It need to be used together with SAVE_FPU_CONTEXT

Definition at line 278 of file core_feature_fpu.h.

◆ SAVE_FPU_CONTEXT

#define SAVE_FPU_CONTEXT ( )

Save FPU context into variables for interrupt nesting.

This macro is used to declare variables which are used for saving FPU context, and it will store the nessary fpu registers into these variables, it need to be used in a interrupt when in this interrupt fpu registers are used.

Remarks

It need to be used together with RESTORE_FPU_CONTEXT
Don't use variable names __fpu_context in your ISR code
If you isr code will use fpu registers, and this interrupt is nested. Then you can do it like this:
void eclic_mtip_handler(void)

{

// !!!Interrupt is enabled here!!!

// !!!Higher priority interrupt could nest it!!!

// Necessary only when you need to use fpu registers

// in this isr handler functions

SAVE_FPU_CONTEXT();

// put you own interrupt handling code here

// pair of SAVE_FPU_CONTEXT()

RESTORE_FPU_CONTEXT();

}

Definition at line 247 of file core_feature_fpu.h.

Typedef Documentation

◆ rv_fpu_t

typedef uint64_t rv_fpu_t

Type of FPU register, depends on the FLEN defined in RISC-V.

Definition at line 215 of file core_feature_fpu.h.

Macros

Typedefs

Detailed Description

Macro Definition Documentation

◆ __disable_FPU

◆ __enable_FPU

◆ __get_FCSR

◆ __get_FFLAGS

◆ __get_FRM

◆ __RISCV_FLEN

◆ __RV_FLD

◆ __RV_FLOAD

◆ __RV_FLW

◆ __RV_FSD

◆ __RV_FSTORE

◆ __RV_FSW

◆ __set_FCSR

◆ __set_FFLAGS

◆ __set_FRM

◆ RESTORE_FPU_CONTEXT

◆ SAVE_FPU_CONTEXT

Typedef Documentation

◆ rv_fpu_t