Register Define and Type Definitions

group NMSIS_Core_Registers

Type definitions and defines for core registers.

Defines

__RISCV_XLEN 32

Refer to the width of an integer register in bits(either 32 or 64)

Typedefs

typedef uint32_t rv_csr_t

Type of Control and Status Register(CSR), depends on the XLEN defined in RISC-V.

Core

group NMSIS_Core_Base_Registers

Type definitions and defines for base core registers.

union CSR_MISA_Type

#include <core_feature_base.h>

Union type to access MISA register.

Public Members

rv_csr_t a

bit: 0 Atomic extension

rv_csr_t b

bit: 1 Tentatively reserved for Bit-Manipulation extension

rv_csr_t c

bit: 2 Compressed extension

rv_csr_t d

bit: 3 Double-precision floating-point extension

Type used for csr data access.

rv_csr_t e

bit: 4 RV32E base ISA

rv_csr_t f

bit: 5 Single-precision floating-point extension

rv_csr_t g

bit: 6 Additional standard extensions present

rv_csr_t h

bit: 7 Hypervisor extension

rv_csr_t i

bit: 8 RV32I/64I/128I base ISA

rv_csr_t j

bit: 9 Tentatively reserved for Dynamically Translated Languages extension

rv_csr_t _reserved1

bit: 10 Reserved

rv_csr_t l

bit: 11 Tentatively reserved for Decimal Floating-Point extension

rv_csr_t m

bit: 12 Integer Multiply/Divide extension

rv_csr_t n

bit: 13 User-level interrupts supported

rv_csr_t _reserved2

bit: 14 Reserved

rv_csr_t p

bit: 15 Tentatively reserved for Packed-SIMD extension

rv_csr_t q

bit: 16 Quad-precision floating-point extension

rv_csr_t _resreved3

bit: 17 Reserved

rv_csr_t s

bit: 18 Supervisor mode implemented

rv_csr_t t

bit: 19 Tentatively reserved for Transactional Memory extension

rv_csr_t u

bit: 20 User mode implemented

rv_csr_t v

bit: 21 Tentatively reserved for Vector extension

rv_csr_t _reserved4

bit: 22 Reserved

rv_csr_t x

bit: 23 Non-standard extensions present

rv_csr_t _reserved5

bit: 24..29 Reserved

rv_csr_t mxl

bit: 30..31 Machine XLEN

struct CSR_MISA_Type::[anonymous] b

Structure used for bit access.

union CSR_MSTATUS_Type

#include <core_feature_base.h>

Union type to access MSTATUS configure register.

Public Members

rv_csr_t _reserved0

bit: 0 Reserved

rv_csr_t sie

bit: 1 supervisor interrupt enable flag

rv_csr_t _reserved1

bit: 2 Reserved

rv_csr_t mie

bit: 3 Machine mode interrupt enable flag

rv_csr_t _reserved2

bit: 4 Reserved

rv_csr_t spie

bit: 3 Supervisor Privilede mode interrupt enable flag

rv_csr_t _reserved3

bit: Reserved

rv_csr_t mpie

bit: mirror of MIE flag

rv_csr_t _reserved4

bit: Reserved

rv_csr_t mpp

bit: mirror of Privilege Mode

rv_csr_t fs

bit: FS status flag

rv_csr_t xs

bit: XS status flag

rv_csr_t mprv

bit: Machine mode PMP

rv_csr_t sum

bit: Supervisor Mode load and store protection

rv_csr_t _reserved6

bit: 19..30 Reserved

rv_csr_t sd

bit: Dirty status for XS or FS

struct CSR_MSTATUS_Type::[anonymous] b

Structure used for bit access.

rv_csr_t d

Type used for csr data access.

union CSR_MTVEC_Type

#include <core_feature_base.h>

Union type to access MTVEC configure register.

Public Members

rv_csr_t mode

bit: 0..2 interrupt mode control

rv_csr_t addr

bit: 3..31 mtvec address

struct CSR_MTVEC_Type::[anonymous] b

Structure used for bit access.

rv_csr_t d

Type used for csr data access.

union CSR_MCAUSE_Type

#include <core_feature_base.h>

Union type to access MCAUSE configure register.

Public Members

rv_csr_t exccode

bit: 11..0 exception or interrupt code

rv_csr_t _reserved0

bit: 15..12 Reserved

rv_csr_t mpil

bit: 23..16 Previous interrupt level

rv_csr_t _reserved1

bit: 26..24 Reserved

rv_csr_t mpie

bit: 27 Interrupt enable flag before enter interrupt

rv_csr_t mpp

bit: 29..28 Privilede mode flag before enter interrupt

rv_csr_t minhv

bit: 30 Machine interrupt vector table

rv_csr_t interrupt

bit: 31 trap type.

0 means exception and 1 means interrupt

struct CSR_MCAUSE_Type::[anonymous] b

Structure used for bit access.

rv_csr_t d

Type used for csr data access.

union CSR_MCOUNTINHIBIT_Type

#include <core_feature_base.h>

Union type to access MCOUNTINHIBIT configure register.

Public Members

rv_csr_t cy

bit: 0 1 means disable mcycle counter

rv_csr_t _reserved0

bit: 1 Reserved

rv_csr_t ir

bit: 2 1 means disable minstret counter

rv_csr_t _reserved1

bit: 3..31 Reserved

struct CSR_MCOUNTINHIBIT_Type::[anonymous] b

Structure used for bit access.

rv_csr_t d

Type used for csr data access.

PLIC

group NMSIS_Core_PLIC_Registers

Type definitions and defines for plic registers.

Defines

PLIC_PRIORITY_OFFSET _AC(0x0000,UL)

PLIC Priority register offset.

PLIC_PRIORITY_SHIFT_PER_SOURCE 2

PLIC Priority register offset shift per source.

PLIC_PENDING_OFFSET _AC(0x1000,UL)

PLIC Pending register offset.

PLIC_PENDING_SHIFT_PER_SOURCE 0

PLIC Pending register offset shift per source.

PLIC_ENABLE_OFFSET _AC(0x2000,UL)

PLIC Enable register offset.

PLIC_ENABLE_SHIFT_PER_TARGET 7

PLIC Enable register offset shift per target.

PLIC_THRESHOLD_OFFSET _AC(0x200000,UL)

PLIC Threshold register offset.

PLIC_CLAIM_OFFSET _AC(0x200004,UL)

PLIC Claim register offset.

PLIC_THRESHOLD_SHIFT_PER_TARGET 12

PLIC Threshold register offset shift per target.

PLIC_CLAIM_SHIFT_PER_TARGET 12

PLIC Claim register offset shift per target.

PLIC_BASE __PLIC_BASEADDR

PLIC Base Address.

SysTimer

group NMSIS_Core_SysTimer_Registers

Type definitions and defines for system timer registers.

Defines

SysTimer_MSIP_MSIP_Pos 0U

SysTick Timer MSIP: MSIP bit Position.

SysTimer_MSIP_MSIP_Msk (1UL << SysTimer_MSIP_MSIP_Pos)

SysTick Timer MSIP: MSIP Mask.

SysTimer_MTIMER_Msk (0xFFFFFFFFFFFFFFFFULL)

SysTick Timer MTIMER value Mask.

SysTimer_MTIMERCMP_Msk (0xFFFFFFFFFFFFFFFFULL)

SysTick Timer MTIMERCMP value Mask.

SysTimer_MSIP_Msk (0xFFFFFFFFUL)

SysTick Timer MSIP value Mask.

SysTimer_BASE __SYSTIMER_BASEADDR

SysTick Base Address.

SysTimer ((SysTimer_Type *) SysTimer_BASE)

SysTick configuration struct.

struct SysTimer_Type

#include <core_feature_timer.h>

Structure type to access the System Timer (SysTimer).

Structure definition to access the system timer(SysTimer).

Remark