DMAMUX
系统直接存储器访问(sys_udma)主要为存储器与存储器之间提供高速数据传输，可以在无需任何CPU操作的情况下通过 sys_udma 进行快速数据搬运， 这样减轻了 CPU 的负担。
系统 udma（sys_udma）
sys_udma 提供了一个 ICB 接口从总线，用于配置访问的地址，类型，长度，优先级等，另外还有 2 组（一组只读，一组只写） ICB 接口的主总线，用于访问系统中的存储器。
sys_udma 具有 8 个存储器到存储器访问通道，通过系统总线来处理数据，总线引入轮询仲裁机制来处理多个主设备发出的请求。
控制器如 sys_udma 结构图 所示。
sys_udma 结构图
hsm_udma
hsm_udma 不仅提供了存储器与存储器之间的数据传输，还提供了 hsm（hardware secure module）中 外设 IP 与 存储器之间的数据交换。hsm_udma 具有 4 个存储器到存储器访问通道和 4 个外设访问通道，其控制器如 hsm_udma 结构图 所示。
hsm_udma 结构图
其外设连接关系如 hsm_udma连接表 所示。
SRC_IP |
SRC_SGL |
SRC_BIT |
DST_IP |
DST_SGL |
DST_BIT |
|---|---|---|---|---|---|
cryp0 |
tx_dma_req |
hsm_udma |
pmem_tran_req0 |
0 |
|
cryp0 |
rx_dma_req |
hsm_udma |
pmem_tran_req1 |
0 |
|
hash0 |
tx_dma_req_o |
hsm_udma |
pmem_tran_req2 |
0 |
|
basic_timer0 |
dma_req_o |
hsm_udma |
pmem_tran_req3 |
0 |
|
hsm_udma |
pmem_tran_ack0 |
0 |
cryp0 |
tx_dma_ack |
|
hsm_udma |
pmem_tran_ack1 |
0 |
cryp0 |
rx_dma_ack |
|
hsm_udma |
pmem_tran_ack2 |
0 |
hash0 |
tx_dma_ack_i |
|
hsm_udma |
pmem_tran_ack3 |
0 |
basic_timer0 |
dma_ack_i |
|
cryp0 |
tx_req_len |
0 |
hsm_udma |
pmem_tran_req0_len |
0 |
cryp0 |
tx_req_len |
1 |
hsm_udma |
pmem_tran_req0_len |
1 |
cryp0 |
tx_req_len |
2 |
hsm_udma |
pmem_tran_req0_len |
2 |
cryp0 |
tx_req_len |
3 |
hsm_udma |
pmem_tran_req0_len |
3 |
cryp0 |
rx_req_len |
0 |
hsm_udma |
pmem_tran_req1_len |
0 |
cryp0 |
rx_req_len |
1 |
hsm_udma |
pmem_tran_req1_len |
1 |
cryp0 |
rx_req_len |
2 |
hsm_udma |
pmem_tran_req1_len |
2 |
cryp0 |
rx_req_len |
3 |
hsm_udma |
pmem_tran_req1_len |
3 |
hash0 |
tx_req_len_o |
0 |
hsm_udma |
pmem_tran_req2_len |
0 |
hash0 |
tx_req_len_o |
1 |
hsm_udma |
pmem_tran_req2_len |
1 |
hash0 |
tx_req_len_o |
2 |
hsm_udma |
pmem_tran_req2_len |
2 |
hash0 |
tx_req_len_o |
3 |
hsm_udma |
pmem_tran_req2_len |
3 |
ACC_UDMA0/ACC_UDMA1
ACC_UDMA0/ACC_UDMA1 不仅提供了存储器与存储器之间的数据传输，还提供了系统域中外设 IP 与 存储器之间的数据交换。ACC_UDMA0 具有 2 个存储器到存储器访问通道和 13 个外设访问通道； ACC_UDMA1 具有 2 个存储器到存储器访问通道和 12 个外设访问通道。并且这两个 ACC_UDMA 控制器 还为外设增加了 mux 功能，软件可以灵活配置物理通道，其控制器如 ACC_UDMA 结构图 所示。
ACC_UDMA 结构图
其具体的外设连接关系如 ACC_UDMA 连接 所示。
SRC_IP |
SRC_SGL |
SRC_BIT |
DST_IP |
DST_SGL |
DST_BIT |
|---|---|---|---|---|---|
USART0 |
USART_dma_tx_req |
ACC_UDMA0 |
pmem_tran_req0 |
0 |
|
USART0 |
USART_dma_rx_req |
ACC_UDMA0 |
pmem_tran_req1 |
0 |
|
USART1 |
USART_dma_tx_req |
ACC_UDMA0 |
pmem_tran_req0 |
1 |
|
USART1 |
USART_dma_rx_req |
ACC_UDMA0 |
pmem_tran_req1 |
1 |
|
USART2 |
USART_dma_tx_req |
ACC_UDMA0 |
pmem_tran_req0 |
2 |
|
USART2 |
USART_dma_rx_req |
ACC_UDMA0 |
pmem_tran_req1 |
2 |
|
USART3 |
USART_dma_tx_req |
ACC_UDMA0 |
pmem_tran_req0 |
3 |
|
USART3 |
USART_dma_rx_req |
ACC_UDMA0 |
pmem_tran_req1 |
3 |
|
USART4 |
USART_dma_tx_req |
ACC_UDMA0 |
pmem_tran_req0 |
4 |
|
USART4 |
USART_dma_rx_req |
ACC_UDMA0 |
pmem_tran_req1 |
4 |
|
USART5 |
USART_dma_tx_req |
ACC_UDMA0 |
pmem_tran_req0 |
5 |
|
USART5 |
USART_dma_rx_req |
ACC_UDMA0 |
pmem_tran_req1 |
5 |
|
USART6 |
USART_dma_tx_req |
ACC_UDMA0 |
pmem_tran_req0 |
6 |
|
USART6 |
USART_dma_rx_req |
ACC_UDMA0 |
pmem_tran_req1 |
6 |
|
USART7 |
USART_dma_tx_req |
ACC_UDMA1 |
pmem_tran_req1 |
6 |
|
USART7 |
USART_dma_rx_req |
ACC_UDMA1 |
pmem_tran_req11 |
3 |
|
USART8 |
USART_dma_tx_req |
ACC_UDMA1 |
pmem_tran_req0 |
0 |
|
USART8 |
USART_dma_rx_req |
ACC_UDMA1 |
pmem_tran_req1 |
0 |
|
USART9 |
USART_dma_tx_req |
ACC_UDMA1 |
pmem_tran_req0 |
1 |
|
USART9 |
USART_dma_rx_req |
ACC_UDMA1 |
pmem_tran_req1 |
1 |
|
USART10 |
USART_dma_tx_req |
ACC_UDMA1 |
pmem_tran_req0 |
2 |
|
USART10 |
USART_dma_rx_req |
ACC_UDMA1 |
pmem_tran_req1 |
2 |
|
USART11 |
USART_dma_tx_req |
ACC_UDMA1 |
pmem_tran_req0 |
3 |
|
USART11 |
USART_dma_rx_req |
ACC_UDMA1 |
pmem_tran_req1 |
3 |
|
USART12 |
USART_dma_tx_req |
ACC_UDMA1 |
pmem_tran_req0 |
4 |
|
USART12 |
USART_dma_rx_req |
ACC_UDMA1 |
pmem_tran_req1 |
4 |
|
ACC_UDMA0 |
pmem_tran_ack0 |
0 |
USART0 |
USART_dma_tx_ack |
|
ACC_UDMA0 |
pmem_tran_ack1 |
0 |
USART0 |
USART_dma_rx_ack |
|
ACC_UDMA0 |
pmem_tran_ack0 |
1 |
USART1 |
USART_dma_tx_ack |
|
ACC_UDMA0 |
pmem_tran_ack1 |
1 |
USART1 |
USART_dma_rx_ack |
|
ACC_UDMA0 |
pmem_tran_ack0 |
2 |
USART2 |
USART_dma_tx_ack |
|
ACC_UDMA0 |
pmem_tran_ack1 |
2 |
USART2 |
USART_dma_rx_ack |
|
ACC_UDMA0 |
pmem_tran_ack0 |
3 |
USART3 |
USART_dma_tx_ack |
|
ACC_UDMA0 |
pmem_tran_ack1 |
3 |
USART3 |
USART_dma_rx_ack |
|
ACC_UDMA0 |
pmem_tran_ack0 |
4 |
USART4 |
USART_dma_tx_ack |
|
ACC_UDMA0 |
pmem_tran_ack1 |
4 |
USART4 |
USART_dma_rx_ack |
|
ACC_UDMA0 |
pmem_tran_ack0 |
5 |
USART5 |
USART_dma_tx_ack |
|
ACC_UDMA0 |
pmem_tran_ack1 |
5 |
USART5 |
USART_dma_rx_ack |
|
ACC_UDMA0 |
pmem_tran_ack0 |
6 |
USART6 |
USART_dma_tx_ack |
|
ACC_UDMA0 |
pmem_tran_ack1 |
6 |
USART6 |
USART_dma_rx_ack |
|
ACC_UDMA1 |
pmem_tran_ack1 |
6 |
USART7 |
USART_dma_tx_ack |
|
ACC_UDMA1 |
pmem_tran_ack11 |
3 |
USART7 |
USART_dma_rx_ack |
|
ACC_UDMA1 |
pmem_tran_ack0 |
0 |
USART8 |
USART_dma_tx_ack |
|
ACC_UDMA1 |
pmem_tran_ack1 |
0 |
USART8 |
USART_dma_rx_ack |
|
ACC_UDMA1 |
pmem_tran_ack0 |
1 |
USART9 |
USART_dma_tx_ack |
|
ACC_UDMA1 |
pmem_tran_ack1 |
1 |
USART9 |
USART_dma_rx_ack |
|
ACC_UDMA1 |
pmem_tran_ack0 |
2 |
USART10 |
USART_dma_tx_ack |
|
ACC_UDMA1 |
pmem_tran_ack1 |
2 |
USART10 |
USART_dma_rx_ack |
|
ACC_UDMA1 |
pmem_tran_ack0 |
3 |
USART11 |
USART_dma_tx_ack |
|
ACC_UDMA1 |
pmem_tran_ack1 |
3 |
USART11 |
USART_dma_rx_ack |
|
ACC_UDMA1 |
pmem_tran_ack0 |
4 |
USART12 |
USART_dma_tx_ack |
|
ACC_UDMA1 |
pmem_tran_ack1 |
4 |
USART12 |
USART_dma_rx_ack |
|
I2C0 |
I2C_dma_tx_req |
ACC_UDMA0 |
pmem_tran_req2 |
0 |
|
I2C0 |
I2C_dma_rx_req |
ACC_UDMA0 |
pmem_tran_req3 |
0 |
|
I2C1 |
I2C_dma_tx_req |
ACC_UDMA0 |
pmem_tran_req2 |
1 |
|
I2C1 |
I2C_dma_rx_req |
ACC_UDMA0 |
pmem_tran_req3 |
1 |
|
I2C2 |
I2C_dma_tx_req |
ACC_UDMA1 |
pmem_tran_req0 |
5 |
|
I2C2 |
I2C_dma_rx_req |
ACC_UDMA1 |
pmem_tran_req1 |
5 |
|
I2C3 |
I2C_dma_tx_req |
ACC_UDMA1 |
pmem_tran_req0 |
6 |
|
I2C3 |
I2C_dma_rx_req |
ACC_UDMA1 |
pmem_tran_req11 |
2 |
|
ACC_UDMA0 |
pmem_tran_ack2 |
0 |
I2C0 |
I2C_dma_tx_ack |
|
ACC_UDMA0 |
pmem_tran_ack3 |
0 |
I2C0 |
I2C_dma_rx_ack |
|
ACC_UDMA0 |
pmem_tran_ack2 |
1 |
I2C1 |
I2C_dma_tx_ack |
|
ACC_UDMA0 |
pmem_tran_ack3 |
1 |
I2C1 |
I2C_dma_rx_ack |
|
ACC_UDMA1 |
pmem_tran_ack0 |
5 |
I2C2 |
I2C_dma_tx_ack |
|
ACC_UDMA1 |
pmem_tran_ack1 |
5 |
I2C2 |
I2C_dma_rx_ack |
|
ACC_UDMA1 |
pmem_tran_ack0 |
6 |
I2C3 |
I2C_dma_tx_ack |
|
ACC_UDMA1 |
pmem_tran_ack11 |
2 |
I2C3 |
I2C_dma_rx_ack |
|
QSPI_XIP0 |
tx_dma_req |
ACC_UDMA0 |
pmem_tran_req2 |
2 |
|
QSPI_XIP0 |
rx_dma_req |
ACC_UDMA0 |
pmem_tran_req3 |
2 |
|
QSPI_XIP1 |
tx_dma_req |
ACC_UDMA0 |
pmem_tran_req2 |
3 |
|
QSPI_XIP1 |
rx_dma_req |
ACC_UDMA0 |
pmem_tran_req3 |
3 |
|
QSPI_XIP2 |
tx_dma_req |
ACC_UDMA0 |
pmem_tran_req2 |
4 |
|
QSPI_XIP2 |
rx_dma_req |
ACC_UDMA0 |
pmem_tran_req3 |
4 |
|
QSPI3 |
tx_dma_req |
ACC_UDMA0 |
pmem_tran_req2 |
7 |
|
QSPI3 |
rx_dma_req |
ACC_UDMA0 |
pmem_tran_req3 |
7 |
|
QSPI4 |
tx_dma_req |
ACC_UDMA1 |
pmem_tran_req0 |
7 |
|
QSPI4 |
rx_dma_req |
ACC_UDMA1 |
pmem_tran_req1 |
7 |
|
QSPI5 |
tx_dma_req |
ACC_UDMA1 |
pmem_tran_req2 |
0 |
|
QSPI5 |
rx_dma_req |
ACC_UDMA1 |
pmem_tran_req3 |
0 |
|
QSPI6 |
tx_dma_req |
ACC_UDMA1 |
pmem_tran_req2 |
1 |
|
QSPI6 |
rx_dma_req |
ACC_UDMA1 |
pmem_tran_req3 |
1 |
|
ACC_UDMA0 |
pmem_tran_ack2 |
2 |
QSPI_XIP0 |
tx_dma_ack |
|
ACC_UDMA0 |
pmem_tran_ack3 |
2 |
QSPI_XIP0 |
rx_dma_ack |
|
ACC_UDMA0 |
pmem_tran_ack2 |
3 |
QSPI_XIP1 |
tx_dma_ack |
|
ACC_UDMA0 |
pmem_tran_ack3 |
3 |
QSPI_XIP1 |
rx_dma_ack |
|
ACC_UDMA0 |
pmem_tran_ack2 |
4 |
QSPI_XIP2 |
tx_dma_ack |
|
ACC_UDMA0 |
pmem_tran_ack3 |
4 |
QSPI_XIP2 |
rx_dma_ack |
|
ACC_UDMA0 |
pmem_tran_ack2 |
7 |
QSPI3 |
tx_dma_ack |
|
ACC_UDMA0 |
pmem_tran_ack3 |
7 |
QSPI3 |
rx_dma_ack |
|
ACC_UDMA1 |
pmem_tran_ack0 |
7 |
QSPI4 |
tx_dma_ack |
|
ACC_UDMA1 |
pmem_tran_ack1 |
7 |
QSPI4 |
rx_dma_ack |
|
ACC_UDMA1 |
pmem_tran_ack2 |
0 |
QSPI5 |
tx_dma_ack |
|
ACC_UDMA1 |
pmem_tran_ack3 |
0 |
QSPI5 |
rx_dma_ack |
|
ACC_UDMA1 |
pmem_tran_ack2 |
1 |
QSPI6 |
tx_dma_ack |
|
ACC_UDMA1 |
pmem_tran_ack3 |
1 |
QSPI6 |
rx_dma_ack |
|
SAI0 |
sai_0_a_tx_dma_req |
ACC_UDMA0 |
pmem_tran_req4 |
0 |
|
SAI0 |
sai_0_a_rx_dma_req |
ACC_UDMA0 |
pmem_tran_req12 |
4 |
|
SAI0 |
sai_0_b_tx_dma_req |
ACC_UDMA0 |
pmem_tran_req4 |
1 |
|
SAI0 |
sai_0_b_rx_dma_req |
ACC_UDMA0 |
pmem_tran_req12 |
5 |
|
SAI0 |
sai_1_a_tx_dma_req |
ACC_UDMA0 |
pmem_tran_req4 |
2 |
|
SAI0 |
sai_1_a_rx_dma_req |
ACC_UDMA0 |
pmem_tran_req12 |
6 |
|
SAI0 |
sai_1_b_tx_dma_req |
ACC_UDMA0 |
pmem_tran_req4 |
3 |
|
SAI0 |
sai_1_b_rx_dma_req |
ACC_UDMA0 |
pmem_tran_req12 |
7 |
|
SAI0 |
sai_2_a_tx_dma_req |
ACC_UDMA1 |
pmem_tran_req2 |
2 |
|
SAI0 |
sai_2_a_rx_dma_req |
ACC_UDMA1 |
pmem_tran_req3 |
2 |
|
SAI0 |
sai_2_b_tx_dma_req |
ACC_UDMA1 |
pmem_tran_req2 |
3 |
|
SAI0 |
sai_2_b_rx_dma_req |
ACC_UDMA1 |
pmem_tran_req3 |
3 |
|
SAI0 |
sai_3_a_tx_dma_req |
ACC_UDMA1 |
pmem_tran_req2 |
4 |
|
SAI0 |
sai_3_a_rx_dma_req |
ACC_UDMA1 |
pmem_tran_req3 |
4 |
|
SAI0 |
sai_3_b_tx_dma_req |
ACC_UDMA1 |
pmem_tran_req2 |
5 |
|
SAI0 |
sai_3_b_rx_dma_req |
ACC_UDMA1 |
pmem_tran_req3 |
5 |
|
ACC_UDMA0 |
pmem_tran_ack4 |
0 |
SAI0 |
sai_0_a_tx_dma_ack |
|
ACC_UDMA0 |
pmem_tran_ack12 |
4 |
SAI0 |
sai_0_a_rx_dma_ack |
|
ACC_UDMA0 |
pmem_tran_ack4 |
1 |
SAI0 |
sai_0_b_tx_dma_ack |
|
ACC_UDMA0 |
pmem_tran_ack12 |
5 |
SAI0 |
sai_0_b_rx_dma_ack |
|
ACC_UDMA0 |
pmem_tran_ack4 |
2 |
SAI0 |
sai_1_a_tx_dma_ack |
|
ACC_UDMA0 |
pmem_tran_ack12 |
6 |
SAI0 |
sai_1_a_rx_dma_ack |
|
ACC_UDMA0 |
pmem_tran_ack4 |
3 |
SAI0 |
sai_1_b_tx_dma_ack |
|
ACC_UDMA0 |
pmem_tran_ack12 |
7 |
SAI0 |
sai_1_b_rx_dma_ack |
|
ACC_UDMA1 |
pmem_tran_ack2 |
2 |
SAI0 |
sai_2_a_tx_dma_ack |
|
ACC_UDMA1 |
pmem_tran_ack3 |
2 |
SAI0 |
sai_2_a_rx_dma_ack |
|
ACC_UDMA1 |
pmem_tran_ack2 |
3 |
SAI0 |
sai_2_b_tx_dma_ack |
|
ACC_UDMA1 |
pmem_tran_ack3 |
3 |
SAI0 |
sai_2_b_rx_dma_ack |
|
ACC_UDMA1 |
pmem_tran_ack2 |
4 |
SAI0 |
sai_3_a_tx_dma_ack |
|
ACC_UDMA1 |
pmem_tran_ack3 |
4 |
SAI0 |
sai_3_a_rx_dma_ack |
|
ACC_UDMA1 |
pmem_tran_ack2 |
5 |
SAI0 |
sai_3_b_tx_dma_ack |
|
ACC_UDMA1 |
pmem_tran_ack3 |
5 |
SAI0 |
sai_3_b_rx_dma_ack |
|
ADC |
o_dma_request_adc0 |
ACC_UDMA1 |
pmem_tran_req2 |
6 |
|
ADC |
o_dma_request_adc1 |
ACC_UDMA1 |
pmem_tran_req3 |
6 |
|
ADC |
o_dma_request_adc2 |
ACC_UDMA1 |
pmem_tran_req2 |
7 |
|
ACC_UDMA1 |
pmem_tran_ack2 |
6 |
ADC |
o_dma_ack_adc0 |
|
ACC_UDMA1 |
pmem_tran_ack3 |
6 |
ADC |
o_dma_ack_adc1 |
|
ACC_UDMA1 |
pmem_tran_ack2 |
7 |
ADC |
o_dma_ack_adc2 |
|
DAC |
o_ch1_dma_req |
ACC_UDMA0 |
pmem_tran_req2 |
5 |
|
DAC |
o_ch2_dma_req |
ACC_UDMA0 |
pmem_tran_req3 |
5 |
|
ACC_UDMA0 |
pmem_tran_ack2 |
5 |
DAC |
i_ch1_dma_ack |
|
ACC_UDMA0 |
pmem_tran_ack3 |
5 |
DAC |
i_ch2_dma_ack |
|
CORDIC0 |
dma_tx_req |
ACC_UDMA0 |
pmem_tran_req4 |
4 |
|
ACC_UDMA0 |
pmem_tran_ack4 |
4 |
CORDIC0 |
dma_tx_ack |
|
CORDIC0 |
dma_rx_req |
ACC_UDMA0 |
pmem_tran_req12 |
1 |
|
ACC_UDMA0 |
pmem_tran_ack12 |
1 |
CORDIC0 |
dma_rx_ack |
|
SWPMI0 |
dma_tx_req |
ACC_UDMA0 |
pmem_tran_req4 |
5 |
|
ACC_UDMA0 |
pmem_tran_ack4 |
5 |
SWPMI0 |
dma_tx_ack |
|
SWPMI0 |
dma_rx_req |
ACC_UDMA0 |
pmem_tran_req12 |
2 |
|
ACC_UDMA0 |
pmem_tran_ack12 |
2 |
SWPMI0 |
dma_rx_ack |
|
SPDIFRX0 |
spdifrx_ctrl_dma_req |
ACC_UDMA0 |
pmem_tran_req4 |
6 |
|
ACC_UDMA0 |
pmem_tran_ack4 |
6 |
SPDIFRX0 |
spdifrx_ctrl_dma_ack |
|
SPDIFRX0 |
spdifrx_dat_dma_req |
ACC_UDMA0 |
pmem_tran_req12 |
3 |
|
ACC_UDMA0 |
pmem_tran_ack12 |
3 |
SPDIFRX0 |
spdifrx_dat_dma_ack |
|
DFSDM0 |
dfsdm_dma_req0 |
ACC_UDMA0 |
pmem_tran_req2 |
6 |
|
ACC_UDMA0 |
pmem_tran_ack2 |
6 |
DFSDM0 |
dfsdm_dma_ack0 |
|
DFSDM0 |
dfsdm_dma_req1 |
ACC_UDMA0 |
pmem_tran_req3 |
6 |
|
ACC_UDMA0 |
pmem_tran_ack3 |
6 |
DFSDM0 |
dfsdm_dma_ack1 |
|
DFSDM0 |
dfsdm_dma_req2 |
ACC_UDMA0 |
pmem_tran_req12 |
0 |
|
ACC_UDMA0 |
pmem_tran_ack12 |
0 |
DFSDM0 |
dfsdm_dma_ack2 |
|
DFSDM0 |
dfsdm_dma_req3 |
ACC_UDMA1 |
pmem_tran_req3 |
7 |
|
ACC_UDMA1 |
pmem_tran_ack3 |
7 |
DFSDM0 |
dfsdm_dma_ack3 |
|
DFSDM0 |
dfsdm_dma_req4 |
ACC_UDMA1 |
pmem_tran_req11 |
4 |
|
ACC_UDMA1 |
pmem_tran_ack11 |
4 |
DFSDM0 |
dfsdm_dma_ack4 |
|
DFSDM0 |
dfsdm_dma_req5 |
ACC_UDMA1 |
pmem_tran_req11 |
5 |
|
ACC_UDMA1 |
pmem_tran_ack11 |
5 |
DFSDM0 |
dfsdm_dma_ack5 |
|
ADVANCED_TIMER0 |
tim2dma_req_com |
ACC_UDMA0 |
pmem_tran_req5 |
0 |
|
ADVANCED_TIMER0 |
tim2dma_req_trg |
ACC_UDMA0 |
pmem_tran_req6 |
0 |
|
ADVANCED_TIMER0 |
tim2dma_req_uev |
ACC_UDMA0 |
pmem_tran_req7 |
0 |
|
ADVANCED_TIMER0 |
tim2dma_req_cc1 |
ACC_UDMA0 |
pmem_tran_req8 |
0 |
|
ADVANCED_TIMER0 |
tim2dma_req_cc2 |
ACC_UDMA0 |
pmem_tran_req9 |
0 |
|
ADVANCED_TIMER0 |
tim2dma_req_cc3 |
ACC_UDMA0 |
pmem_tran_req10 |
0 |
|
ADVANCED_TIMER0 |
tim2dma_req_cc4 |
ACC_UDMA0 |
pmem_tran_req11 |
0 |
|
ADVANCED_TIMER1 |
tim2dma_req_com |
ACC_UDMA0 |
pmem_tran_req5 |
1 |
|
ADVANCED_TIMER1 |
tim2dma_req_trg |
ACC_UDMA0 |
pmem_tran_req6 |
1 |
|
ADVANCED_TIMER1 |
tim2dma_req_uev |
ACC_UDMA0 |
pmem_tran_req7 |
1 |
|
ADVANCED_TIMER1 |
tim2dma_req_cc1 |
ACC_UDMA0 |
pmem_tran_req8 |
1 |
|
ADVANCED_TIMER1 |
tim2dma_req_cc2 |
ACC_UDMA0 |
pmem_tran_req9 |
1 |
|
ADVANCED_TIMER1 |
tim2dma_req_cc3 |
ACC_UDMA0 |
pmem_tran_req10 |
1 |
|
ADVANCED_TIMER1 |
tim2dma_req_cc4 |
ACC_UDMA0 |
pmem_tran_req11 |
1 |
|
ADVANCED_TIMER2 |
tim2dma_req_com |
ACC_UDMA0 |
pmem_tran_req5 |
2 |
|
ADVANCED_TIMER2 |
tim2dma_req_trg |
ACC_UDMA0 |
pmem_tran_req6 |
2 |
|
ADVANCED_TIMER2 |
tim2dma_req_uev |
ACC_UDMA0 |
pmem_tran_req7 |
2 |
|
ADVANCED_TIMER2 |
tim2dma_req_cc1 |
ACC_UDMA0 |
pmem_tran_req8 |
2 |
|
ADVANCED_TIMER2 |
tim2dma_req_cc2 |
ACC_UDMA0 |
pmem_tran_req9 |
2 |
|
ADVANCED_TIMER2 |
tim2dma_req_cc3 |
ACC_UDMA0 |
pmem_tran_req10 |
2 |
|
ADVANCED_TIMER2 |
tim2dma_req_cc4 |
ACC_UDMA0 |
pmem_tran_req11 |
2 |
|
ADVANCED_TIMER3 |
tim2dma_req_com |
ACC_UDMA0 |
pmem_tran_req5 |
3 |
|
ADVANCED_TIMER3 |
tim2dma_req_trg |
ACC_UDMA0 |
pmem_tran_req6 |
3 |
|
ADVANCED_TIMER3 |
tim2dma_req_uev |
ACC_UDMA0 |
pmem_tran_req7 |
3 |
|
ADVANCED_TIMER3 |
tim2dma_req_cc1 |
ACC_UDMA0 |
pmem_tran_req8 |
3 |
|
ADVANCED_TIMER3 |
tim2dma_req_cc2 |
ACC_UDMA0 |
pmem_tran_req9 |
3 |
|
ADVANCED_TIMER3 |
tim2dma_req_cc3 |
ACC_UDMA0 |
pmem_tran_req10 |
3 |
|
ADVANCED_TIMER3 |
tim2dma_req_cc4 |
ACC_UDMA0 |
pmem_tran_req11 |
3 |
|
ADVANCED_TIMER4 |
tim2dma_req_com |
ACC_UDMA0 |
pmem_tran_req5 |
4 |
|
ADVANCED_TIMER4 |
tim2dma_req_trg |
ACC_UDMA0 |
pmem_tran_req6 |
4 |
|
ADVANCED_TIMER4 |
tim2dma_req_uev |
ACC_UDMA0 |
pmem_tran_req7 |
4 |
|
ADVANCED_TIMER4 |
tim2dma_req_cc1 |
ACC_UDMA0 |
pmem_tran_req8 |
4 |
|
ADVANCED_TIMER4 |
tim2dma_req_cc2 |
ACC_UDMA0 |
pmem_tran_req9 |
4 |
|
ADVANCED_TIMER4 |
tim2dma_req_cc3 |
ACC_UDMA0 |
pmem_tran_req10 |
4 |
|
ADVANCED_TIMER4 |
tim2dma_req_cc4 |
ACC_UDMA0 |
pmem_tran_req11 |
4 |
|
ADVANCED_TIMER5 |
tim2dma_req_com |
ACC_UDMA0 |
pmem_tran_req5 |
5 |
|
ADVANCED_TIMER5 |
tim2dma_req_trg |
ACC_UDMA0 |
pmem_tran_req6 |
5 |
|
ADVANCED_TIMER5 |
tim2dma_req_uev |
ACC_UDMA0 |
pmem_tran_req7 |
5 |
|
ADVANCED_TIMER5 |
tim2dma_req_cc1 |
ACC_UDMA0 |
pmem_tran_req8 |
5 |
|
ADVANCED_TIMER5 |
tim2dma_req_cc2 |
ACC_UDMA0 |
pmem_tran_req9 |
5 |
|
ADVANCED_TIMER5 |
tim2dma_req_cc3 |
ACC_UDMA0 |
pmem_tran_req10 |
5 |
|
ADVANCED_TIMER5 |
tim2dma_req_cc4 |
ACC_UDMA0 |
pmem_tran_req11 |
5 |
|
ADVANCED_TIMER6 |
tim2dma_req_com |
ACC_UDMA0 |
pmem_tran_req5 |
6 |
|
ADVANCED_TIMER6 |
tim2dma_req_trg |
ACC_UDMA0 |
pmem_tran_req6 |
6 |
|
ADVANCED_TIMER6 |
tim2dma_req_uev |
ACC_UDMA0 |
pmem_tran_req7 |
6 |
|
ADVANCED_TIMER6 |
tim2dma_req_cc1 |
ACC_UDMA0 |
pmem_tran_req8 |
6 |
|
ADVANCED_TIMER6 |
tim2dma_req_cc2 |
ACC_UDMA0 |
pmem_tran_req9 |
6 |
|
ADVANCED_TIMER6 |
tim2dma_req_cc3 |
ACC_UDMA0 |
pmem_tran_req10 |
6 |
|
ADVANCED_TIMER6 |
tim2dma_req_cc4 |
ACC_UDMA0 |
pmem_tran_req11 |
6 |
|
ADVANCED_TIMER7 |
tim2dma_req_com |
ACC_UDMA0 |
pmem_tran_req5 |
7 |
|
ADVANCED_TIMER7 |
tim2dma_req_trg |
ACC_UDMA0 |
pmem_tran_req6 |
7 |
|
ADVANCED_TIMER7 |
tim2dma_req_uev |
ACC_UDMA0 |
pmem_tran_req7 |
7 |
|
ADVANCED_TIMER7 |
tim2dma_req_cc1 |
ACC_UDMA0 |
pmem_tran_req8 |
7 |
|
ADVANCED_TIMER7 |
tim2dma_req_cc2 |
ACC_UDMA0 |
pmem_tran_req9 |
7 |
|
ADVANCED_TIMER7 |
tim2dma_req_cc3 |
ACC_UDMA0 |
pmem_tran_req10 |
7 |
|
ADVANCED_TIMER7 |
tim2dma_req_cc4 |
ACC_UDMA0 |
pmem_tran_req11 |
7 |
|
ADVANCED_TIMER8 |
tim2dma_req_com |
ACC_UDMA1 |
pmem_tran_req4 |
0 |
|
ADVANCED_TIMER8 |
tim2dma_req_trg |
ACC_UDMA1 |
pmem_tran_req5 |
0 |
|
ADVANCED_TIMER8 |
tim2dma_req_uev |
ACC_UDMA1 |
pmem_tran_req6 |
0 |
|
ADVANCED_TIMER8 |
tim2dma_req_cc1 |
ACC_UDMA1 |
pmem_tran_req7 |
0 |
|
ADVANCED_TIMER8 |
tim2dma_req_cc2 |
ACC_UDMA1 |
pmem_tran_req8 |
0 |
|
ADVANCED_TIMER8 |
tim2dma_req_cc3 |
ACC_UDMA1 |
pmem_tran_req9 |
0 |
|
ADVANCED_TIMER8 |
tim2dma_req_cc4 |
ACC_UDMA1 |
pmem_tran_req10 |
0 |
|
ADVANCED_TIMER9 |
tim2dma_req_com |
ACC_UDMA1 |
pmem_tran_req4 |
1 |
|
ADVANCED_TIMER9 |
tim2dma_req_trg |
ACC_UDMA1 |
pmem_tran_req5 |
1 |
|
ADVANCED_TIMER9 |
tim2dma_req_uev |
ACC_UDMA1 |
pmem_tran_req6 |
1 |
|
ADVANCED_TIMER9 |
tim2dma_req_cc1 |
ACC_UDMA1 |
pmem_tran_req7 |
1 |
|
ADVANCED_TIMER9 |
tim2dma_req_cc2 |
ACC_UDMA1 |
pmem_tran_req8 |
1 |
|
ADVANCED_TIMER9 |
tim2dma_req_cc3 |
ACC_UDMA1 |
pmem_tran_req9 |
1 |
|
ADVANCED_TIMER9 |
tim2dma_req_cc4 |
ACC_UDMA1 |
pmem_tran_req10 |
1 |
|
ADVANCED_TIMER10 |
tim2dma_req_com |
ACC_UDMA1 |
pmem_tran_req4 |
2 |
|
ADVANCED_TIMER10 |
tim2dma_req_trg |
ACC_UDMA1 |
pmem_tran_req5 |
2 |
|
ADVANCED_TIMER10 |
tim2dma_req_uev |
ACC_UDMA1 |
pmem_tran_req6 |
2 |
|
ADVANCED_TIMER10 |
tim2dma_req_cc1 |
ACC_UDMA1 |
pmem_tran_req7 |
2 |
|
ADVANCED_TIMER10 |
tim2dma_req_cc2 |
ACC_UDMA1 |
pmem_tran_req8 |
2 |
|
ADVANCED_TIMER10 |
tim2dma_req_cc3 |
ACC_UDMA1 |
pmem_tran_req9 |
2 |
|
ADVANCED_TIMER10 |
tim2dma_req_cc4 |
ACC_UDMA1 |
pmem_tran_req10 |
2 |
|
ADVANCED_TIMER11 |
tim2dma_req_com |
ACC_UDMA1 |
pmem_tran_req4 |
3 |
|
ADVANCED_TIMER11 |
tim2dma_req_trg |
ACC_UDMA1 |
pmem_tran_req5 |
3 |
|
ADVANCED_TIMER11 |
tim2dma_req_uev |
ACC_UDMA1 |
pmem_tran_req6 |
3 |
|
ADVANCED_TIMER11 |
tim2dma_req_cc1 |
ACC_UDMA1 |
pmem_tran_req7 |
3 |
|
ADVANCED_TIMER11 |
tim2dma_req_cc2 |
ACC_UDMA1 |
pmem_tran_req8 |
3 |
|
ADVANCED_TIMER11 |
tim2dma_req_cc3 |
ACC_UDMA1 |
pmem_tran_req9 |
3 |
|
ADVANCED_TIMER11 |
tim2dma_req_cc4 |
ACC_UDMA1 |
pmem_tran_req10 |
3 |
|
ADVANCED_TIMER12 |
tim2dma_req_com |
ACC_UDMA1 |
pmem_tran_req4 |
4 |
|
ADVANCED_TIMER12 |
tim2dma_req_trg |
ACC_UDMA1 |
pmem_tran_req5 |
4 |
|
ADVANCED_TIMER12 |
tim2dma_req_uev |
ACC_UDMA1 |
pmem_tran_req6 |
4 |
|
ADVANCED_TIMER12 |
tim2dma_req_cc1 |
ACC_UDMA1 |
pmem_tran_req7 |
4 |
|
ADVANCED_TIMER12 |
tim2dma_req_cc2 |
ACC_UDMA1 |
pmem_tran_req8 |
4 |
|
ADVANCED_TIMER12 |
tim2dma_req_cc3 |
ACC_UDMA1 |
pmem_tran_req9 |
4 |
|
ADVANCED_TIMER12 |
tim2dma_req_cc4 |
ACC_UDMA1 |
pmem_tran_req10 |
4 |
|
ADVANCED_TIMER13 |
tim2dma_req_com |
ACC_UDMA1 |
pmem_tran_req4 |
5 |
|
ADVANCED_TIMER13 |
tim2dma_req_trg |
ACC_UDMA1 |
pmem_tran_req5 |
5 |
|
ADVANCED_TIMER13 |
tim2dma_req_uev |
ACC_UDMA1 |
pmem_tran_req6 |
5 |
|
ADVANCED_TIMER13 |
tim2dma_req_cc1 |
ACC_UDMA1 |
pmem_tran_req7 |
5 |
|
ADVANCED_TIMER13 |
tim2dma_req_cc2 |
ACC_UDMA1 |
pmem_tran_req8 |
5 |
|
ADVANCED_TIMER13 |
tim2dma_req_cc3 |
ACC_UDMA1 |
pmem_tran_req9 |
5 |
|
ADVANCED_TIMER13 |
tim2dma_req_cc4 |
ACC_UDMA1 |
pmem_tran_req10 |
5 |
|
ADVANCED_TIMER14 |
tim2dma_req_com |
ACC_UDMA1 |
pmem_tran_req4 |
6 |
|
ADVANCED_TIMER14 |
tim2dma_req_trg |
ACC_UDMA1 |
pmem_tran_req5 |
6 |
|
ADVANCED_TIMER14 |
tim2dma_req_uev |
ACC_UDMA1 |
pmem_tran_req6 |
6 |
|
ADVANCED_TIMER14 |
tim2dma_req_cc1 |
ACC_UDMA1 |
pmem_tran_req7 |
6 |
|
ADVANCED_TIMER14 |
tim2dma_req_cc2 |
ACC_UDMA1 |
pmem_tran_req8 |
6 |
|
ADVANCED_TIMER14 |
tim2dma_req_cc3 |
ACC_UDMA1 |
pmem_tran_req9 |
6 |
|
ADVANCED_TIMER14 |
tim2dma_req_cc4 |
ACC_UDMA1 |
pmem_tran_req10 |
6 |
|
ADVANCED_TIMER15 |
tim2dma_req_com |
ACC_UDMA1 |
pmem_tran_req4 |
7 |
|
ADVANCED_TIMER15 |
tim2dma_req_trg |
ACC_UDMA1 |
pmem_tran_req5 |
7 |
|
ADVANCED_TIMER15 |
tim2dma_req_uev |
ACC_UDMA1 |
pmem_tran_req6 |
7 |
|
ADVANCED_TIMER15 |
tim2dma_req_cc1 |
ACC_UDMA1 |
pmem_tran_req7 |
7 |
|
ADVANCED_TIMER15 |
tim2dma_req_cc2 |
ACC_UDMA1 |
pmem_tran_req8 |
7 |
|
ADVANCED_TIMER15 |
tim2dma_req_cc3 |
ACC_UDMA1 |
pmem_tran_req9 |
7 |
|
ADVANCED_TIMER15 |
tim2dma_req_cc4 |
ACC_UDMA1 |
pmem_tran_req10 |
7 |
|
ACC_UDMA0 |
pmem_tran_ack5 |
0 |
ADVANCED_TIMER0 |
dma2tim_clr_com |
|
ACC_UDMA0 |
pmem_tran_ack6 |
0 |
ADVANCED_TIMER0 |
dma2tim_clr_trg |
|
ACC_UDMA0 |
pmem_tran_ack7 |
0 |
ADVANCED_TIMER0 |
dma2tim_clr_uev |
|
ACC_UDMA0 |
pmem_tran_ack8 |
0 |
ADVANCED_TIMER0 |
dma2tim_clr_cc1 |
|
ACC_UDMA0 |
pmem_tran_ack9 |
0 |
ADVANCED_TIMER0 |
dma2tim_clr_cc2 |
|
ACC_UDMA0 |
pmem_tran_ack10 |
0 |
ADVANCED_TIMER0 |
dma2tim_clr_cc3 |
|
ACC_UDMA0 |
pmem_tran_ack11 |
0 |
ADVANCED_TIMER0 |
dma2tim_clr_cc4 |
|
ACC_UDMA0 |
pmem_tran_ack5 |
1 |
ADVANCED_TIMER1 |
dma2tim_clr_com |
|
ACC_UDMA0 |
pmem_tran_ack6 |
1 |
ADVANCED_TIMER1 |
dma2tim_clr_trg |
|
ACC_UDMA0 |
pmem_tran_ack7 |
1 |
ADVANCED_TIMER1 |
dma2tim_clr_uev |
|
ACC_UDMA0 |
pmem_tran_ack8 |
1 |
ADVANCED_TIMER1 |
dma2tim_clr_cc1 |
|
ACC_UDMA0 |
pmem_tran_ack9 |
1 |
ADVANCED_TIMER1 |
dma2tim_clr_cc2 |
|
ACC_UDMA0 |
pmem_tran_ack10 |
1 |
ADVANCED_TIMER1 |
dma2tim_clr_cc3 |
|
ACC_UDMA0 |
pmem_tran_ack11 |
1 |
ADVANCED_TIMER1 |
dma2tim_clr_cc4 |
|
ACC_UDMA0 |
pmem_tran_ack5 |
2 |
ADVANCED_TIMER2 |
dma2tim_clr_com |
|
ACC_UDMA0 |
pmem_tran_ack6 |
2 |
ADVANCED_TIMER2 |
dma2tim_clr_trg |
|
ACC_UDMA0 |
pmem_tran_ack7 |
2 |
ADVANCED_TIMER2 |
dma2tim_clr_uev |
|
ACC_UDMA0 |
pmem_tran_ack8 |
2 |
ADVANCED_TIMER2 |
dma2tim_clr_cc1 |
|
ACC_UDMA0 |
pmem_tran_ack9 |
2 |
ADVANCED_TIMER2 |
dma2tim_clr_cc2 |
|
ACC_UDMA0 |
pmem_tran_ack10 |
2 |
ADVANCED_TIMER2 |
dma2tim_clr_cc3 |
|
ACC_UDMA0 |
pmem_tran_ack11 |
2 |
ADVANCED_TIMER2 |
dma2tim_clr_cc4 |
|
ACC_UDMA0 |
pmem_tran_ack5 |
3 |
ADVANCED_TIMER3 |
dma2tim_clr_com |
|
ACC_UDMA0 |
pmem_tran_ack6 |
3 |
ADVANCED_TIMER3 |
dma2tim_clr_trg |
|
ACC_UDMA0 |
pmem_tran_ack7 |
3 |
ADVANCED_TIMER3 |
dma2tim_clr_uev |
|
ACC_UDMA0 |
pmem_tran_ack8 |
3 |
ADVANCED_TIMER3 |
dma2tim_clr_cc1 |
|
ACC_UDMA0 |
pmem_tran_ack9 |
3 |
ADVANCED_TIMER3 |
dma2tim_clr_cc2 |
|
ACC_UDMA0 |
pmem_tran_ack10 |
3 |
ADVANCED_TIMER3 |
dma2tim_clr_cc3 |
|
ACC_UDMA0 |
pmem_tran_ack11 |
3 |
ADVANCED_TIMER3 |
dma2tim_clr_cc4 |
|
ACC_UDMA0 |
pmem_tran_ack5 |
4 |
ADVANCED_TIMER4 |
dma2tim_clr_com |
|
ACC_UDMA0 |
pmem_tran_ack6 |
4 |
ADVANCED_TIMER4 |
dma2tim_clr_trg |
|
ACC_UDMA0 |
pmem_tran_ack7 |
4 |
ADVANCED_TIMER4 |
dma2tim_clr_uev |
|
ACC_UDMA0 |
pmem_tran_ack8 |
4 |
ADVANCED_TIMER4 |
dma2tim_clr_cc1 |
|
ACC_UDMA0 |
pmem_tran_ack9 |
4 |
ADVANCED_TIMER4 |
dma2tim_clr_cc2 |
|
ACC_UDMA0 |
pmem_tran_ack10 |
4 |
ADVANCED_TIMER4 |
dma2tim_clr_cc3 |
|
ACC_UDMA0 |
pmem_tran_ack11 |
4 |
ADVANCED_TIMER4 |
dma2tim_clr_cc4 |
|
ACC_UDMA0 |
pmem_tran_ack5 |
5 |
ADVANCED_TIMER5 |
dma2tim_clr_com |
|
ACC_UDMA0 |
pmem_tran_ack6 |
5 |
ADVANCED_TIMER5 |
dma2tim_clr_trg |
|
ACC_UDMA0 |
pmem_tran_ack7 |
5 |
ADVANCED_TIMER5 |
dma2tim_clr_uev |
|
ACC_UDMA0 |
pmem_tran_ack8 |
5 |
ADVANCED_TIMER5 |
dma2tim_clr_cc1 |
|
ACC_UDMA0 |
pmem_tran_ack9 |
5 |
ADVANCED_TIMER5 |
dma2tim_clr_cc2 |
|
ACC_UDMA0 |
pmem_tran_ack10 |
5 |
ADVANCED_TIMER5 |
dma2tim_clr_cc3 |
|
ACC_UDMA0 |
pmem_tran_ack11 |
5 |
ADVANCED_TIMER5 |
dma2tim_clr_cc4 |
|
ACC_UDMA0 |
pmem_tran_ack5 |
6 |
ADVANCED_TIMER6 |
dma2tim_clr_com |
|
ACC_UDMA0 |
pmem_tran_ack6 |
6 |
ADVANCED_TIMER6 |
dma2tim_clr_trg |
|
ACC_UDMA0 |
pmem_tran_ack7 |
6 |
ADVANCED_TIMER6 |
dma2tim_clr_uev |
|
ACC_UDMA0 |
pmem_tran_ack8 |
6 |
ADVANCED_TIMER6 |
dma2tim_clr_cc1 |
|
ACC_UDMA0 |
pmem_tran_ack9 |
6 |
ADVANCED_TIMER6 |
dma2tim_clr_cc2 |
|
ACC_UDMA0 |
pmem_tran_ack10 |
6 |
ADVANCED_TIMER6 |
dma2tim_clr_cc3 |
|
ACC_UDMA0 |
pmem_tran_ack11 |
6 |
ADVANCED_TIMER6 |
dma2tim_clr_cc4 |
|
ACC_UDMA0 |
pmem_tran_ack5 |
7 |
ADVANCED_TIMER7 |
dma2tim_clr_com |
|
ACC_UDMA0 |
pmem_tran_ack6 |
7 |
ADVANCED_TIMER7 |
dma2tim_clr_trg |
|
ACC_UDMA0 |
pmem_tran_ack7 |
7 |
ADVANCED_TIMER7 |
dma2tim_clr_uev |
|
ACC_UDMA0 |
pmem_tran_ack8 |
7 |
ADVANCED_TIMER7 |
dma2tim_clr_cc1 |
|
ACC_UDMA0 |
pmem_tran_ack9 |
7 |
ADVANCED_TIMER7 |
dma2tim_clr_cc2 |
|
ACC_UDMA0 |
pmem_tran_ack10 |
7 |
ADVANCED_TIMER7 |
dma2tim_clr_cc3 |
|
ACC_UDMA0 |
pmem_tran_ack11 |
7 |
ADVANCED_TIMER7 |
dma2tim_clr_cc4 |
|
ACC_UDMA1 |
pmem_tran_ack4 |
0 |
ADVANCED_TIMER8 |
dma2tim_clr_com |
|
ACC_UDMA1 |
pmem_tran_ack5 |
0 |
ADVANCED_TIMER8 |
dma2tim_clr_trg |
|
ACC_UDMA1 |
pmem_tran_ack6 |
0 |
ADVANCED_TIMER8 |
dma2tim_clr_uev |
|
ACC_UDMA1 |
pmem_tran_ack7 |
0 |
ADVANCED_TIMER8 |
dma2tim_clr_cc1 |
|
ACC_UDMA1 |
pmem_tran_ack8 |
0 |
ADVANCED_TIMER8 |
dma2tim_clr_cc2 |
|
ACC_UDMA1 |
pmem_tran_ack9 |
0 |
ADVANCED_TIMER8 |
dma2tim_clr_cc3 |
|
ACC_UDMA1 |
pmem_tran_ack10 |
0 |
ADVANCED_TIMER8 |
dma2tim_clr_cc4 |
|
ACC_UDMA1 |
pmem_tran_ack4 |
1 |
ADVANCED_TIMER9 |
dma2tim_clr_com |
|
ACC_UDMA1 |
pmem_tran_ack5 |
1 |
ADVANCED_TIMER9 |
dma2tim_clr_trg |
|
ACC_UDMA1 |
pmem_tran_ack6 |
1 |
ADVANCED_TIMER9 |
dma2tim_clr_uev |
|
ACC_UDMA1 |
pmem_tran_ack7 |
1 |
ADVANCED_TIMER9 |
dma2tim_clr_cc1 |
|
ACC_UDMA1 |
pmem_tran_ack8 |
1 |
ADVANCED_TIMER9 |
dma2tim_clr_cc2 |
|
ACC_UDMA1 |
pmem_tran_ack9 |
1 |
ADVANCED_TIMER9 |
dma2tim_clr_cc3 |
|
ACC_UDMA1 |
pmem_tran_ack10 |
1 |
ADVANCED_TIMER9 |
dma2tim_clr_cc4 |
|
ACC_UDMA1 |
pmem_tran_ack4 |
2 |
ADVANCED_TIMER10 |
dma2tim_clr_com |
|
ACC_UDMA1 |
pmem_tran_ack5 |
2 |
ADVANCED_TIMER10 |
dma2tim_clr_trg |
|
ACC_UDMA1 |
pmem_tran_ack6 |
2 |
ADVANCED_TIMER10 |
dma2tim_clr_uev |
|
ACC_UDMA1 |
pmem_tran_ack7 |
2 |
ADVANCED_TIMER10 |
dma2tim_clr_cc1 |
|
ACC_UDMA1 |
pmem_tran_ack8 |
2 |
ADVANCED_TIMER10 |
dma2tim_clr_cc2 |
|
ACC_UDMA1 |
pmem_tran_ack9 |
2 |
ADVANCED_TIMER10 |
dma2tim_clr_cc3 |
|
ACC_UDMA1 |
pmem_tran_ack10 |
2 |
ADVANCED_TIMER10 |
dma2tim_clr_cc4 |
|
ACC_UDMA1 |
pmem_tran_ack4 |
3 |
ADVANCED_TIMER11 |
dma2tim_clr_com |
|
ACC_UDMA1 |
pmem_tran_ack5 |
3 |
ADVANCED_TIMER11 |
dma2tim_clr_trg |
|
ACC_UDMA1 |
pmem_tran_ack6 |
3 |
ADVANCED_TIMER11 |
dma2tim_clr_uev |
|
ACC_UDMA1 |
pmem_tran_ack7 |
3 |
ADVANCED_TIMER11 |
dma2tim_clr_cc1 |
|
ACC_UDMA1 |
pmem_tran_ack8 |
3 |
ADVANCED_TIMER11 |
dma2tim_clr_cc2 |
|
ACC_UDMA1 |
pmem_tran_ack9 |
3 |
ADVANCED_TIMER11 |
dma2tim_clr_cc3 |
|
ACC_UDMA1 |
pmem_tran_ack10 |
3 |
ADVANCED_TIMER11 |
dma2tim_clr_cc4 |
|
ACC_UDMA1 |
pmem_tran_ack4 |
4 |
ADVANCED_TIMER12 |
dma2tim_clr_com |
|
ACC_UDMA1 |
pmem_tran_ack5 |
4 |
ADVANCED_TIMER12 |
dma2tim_clr_trg |
|
ACC_UDMA1 |
pmem_tran_ack6 |
4 |
ADVANCED_TIMER12 |
dma2tim_clr_uev |
|
ACC_UDMA1 |
pmem_tran_ack7 |
4 |
ADVANCED_TIMER12 |
dma2tim_clr_cc1 |
|
ACC_UDMA1 |
pmem_tran_ack8 |
4 |
ADVANCED_TIMER12 |
dma2tim_clr_cc2 |
|
ACC_UDMA1 |
pmem_tran_ack9 |
4 |
ADVANCED_TIMER12 |
dma2tim_clr_cc3 |
|
ACC_UDMA1 |
pmem_tran_ack10 |
4 |
ADVANCED_TIMER12 |
dma2tim_clr_cc4 |
|
ACC_UDMA1 |
pmem_tran_ack4 |
5 |
ADVANCED_TIMER13 |
dma2tim_clr_com |
|
ACC_UDMA1 |
pmem_tran_ack5 |
5 |
ADVANCED_TIMER13 |
dma2tim_clr_trg |
|
ACC_UDMA1 |
pmem_tran_ack6 |
5 |
ADVANCED_TIMER13 |
dma2tim_clr_uev |
|
ACC_UDMA1 |
pmem_tran_ack7 |
5 |
ADVANCED_TIMER13 |
dma2tim_clr_cc1 |
|
ACC_UDMA1 |
pmem_tran_ack8 |
5 |
ADVANCED_TIMER13 |
dma2tim_clr_cc2 |
|
ACC_UDMA1 |
pmem_tran_ack9 |
5 |
ADVANCED_TIMER13 |
dma2tim_clr_cc3 |
|
ACC_UDMA1 |
pmem_tran_ack10 |
5 |
ADVANCED_TIMER13 |
dma2tim_clr_cc4 |
|
ACC_UDMA1 |
pmem_tran_ack4 |
6 |
ADVANCED_TIMER14 |
dma2tim_clr_com |
|
ACC_UDMA1 |
pmem_tran_ack5 |
6 |
ADVANCED_TIMER14 |
dma2tim_clr_trg |
|
ACC_UDMA1 |
pmem_tran_ack6 |
6 |
ADVANCED_TIMER14 |
dma2tim_clr_uev |
|
ACC_UDMA1 |
pmem_tran_ack7 |
6 |
ADVANCED_TIMER14 |
dma2tim_clr_cc1 |
|
ACC_UDMA1 |
pmem_tran_ack8 |
6 |
ADVANCED_TIMER14 |
dma2tim_clr_cc2 |
|
ACC_UDMA1 |
pmem_tran_ack9 |
6 |
ADVANCED_TIMER14 |
dma2tim_clr_cc3 |
|
ACC_UDMA1 |
pmem_tran_ack10 |
6 |
ADVANCED_TIMER14 |
dma2tim_clr_cc4 |
|
ACC_UDMA1 |
pmem_tran_ack4 |
7 |
ADVANCED_TIMER15 |
dma2tim_clr_com |
|
ACC_UDMA1 |
pmem_tran_ack5 |
7 |
ADVANCED_TIMER15 |
dma2tim_clr_trg |
|
ACC_UDMA1 |
pmem_tran_ack6 |
7 |
ADVANCED_TIMER15 |
dma2tim_clr_uev |
|
ACC_UDMA1 |
pmem_tran_ack7 |
7 |
ADVANCED_TIMER15 |
dma2tim_clr_cc1 |
|
ACC_UDMA1 |
pmem_tran_ack8 |
7 |
ADVANCED_TIMER15 |
dma2tim_clr_cc2 |
|
ACC_UDMA1 |
pmem_tran_ack9 |
7 |
ADVANCED_TIMER15 |
dma2tim_clr_cc3 |
|
ACC_UDMA1 |
pmem_tran_ack10 |
7 |
ADVANCED_TIMER15 |
dma2tim_clr_cc4 |
FLT_UDMA
FLT_UDMA 主要是为 flt_macc 这个加速器搬移数据，具有 3 个外设访问通道，其控制器如 FLT_UDMA 结构图 所示。
FLT_UDMA 结构图
其外设连接关系如 flt_udma连接表 所示。
SRC_IP |
SRC_SGL |
SRC_BIT |
DST_IP |
DST_SGL |
DST_BIT |
FLT_MACC0 |
dma_xwreq |
FLT_UDMA |
pmem_tran_req0 |
0 |
|
FLT_UDMA |
pmem_tran_ack0 |
0 |
FLT_MACC0 |
dma_xwack |
|
FLT_MACC0 |
dma_rreq |
FLT_UDMA |
pmem_tran_req1 |
0 |
|
FLT_UDMA |
pmem_tran_ack1 |
0 |
FLT_MACC0 |
dma_rack |
|
FLT_MACC0 |
dma_xwlen |
0 |
FLT_UDMA |
pmem_tran_req0_len |
0 |
FLT_MACC0 |
dma_xwlen |
1 |
FLT_UDMA |
pmem_tran_req0_len |
1 |
FLT_MACC0 |
dma_xwlen |
2 |
FLT_UDMA |
pmem_tran_req0_len |
2 |
FLT_MACC0 |
dma_xwlen |
3 |
FLT_UDMA |
pmem_tran_req0_len |
3 |
FLT_MACC0 |
dma_rlen |
0 |
FLT_UDMA |
pmem_tran_req1_len |
0 |
FLT_MACC0 |
dma_rlen |
1 |
FLT_UDMA |
pmem_tran_req1_len |
1 |
FLT_MACC0 |
dma_rlen |
2 |
FLT_UDMA |
pmem_tran_req1_len |
2 |
FLT_MACC0 |
dma_rlen |
3 |
FLT_UDMA |
pmem_tran_req1_len |
3 |
DCMI0 |
pssi_dma_req |
FLT_UDMA |
pmem_tran_req2 |
0 |
|
FLT_UDMA |
pmem_tran_ack2 |
0 |
DCMI0 |
pssi_dma_ack |
|
DCMI0 |
pssi_dma_len |
0 |
FLT_UDMA |
pmem_tran_req2_len |
0 |
DCMI0 |
pssi_dma_len |
1 |
FLT_UDMA |
pmem_tran_req2_len |
1 |
DCMI0 |
pssi_dma_len |
2 |
FLT_UDMA |
pmem_tran_req2_len |
2 |
DCMI0 |
pssi_dma_len |
3 |
FLT_UDMA |
pmem_tran_req2_len |
3 |