NMSIS-Core  Version 1.2.0
NMSIS-Core support for Nuclei processor-based devices
Functions
Signed MSW 32x32 Multiply and Add Instructions
Intrinsic Functions for SIMD Instructions » Partial-SIMD Data Processing Instructions

Signed MSW 32x32 Multiply and Add Instructions. More...

Functions

__STATIC_FORCEINLINE long __RV_KMMAC (long t, long a, long b)
 KMMAC (SIMD Saturating MSW Signed Multiply Word and Add) More...
 
__STATIC_FORCEINLINE long __RV_KMMAC_U (long t, long a, long b)
 KMMAC.u (SIMD Saturating MSW Signed Multiply Word and Add with Rounding) More...
 
__STATIC_FORCEINLINE long __RV_KMMSB (long t, long a, long b)
 KMMSB (SIMD Saturating MSW Signed Multiply Word and Subtract) More...
 
__STATIC_FORCEINLINE long __RV_KMMSB_U (long t, long a, long b)
 KMMSB.u (SIMD Saturating MSW Signed Multiply Word and Subtraction with Rounding) More...
 
__STATIC_FORCEINLINE long __RV_KWMMUL (long a, long b)
 KWMMUL (SIMD Saturating MSW Signed Multiply Word & Double) More...
 
__STATIC_FORCEINLINE long __RV_KWMMUL_U (long a, long b)
 KWMMUL.u (SIMD Saturating MSW Signed Multiply Word & Double with Rounding) More...
 
__STATIC_FORCEINLINE long __RV_SMMUL (long a, long b)
 SMMUL (SIMD MSW Signed Multiply Word) More...
 
__STATIC_FORCEINLINE long __RV_SMMUL_U (long a, long b)
 SMMUL.u (SIMD MSW Signed Multiply Word with Rounding) More...
 

Detailed Description

Signed MSW 32x32 Multiply and Add Instructions.

there are 8 Signed MSW 32x32 Multiply and Add Instructions

Function Documentation

◆ __RV_KMMAC()

__STATIC_FORCEINLINE long __RV_KMMAC ( long  t,
long  a,
long  b 
)

KMMAC (SIMD Saturating MSW Signed Multiply Word and Add)

Type: SIMD

Syntax:

KMMAC Rd, Rs1, Rs2
KMMAC.u Rd, Rs1, Rs2

Purpose:
Multiply the signed 32-bit integer elements of two registers and add the most significant 32-bit results with the signed 32-bit integer elements of a third register. The addition results are saturated first and then written back to the third register. The .u form performs an additional rounding up operation on the multiplication results before adding the most significant 32-bit part of the results.

Description:
This instruction multiplies the signed 32-bit elements of Rs1 with the signed 32-bit elements of Rs2 and adds the most significant 32-bit multiplication results with the signed 32-bit elements of Rd. If the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The results after saturation are written to Rd. The .u form of the instruction additionally rounds up the most significant 32-bit of the 64-bit multiplication results by adding a 1 to bit 31 of the results.

Operations:

Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
if (`.u` form) {
Round[x][32:0] = Mres[x][63:31] + 1;
res[x] = Rd.W[x] + Round[x][32:1];
} else {
res[x] = Rd.W[x] + Mres[x][63:32];
}
if (res[x] > (2^31)-1) {
res[x] = (2^31)-1;
OV = 1;
} else if (res[x] < -2^31) {
res[x] = -2^31;
OV = 1;
}
Rd.W[x] = res[x];
for RV32: x=0
for RV64: x=1...0
Parameters
[in]tlong type of value stored in t
[in]along type of value stored in a
[in]blong type of value stored in b
Returns
value stored in long type

Definition at line 3406 of file core_feature_dsp.h.

3407 {
3408  __ASM volatile("kmmac %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
3409  return t;
3410 }

References __ASM.

◆ __RV_KMMAC_U()

__STATIC_FORCEINLINE long __RV_KMMAC_U ( long  t,
long  a,
long  b 
)

KMMAC.u (SIMD Saturating MSW Signed Multiply Word and Add with Rounding)

Type: SIMD

Syntax:

KMMAC Rd, Rs1, Rs2
KMMAC.u Rd, Rs1, Rs2

Purpose:
Multiply the signed 32-bit integer elements of two registers and add the most significant 32-bit results with the signed 32-bit integer elements of a third register. The addition results are saturated first and then written back to the third register. The .u form performs an additional rounding up operation on the multiplication results before adding the most significant 32-bit part of the results.

Description:
This instruction multiplies the signed 32-bit elements of Rs1 with the signed 32-bit elements of Rs2 and adds the most significant 32-bit multiplication results with the signed 32-bit elements of Rd. If the addition result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The results after saturation are written to Rd. The .u form of the instruction additionally rounds up the most significant 32-bit of the 64-bit multiplication results by adding a 1 to bit 31 of the results.

Operations:

Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
if (`.u` form) {
Round[x][32:0] = Mres[x][63:31] + 1;
res[x] = Rd.W[x] + Round[x][32:1];
} else {
res[x] = Rd.W[x] + Mres[x][63:32];
}
if (res[x] > (2^31)-1) {
res[x] = (2^31)-1;
OV = 1;
} else if (res[x] < -2^31) {
res[x] = -2^31;
OV = 1;
}
Rd.W[x] = res[x];
for RV32: x=0
for RV64: x=1...0
Parameters
[in]tlong type of value stored in t
[in]along type of value stored in a
[in]blong type of value stored in b
Returns
value stored in long type

Definition at line 3467 of file core_feature_dsp.h.

3468 {
3469  __ASM volatile("kmmac.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
3470  return t;
3471 }

References __ASM.

◆ __RV_KMMSB()

__STATIC_FORCEINLINE long __RV_KMMSB ( long  t,
long  a,
long  b 
)

KMMSB (SIMD Saturating MSW Signed Multiply Word and Subtract)

Type: SIMD

Syntax:

KMMSB Rd, Rs1, Rs2
KMMSB.u Rd, Rs1, Rs2

Purpose:
Multiply the signed 32-bit integer elements of two registers and subtract the most significant 32-bit results from the signed 32-bit elements of a third register. The subtraction results are written to the third register. The .u form performs an additional rounding up operation on the multiplication results before subtracting the most significant 32-bit part of the results.

Description:
This instruction multiplies the signed 32-bit elements of Rs1 with the signed 32-bit elements of Rs2 and subtracts the most significant 32-bit multiplication results from the signed 32-bit elements of Rd. If the subtraction result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The results after saturation are written to Rd. The .u form of the instruction additionally rounds up the most significant 32-bit of the 64-bit multiplication results by adding a 1 to bit 31 of the results.

Operations:

Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
if (`.u` form) {
Round[x][32:0] = Mres[x][63:31] + 1;
res[x] = Rd.W[x] - Round[x][32:1];
} else {
res[x] = Rd.W[x] - Mres[x][63:32];
}
if (res[x] > (2^31)-1) {
res[x] = (2^31)-1;
OV = 1;
} else if (res[x] < -2^31) {
res[x] = -2^31;
OV = 1;
}
Rd.W[x] = res[x];
for RV32: x=0
for RV64: x=1...0
Parameters
[in]tlong type of value stored in t
[in]along type of value stored in a
[in]blong type of value stored in b
Returns
value stored in long type

Definition at line 4047 of file core_feature_dsp.h.

4048 {
4049  __ASM volatile("kmmsb %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
4050  return t;
4051 }

References __ASM.

◆ __RV_KMMSB_U()

__STATIC_FORCEINLINE long __RV_KMMSB_U ( long  t,
long  a,
long  b 
)

KMMSB.u (SIMD Saturating MSW Signed Multiply Word and Subtraction with Rounding)

Type: SIMD

Syntax:

KMMSB Rd, Rs1, Rs2
KMMSB.u Rd, Rs1, Rs2

Purpose:
Multiply the signed 32-bit integer elements of two registers and subtract the most significant 32-bit results from the signed 32-bit elements of a third register. The subtraction results are written to the third register. The .u form performs an additional rounding up operation on the multiplication results before subtracting the most significant 32-bit part of the results.

Description:
This instruction multiplies the signed 32-bit elements of Rs1 with the signed 32-bit elements of Rs2 and subtracts the most significant 32-bit multiplication results from the signed 32-bit elements of Rd. If the subtraction result is beyond the Q31 number range (-2^31 <= Q31 <= 2^31-1), it is saturated to the range and the OV bit is set to 1. The results after saturation are written to Rd. The .u form of the instruction additionally rounds up the most significant 32-bit of the 64-bit multiplication results by adding a 1 to bit 31 of the results.

Operations:

Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
if (`.u` form) {
Round[x][32:0] = Mres[x][63:31] + 1;
res[x] = Rd.W[x] - Round[x][32:1];
} else {
res[x] = Rd.W[x] - Mres[x][63:32];
}
if (res[x] > (2^31)-1) {
res[x] = (2^31)-1;
OV = 1;
} else if (res[x] < -2^31) {
res[x] = -2^31;
OV = 1;
}
Rd.W[x] = res[x];
for RV32: x=0
for RV64: x=1...0
Parameters
[in]tlong type of value stored in t
[in]along type of value stored in a
[in]blong type of value stored in b
Returns
value stored in long type

Definition at line 4107 of file core_feature_dsp.h.

4108 {
4109  __ASM volatile("kmmsb.u %0, %1, %2" : "+r"(t) : "r"(a), "r"(b));
4110  return t;
4111 }

References __ASM.

◆ __RV_KWMMUL()

__STATIC_FORCEINLINE long __RV_KWMMUL ( long  a,
long  b 
)

KWMMUL (SIMD Saturating MSW Signed Multiply Word & Double)

Type: SIMD

Syntax:

KWMMUL Rd, Rs1, Rs2
KWMMUL.u Rd, Rs1, Rs2

Purpose:
Multiply the signed 32-bit integer elements of two registers, shift the results left 1-bit, saturate, and write the most significant 32-bit results to a register. The .u form additionally rounds up the multiplication results from the most signification discarded bit.

Description:
This instruction multiplies the 32-bit elements of Rs1 with the 32-bit elements of Rs2. It then shifts the multiplication results one bit to the left and takes the most significant 32-bit results. If the shifted result is greater than 2^31-1, it is saturated to 2^31-1 and the OV flag is set to 1. The final element result is written to Rd. The 32-bit elements of Rs1 and Rs2 are treated as signed integers. The .u form of the instruction additionally rounds up the 64-bit multiplication results by adding a 1 to bit 30 before the shift and saturation operations.

Operations:

if ((0x80000000 != Rs1.W[x]) | (0x80000000 != Rs2.W[x])) {
Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
if (`.u` form) {
Round[x][33:0] = Mres[x][63:30] + 1;
Rd.W[x] = Round[x][32:1];
} else {
Rd.W[x] = Mres[x][62:31];
}
} else {
Rd.W[x] = 0x7fffffff;
OV = 1;
}
for RV32: x=0
for RV64: x=1...0
Parameters
[in]along type of value stored in a
[in]blong type of value stored in b
Returns
value stored in long type

Definition at line 5647 of file core_feature_dsp.h.

5648 {
5649  long result;
5650  __ASM volatile("kwmmul %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
5651  return result;
5652 }

References __ASM.

◆ __RV_KWMMUL_U()

__STATIC_FORCEINLINE long __RV_KWMMUL_U ( long  a,
long  b 
)

KWMMUL.u (SIMD Saturating MSW Signed Multiply Word & Double with Rounding)

Type: SIMD

Syntax:

KWMMUL Rd, Rs1, Rs2
KWMMUL.u Rd, Rs1, Rs2

Purpose:
Multiply the signed 32-bit integer elements of two registers, shift the results left 1-bit, saturate, and write the most significant 32-bit results to a register. The .u form additionally rounds up the multiplication results from the most signification discarded bit.

Description:
This instruction multiplies the 32-bit elements of Rs1 with the 32-bit elements of Rs2. It then shifts the multiplication results one bit to the left and takes the most significant 32-bit results. If the shifted result is greater than 2^31-1, it is saturated to 2^31-1 and the OV flag is set to 1. The final element result is written to Rd. The 32-bit elements of Rs1 and Rs2 are treated as signed integers. The .u form of the instruction additionally rounds up the 64-bit multiplication results by adding a 1 to bit 30 before the shift and saturation operations.

Operations:

if ((0x80000000 != Rs1.W[x]) | (0x80000000 != Rs2.W[x])) {
Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
if (`.u` form) {
Round[x][33:0] = Mres[x][63:30] + 1;
Rd.W[x] = Round[x][32:1];
} else {
Rd.W[x] = Mres[x][62:31];
}
} else {
Rd.W[x] = 0x7fffffff;
OV = 1;
}
for RV32: x=0
for RV64: x=1...0
Parameters
[in]along type of value stored in a
[in]blong type of value stored in b
Returns
value stored in long type

Definition at line 5703 of file core_feature_dsp.h.

5704 {
5705  long result;
5706  __ASM volatile("kwmmul.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
5707  return result;
5708 }

References __ASM.

◆ __RV_SMMUL()

__STATIC_FORCEINLINE long __RV_SMMUL ( long  a,
long  b 
)

SMMUL (SIMD MSW Signed Multiply Word)

Type: SIMD

Syntax:

SMMUL Rd, Rs1, Rs2
SMMUL.u Rd, Rs1, Rs2

Purpose:
Multiply the 32-bit signed integer elements of two registers and write the most significant 32-bit results to the corresponding 32-bit elements of a register. The .u form performs an additional rounding up operation on the multiplication results before taking the most significant 32-bit part of the results.

Description:
This instruction multiplies the 32-bit elements of Rs1 with the 32-bit elements of Rs2 and writes the most significant 32-bit multiplication results to the corresponding 32-bit elements of Rd. The 32-bit elements of Rs1 and Rs2 are treated as signed integers. The .u form of the instruction rounds up the most significant 32-bit of the 64-bit multiplication results by adding a 1 to bit 31 of the results.

  • For smmul/RV32 instruction, it is an alias to mulh/RV32 instruction.

Operations:

Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
if (`.u` form) {
Round[x][32:0] = Mres[x][63:31] + 1;
Rd.W[x] = Round[x][32:1];
} else {
Rd.W[x] = Mres[x][63:32];
}
for RV32: x=0
for RV64: x=1...0
Parameters
[in]along type of value stored in a
[in]blong type of value stored in b
Returns
value stored in long type

Definition at line 8765 of file core_feature_dsp.h.

8766 {
8767  long result;
8768  __ASM volatile("smmul %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
8769  return result;
8770 }

References __ASM.

◆ __RV_SMMUL_U()

__STATIC_FORCEINLINE long __RV_SMMUL_U ( long  a,
long  b 
)

SMMUL.u (SIMD MSW Signed Multiply Word with Rounding)

Type: SIMD

Syntax:

SMMUL Rd, Rs1, Rs2
SMMUL.u Rd, Rs1, Rs2

Purpose:
Multiply the 32-bit signed integer elements of two registers and write the most significant 32-bit results to the corresponding 32-bit elements of a register. The .u form performs an additional rounding up operation on the multiplication results before taking the most significant 32-bit part of the results.

Description:
This instruction multiplies the 32-bit elements of Rs1 with the 32-bit elements of Rs2 and writes the most significant 32-bit multiplication results to the corresponding 32-bit elements of Rd. The 32-bit elements of Rs1 and Rs2 are treated as signed integers. The .u form of the instruction rounds up the most significant 32-bit of the 64-bit multiplication results by adding a 1 to bit 31 of the results.

  • For smmul/RV32 instruction, it is an alias to mulh/RV32 instruction.

Operations:

Mres[x][63:0] = Rs1.W[x] * Rs2.W[x];
if (`.u` form) {
Round[x][32:0] = Mres[x][63:31] + 1;
Rd.W[x] = Round[x][32:1];
} else {
Rd.W[x] = Mres[x][63:32];
}
for RV32: x=0
for RV64: x=1...0
Parameters
[in]along type of value stored in a
[in]blong type of value stored in b
Returns
value stored in long type

Definition at line 8816 of file core_feature_dsp.h.

8817 {
8818  long result;
8819  __ASM volatile("smmul.u %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
8820  return result;
8821 }

References __ASM.

__ASM
#define __ASM
Pass information from the compiler to the assembler.
Definition: nmsis_gcc.h:55