NMSIS-Core
Version 1.2.0
NMSIS-Core support for Nuclei processor-based devices
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Signed 16-bit Multiply 64-bit Add/Subtract Instructions. More...
Functions | |
__STATIC_FORCEINLINE long long | __RV_SMAL (long long a, unsigned long b) |
SMAL (Signed Multiply Halfs & Add 64-bit) More... | |
__STATIC_FORCEINLINE long long | __RV_SMALBB (long long t, unsigned long a, unsigned long b) |
SMALBB (Signed Multiply Bottom Halfs & Add 64-bit) More... | |
__STATIC_FORCEINLINE long long | __RV_SMALBT (long long t, unsigned long a, unsigned long b) |
SMALBT (Signed Multiply Bottom Half & Top Half & Add 64-bit) More... | |
__STATIC_FORCEINLINE long long | __RV_SMALTT (long long t, unsigned long a, unsigned long b) |
SMALTT (Signed Multiply Top Halfs & Add 64-bit) More... | |
__STATIC_FORCEINLINE long long | __RV_SMALDA (long long t, unsigned long a, unsigned long b) |
SMALDA (Signed Multiply Two Halfs and Two Adds 64-bit) More... | |
__STATIC_FORCEINLINE long long | __RV_SMALXDA (long long t, unsigned long a, unsigned long b) |
SMALXDA (Signed Crossed Multiply Two Halfs and Two Adds 64-bit) More... | |
__STATIC_FORCEINLINE long long | __RV_SMALDS (long long t, unsigned long a, unsigned long b) |
SMALDS (Signed Multiply Two Halfs & Subtract & Add 64-bit) More... | |
__STATIC_FORCEINLINE long long | __RV_SMALDRS (long long t, unsigned long a, unsigned long b) |
SMALDRS (Signed Multiply Two Halfs & Reverse Subtract & Add 64- bit) More... | |
__STATIC_FORCEINLINE long long | __RV_SMALXDS (long long t, unsigned long a, unsigned long b) |
SMALXDS (Signed Crossed Multiply Two Halfs & Subtract & Add 64- bit) More... | |
__STATIC_FORCEINLINE long long | __RV_SMSLDA (long long t, unsigned long a, unsigned long b) |
SMSLDA (Signed Multiply Two Halfs & Add & Subtract 64-bit) More... | |
__STATIC_FORCEINLINE long long | __RV_SMSLXDA (long long t, unsigned long a, unsigned long b) |
SMSLXDA (Signed Crossed Multiply Two Halfs & Add & Subtract 64- bit) More... | |
Signed 16-bit Multiply 64-bit Add/Subtract Instructions.
Signed 16-bit Multiply with 64-bit Add/Subtract Instructions.
there is Signed 16-bit Multiply 64-bit Add/Subtract Instructions
there are 10 Signed 16-bit Multiply with 64-bit Add/Subtract Instructions
__STATIC_FORCEINLINE long long __RV_SMAL | ( | long long | a, |
unsigned long | b | ||
) |
SMAL (Signed Multiply Halfs & Add 64-bit)
Type: Partial-SIMD
Syntax:
Purpose:
Multiply the signed bottom 16-bit content of the 32-bit elements of a register with the top 16-bit content of the same 32-bit elements of the same register, and add the results with a 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back to another even/odd pair of registers (RV32) or a register (RV64).
RV32 Description:
This instruction multiplies the bottom 16-bit content of the lower 32-bit of Rs2 with the top 16-bit content of the lower 32-bit of Rs2 and adds the result with the 64-bit value of an even/odd pair of registers specified by Rs1(4,1). The 64-bit addition result is written back to an even/odd pair of registers specified by Rd(4,1). The 16-bit values of Rs2, and the 64-bit value of the Rs1(4,1) register- pair are treated as signed integers. Rx(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd 2d+1
register of the pair contains the high 32-bit of the operand and the even 2d
register of the pair contains the low 32-bit of the operand.
RV64 Description:
This instruction multiplies the bottom 16-bit content of the 32-bit elements of Rs2 with the top 16-bit content of the same 32-bit elements of Rs2 and adds the results with the 64-bit value of Rs1. The 64- bit addition result is written back to Rd. The 16-bit values of Rs2, and the 64-bit value of Rs1 are treated as signed integers.
Operations:
[in] | a | long long type of value stored in a |
[in] | b | unsigned long type of value stored in b |
Definition at line 7397 of file core_feature_dsp.h.
References __ASM.
__STATIC_FORCEINLINE long long __RV_SMALBB | ( | long long | t, |
unsigned long | a, | ||
unsigned long | b | ||
) |
SMALBB (Signed Multiply Bottom Halfs & Add 64-bit)
Type: DSP (64-bit Profile)
Syntax:
Purpose:
Multiply the signed 16-bit content of the 32-bit elements of a register with the 16-bit content of the corresponding 32-bit elements of another register and add the results with a 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back to the register-pair (RV32) or the register (RV64).
RV32 Description:
For the SMALBB
instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2. For the SMALBT
instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2. For the SMALTT
instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2. The multiplication result is added with the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers. Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd 2d+1
register of the pair contains the high 32-bit of the operand and the even 2d
register of the pair contains the low 32-bit of the operand.
RV64 Description:
For the SMALBB
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. For the SMALBT
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. For the SMALTT
instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. The multiplication results are added with the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.
Operations:
[in] | t | long long type of value stored in t |
[in] | a | unsigned long type of value stored in a |
[in] | b | unsigned long type of value stored in b |
Definition at line 7480 of file core_feature_dsp.h.
References __ASM.
__STATIC_FORCEINLINE long long __RV_SMALBT | ( | long long | t, |
unsigned long | a, | ||
unsigned long | b | ||
) |
SMALBT (Signed Multiply Bottom Half & Top Half & Add 64-bit)
Type: DSP (64-bit Profile)
Syntax:
Purpose:
Multiply the signed 16-bit content of the 32-bit elements of a register with the 16-bit content of the corresponding 32-bit elements of another register and add the results with a 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back to the register-pair (RV32) or the register (RV64).
RV32 Description:
For the SMALBB
instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2. For the SMALBT
instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2. For the SMALTT
instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2. The multiplication result is added with the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers. Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd 2d+1
register of the pair contains the high 32-bit of the operand and the even 2d
register of the pair contains the low 32-bit of the operand.
RV64 Description:
For the SMALBB
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. For the SMALBT
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. For the SMALTT
instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. The multiplication results are added with the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.
Operations:
[in] | t | long long type of value stored in t |
[in] | a | unsigned long type of value stored in a |
[in] | b | unsigned long type of value stored in b |
Definition at line 7562 of file core_feature_dsp.h.
References __ASM.
__STATIC_FORCEINLINE long long __RV_SMALDA | ( | long long | t, |
unsigned long | a, | ||
unsigned long | b | ||
) |
SMALDA (Signed Multiply Two Halfs and Two Adds 64-bit)
Type: DSP (64-bit Profile)
Syntax:
Purpose:
Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then adds the two 32-bit results and the 64-bit value of an even/odd pair of registers together.
RV32 Description:
For the SMALDA
instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2 and then adds the result to the result of multiplying the top 16-bit content of Rs1 with the top 16-bit content of Rs2 with unlimited precision. For the SMALXDA
instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit content of Rs2 and then adds the result to the result of multiplying the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2 with unlimited precision. The result is added to the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64- bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64- bit value of the register-pair are treated as signed integers. Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd 2d+1
register of the pair contains the high 32-bit of the operand and the even 2d
register of the pair contains the low 32-bit of the operand.
RV64 Description:
For the SMALDA
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32- bit elements of Rs2 with unlimited precision. For the SMALXDA
instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2 with unlimited precision. The results are added to the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.
Operations:
[in] | t | long long type of value stored in t |
[in] | a | unsigned long type of value stored in a |
[in] | b | unsigned long type of value stored in b |
Definition at line 7728 of file core_feature_dsp.h.
References __ASM.
__STATIC_FORCEINLINE long long __RV_SMALDRS | ( | long long | t, |
unsigned long | a, | ||
unsigned long | b | ||
) |
SMALDRS (Signed Multiply Two Halfs & Reverse Subtract & Add 64- bit)
Type: DSP (64-bit Profile)
Syntax:
Purpose:
Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then perform a subtraction operation between the two 32-bit results. Then add the subtraction result to the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back to the register-pair.
RV32 Description:
For the SMALDS
instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of Rs1 with the top 16-bit content of Rs2. For the SMALDRS
instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2. For the SMALXDS
instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of Rs1 with the bottom 16-bit content of Rs2. The subtraction result is then added to the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers. Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd 2d+1
register of the pair contains the high 32-bit of the operand and the even 2d
register of the pair contains the low 32-bit of the operand.
RV64 Description:
For the SMALDS
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. For the SMALDRS
instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. For the SMALXDS
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. The subtraction results are then added to the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.
Operations:
[in] | t | long long type of value stored in t |
[in] | a | unsigned long type of value stored in a |
[in] | b | unsigned long type of value stored in b |
Definition at line 7994 of file core_feature_dsp.h.
References __ASM.
__STATIC_FORCEINLINE long long __RV_SMALDS | ( | long long | t, |
unsigned long | a, | ||
unsigned long | b | ||
) |
SMALDS (Signed Multiply Two Halfs & Subtract & Add 64-bit)
Type: DSP (64-bit Profile)
Syntax:
Purpose:
Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then perform a subtraction operation between the two 32-bit results. Then add the subtraction result to the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back to the register-pair.
RV32 Description:
For the SMALDS
instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of Rs1 with the top 16-bit content of Rs2. For the SMALDRS
instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2. For the SMALXDS
instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of Rs1 with the bottom 16-bit content of Rs2. The subtraction result is then added to the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers. Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd 2d+1
register of the pair contains the high 32-bit of the operand and the even 2d
register of the pair contains the low 32-bit of the operand.
RV64 Description:
For the SMALDS
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. For the SMALDRS
instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. For the SMALXDS
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. The subtraction results are then added to the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.
Operations:
[in] | t | long long type of value stored in t |
[in] | a | unsigned long type of value stored in a |
[in] | b | unsigned long type of value stored in b |
Definition at line 7903 of file core_feature_dsp.h.
References __ASM.
__STATIC_FORCEINLINE long long __RV_SMALTT | ( | long long | t, |
unsigned long | a, | ||
unsigned long | b | ||
) |
SMALTT (Signed Multiply Top Halfs & Add 64-bit)
Type: DSP (64-bit Profile)
Syntax:
Purpose:
Multiply the signed 16-bit content of the 32-bit elements of a register with the 16-bit content of the corresponding 32-bit elements of another register and add the results with a 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back to the register-pair (RV32) or the register (RV64).
RV32 Description:
For the SMALBB
instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2. For the SMALBT
instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2. For the SMALTT
instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2. The multiplication result is added with the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers. Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd 2d+1
register of the pair contains the high 32-bit of the operand and the even 2d
register of the pair contains the low 32-bit of the operand.
RV64 Description:
For the SMALBB
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. For the SMALBT
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. For the SMALTT
instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. The multiplication results are added with the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.
Operations:
[in] | t | long long type of value stored in t |
[in] | a | unsigned long type of value stored in a |
[in] | b | unsigned long type of value stored in b |
Definition at line 7644 of file core_feature_dsp.h.
References __ASM.
__STATIC_FORCEINLINE long long __RV_SMALXDA | ( | long long | t, |
unsigned long | a, | ||
unsigned long | b | ||
) |
SMALXDA (Signed Crossed Multiply Two Halfs and Two Adds 64-bit)
Type: DSP (64-bit Profile)
Syntax:
Purpose:
Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then adds the two 32-bit results and the 64-bit value of an even/odd pair of registers together.
RV32 Description:
For the SMALDA
instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2 and then adds the result to the result of multiplying the top 16-bit content of Rs1 with the top 16-bit content of Rs2 with unlimited precision. For the SMALXDA
instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit content of Rs2 and then adds the result to the result of multiplying the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2 with unlimited precision. The result is added to the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64- bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64- bit value of the register-pair are treated as signed integers. Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd 2d+1
register of the pair contains the high 32-bit of the operand and the even 2d
register of the pair contains the low 32-bit of the operand.
RV64 Description:
For the SMALDA
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32- bit elements of Rs2 with unlimited precision. For the SMALXDA
instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and then adds the result to the result of multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2 with unlimited precision. The results are added to the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.
Operations:
[in] | t | long long type of value stored in t |
[in] | a | unsigned long type of value stored in a |
[in] | b | unsigned long type of value stored in b |
Definition at line 7812 of file core_feature_dsp.h.
References __ASM.
__STATIC_FORCEINLINE long long __RV_SMALXDS | ( | long long | t, |
unsigned long | a, | ||
unsigned long | b | ||
) |
SMALXDS (Signed Crossed Multiply Two Halfs & Subtract & Add 64- bit)
Type: DSP (64-bit Profile)
Syntax:
Purpose:
Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then perform a subtraction operation between the two 32-bit results. Then add the subtraction result to the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The addition result is written back to the register-pair.
RV32 Description:
For the SMALDS
instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of Rs1 with the top 16-bit content of Rs2. For the SMALDRS
instruction, it multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of Rs1 with the bottom 16-bit content of Rs2. For the SMALXDS
instruction, it multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of Rs1 with the bottom 16-bit content of Rs2. The subtraction result is then added to the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64-bit addition result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers. Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd 2d+1
register of the pair contains the high 32-bit of the operand and the even 2d
register of the pair contains the low 32-bit of the operand.
RV64 Description:
For the SMALDS
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. For the SMALDRS
instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of multiplying the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. For the SMALXDS
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2 and then subtracts the result from the result of multiplying the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2. The subtraction results are then added to the 64-bit value of Rd. The 64-bit addition result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.
Operations:
[in] | t | long long type of value stored in t |
[in] | a | unsigned long type of value stored in a |
[in] | b | unsigned long type of value stored in b |
Definition at line 8085 of file core_feature_dsp.h.
References __ASM.
__STATIC_FORCEINLINE long long __RV_SMSLDA | ( | long long | t, |
unsigned long | a, | ||
unsigned long | b | ||
) |
SMSLDA (Signed Multiply Two Halfs & Add & Subtract 64-bit)
Type: DSP (64-bit Profile)
Syntax:
Purpose:
Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then subtracts the two 32-bit results from the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The subtraction result is written back to the register-pair.
RV32 Description:
For the SMSLDA
instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit content Rs2 and multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2. For the SMSLXDA
instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit content of Rs2 and multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2. The two multiplication results are subtracted from the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64-bit subtraction result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers. Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd 2d+1
register of the pair contains the high 32-bit of the result and the even 2d
register of the pair contains the low 32-bit of the result.
RV64 Description:
For the SMSLDA
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. For the SMSLXDA
instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. The four multiplication results are subtracted from the 64-bit value of Rd. The 64-bit subtraction result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.
Operations:
[in] | t | long long type of value stored in t |
[in] | a | unsigned long type of value stored in a |
[in] | b | unsigned long type of value stored in b |
Definition at line 9099 of file core_feature_dsp.h.
References __ASM.
__STATIC_FORCEINLINE long long __RV_SMSLXDA | ( | long long | t, |
unsigned long | a, | ||
unsigned long | b | ||
) |
SMSLXDA (Signed Crossed Multiply Two Halfs & Add & Subtract 64- bit)
Type: DSP (64-bit Profile)
Syntax:
Purpose:
Do two signed 16-bit multiplications from the 32-bit elements of two registers; and then subtracts the two 32-bit results from the 64-bit value of an even/odd pair of registers (RV32) or a register (RV64). The subtraction result is written back to the register-pair.
RV32 Description:
For the SMSLDA
instruction, it multiplies the bottom 16-bit content of Rs1 with the bottom 16-bit content Rs2 and multiplies the top 16-bit content of Rs1 with the top 16-bit content of Rs2. For the SMSLXDA
instruction, it multiplies the top 16-bit content of Rs1 with the bottom 16-bit content of Rs2 and multiplies the bottom 16-bit content of Rs1 with the top 16-bit content of Rs2. The two multiplication results are subtracted from the 64-bit value of an even/odd pair of registers specified by Rd(4,1). The 64-bit subtraction result is written back to the register-pair. The 16-bit values of Rs1 and Rs2, and the 64-bit value of the register-pair are treated as signed integers. Rd(4,1), i.e., d, determines the even/odd pair group of the two registers. Specifically, the register pair includes register 2d and 2d+1. The odd 2d+1
register of the pair contains the high 32-bit of the result and the even 2d
register of the pair contains the low 32-bit of the result.
RV64 Description:
For the SMSLDA
instruction, it multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the top 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. For the SMSLXDA
instruction, it multiplies the top 16-bit content of the 32-bit elements of Rs1 with the bottom 16-bit content of the 32-bit elements of Rs2 and multiplies the bottom 16-bit content of the 32-bit elements of Rs1 with the top 16-bit content of the 32-bit elements of Rs2. The four multiplication results are subtracted from the 64-bit value of Rd. The 64-bit subtraction result is written back to Rd. The 16-bit values of Rs1 and Rs2, and the 64-bit value of Rd are treated as signed integers.
Operations:
[in] | t | long long type of value stored in t |
[in] | a | unsigned long type of value stored in a |
[in] | b | unsigned long type of value stored in b |
Definition at line 9181 of file core_feature_dsp.h.
References __ASM.