.. _timer: TIMER Unit Introduction ======================= .. warning:: For latest version of Nuclei ISA Spec since 2022, please get it from AE of Nuclei System Technology. This online version is out of date. TIMER Overview -------------- The Timer Unit (TIMER for short) is used to generate the Timer Interrupt and Software Interrupt in Nuclei processor core. TIMER Registers --------------- The TIMER is a memory-mapped unit: - For the base address of the TIMER unit, please refer to the specific datasheet of the Nuclei processor core. - Registers and the corresponding offset in the TIMER unit are shown in :ref:`table_timer_1`. .. _table_timer_1: .. table:: The address offset of registers in the TIMER unit :widths: auto +--------+--------------+--------------+--------------+--------------+ | Offset | Perm\ | Register | Default | Function | | | ission/Width | Name | Value | Description | +========+==============+==============+==============+==============+ | 0x0 | RW/4B | mtime_lo | 0x00000000 | Reflect the | | | | | | lower 32-bit | | | | | | value of | | | | | | mtime. | | | | | | | | | | | | Shadow copy | | | | | | of MTIME in | | | | | | CLINT mode | +--------+--------------+--------------+--------------+--------------+ | 0x4 | RW/4B | mtime_hi | 0x00000000 | Reflect the | | | | | | upper 32-bit | | | | | | value of | | | | | | mtime. | | | | | | | | | | | | Shadow copy | | | | | | of MTIME in | | | | | | CLINT mode | +--------+--------------+--------------+--------------+--------------+ | 0x8 | RW/4B | mtimecmp_lo | 0xFFFFFFFF | Set the | | | | | | lower 32-bit | | | | | | value of | | | | | | mtimecmp. | | | | | | | | | | | | Shadow copy | | | | | | of MTIMECMP | | | | | | for Hart-0 | | | | | | in CLINT | | | | | | mode | +--------+--------------+--------------+--------------+--------------+ | 0xC | RW/4B | mtimecmp_hi | 0xFFFFFFFF | Set the | | | | | | upper 32-bit | | | | | | value of | | | | | | mtimecmp. | | | | | | | | | | | | Shadow copy | | | | | | of MTIMECMP | | | | | | for Hart-0 | | | | | | in CLINT | | | | | | mode | +--------+--------------+--------------+--------------+--------------+ | 0xFF0 | RW/4B | msftrst | 0x00000000 | Generate | | | | | | soft-reset | | | | | | request. | +--------+--------------+--------------+--------------+--------------+ | 0xFF8 | RW/4B | mtimectl | 0x00000000 | Control some | | | | | | features of | | | | | | the time | | | | | | counter. | +--------+--------------+--------------+--------------+--------------+ | 0xFFC | RW/4B | msip | 0x00000000 | Generate the | | | | | | Software | | | | | | Interrupt. | | | | | | | | | | | | Shadow copy | | | | | | of MSIP for | | | | | | Hart-0 in | | | | | | CLINT mode | +--------+--------------+--------------+--------------+--------------+ | 0x1000 | RW/4B | MSIP for | 0x00000000 | Software | | | | Hart-0 | | Interrupt | | | | | | for Hart-0 | | | | | | in CLINT | | | | | | mode | +--------+--------------+--------------+--------------+--------------+ | 0x1004 | RW/4B | MSIP for | 0x00000000 | Software | | | | Hart-1 | | Interrupt | | | | | | for Hart-1 | | | | | | in CLINT | | | | | | mode | +--------+--------------+--------------+--------------+--------------+ | 0x1008 | RW/4B | MSIP for | 0x00000000 | Software | | | | Hart-2 | | Interrupt | | | | | | for Hart-2 | | | | | | in CLINT | | | | | | mode | +--------+--------------+--------------+--------------+--------------+ | 0x100c | RW/4B | MSIP for | 0x00000000 | Software | | | | Hart-3 | | Interrupt | | | | | | for Hart-3 | | | | | | in CLINT | | | | | | mode | +--------+--------------+--------------+--------------+--------------+ | 0x5000 | RW/8B | MTIMECMP for | 0x00000000 | MTIMECMP for | | | | Hart-0 | | Hart-0 in | | | | | | CLINT mode | +--------+--------------+--------------+--------------+--------------+ | 0x5008 | RW/8B | MTIMECMP for | 0x00000000 | MTIMECMP for | | | | Hart-1 | | Hart-1 in | | | | | | CLINT mode | +--------+--------------+--------------+--------------+--------------+ | 0x5010 | RW/8B | MTIMECMP for | 0x00000000 | MTIMECMP for | | | | Hart-2 | | Hart-2 in | | | | | | CLINT mode | +--------+--------------+--------------+--------------+--------------+ | 0x5018 | RW/8B | MTIMECMP for | 0x00000000 | MTIMECMP for | | | | Hart-3 | | Hart-3 in | | | | | | CLINT mode | +--------+--------------+--------------+--------------+--------------+ | 0xCFF8 | RW/8B | MTIME | 0x00000000 | MTIME in | | | | | | CLINT mode | +--------+--------------+--------------+--------------+--------------+ .. note:: - Registers in the TIMER unit only support aligned read and write access with WORD size. - The address space range of registers in the TIMER unit is 0x000 ~ 0xFFF. The value in the address other than the registers listed in the above table is constant 0. - The functionality of each register is described in the following sections. Time Counter Register mtime ~~~~~~~~~~~~~~~~~~~~~~~~~~~ The key points of TIMER unit are as follows: - The TIMER implements a 64-bit register mtime, which is composed of {mtime_hi, mtime_lo}. This register reflects the value of the 64-bit timer. The timer is turned on by default, so it will always count after reset. - The increment frequency of the counter is controlled by the core's input signal mtime_toggle_a or core's always-on clock input core_aon_clk. Please refer to the specific datasheet of the Nuclei processor core for details about this signal. .. _timer_gen_timeirq: Generate the Timer Interrupt through mtime and mtimecmp ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The TIMER unit can be used to generate the timer interrupt. The key points are as follows: - The TIMER implements a 64-bit register mtimecmp, which is composed of {mtimecmp_hi, mtimecmp_lo}. This register is used as the comparison value of the timer. If the value of mtime is greater than the value of mtimecmp, then a timer interrupt is generated. - If mtimectl.CMPCLREN is set as 1, then the mtime will be automatically cleared to zero when the value of mtime is greater than the value of mtimecmp, and then restart counting from zero. - If mtimectl.CMPCLREN is set as 0, then the mtime will always increments normally. The software can clear the timer interrupt by overwriting the value of mtimecmp or mtime (so that the value of mtimecmp is greater than the value of mtime). .. note:: the timer interrupt is connected to the ECLIC unit as unified interrupt management. Please see :ref:`eclic` for details of ECLIC. Control the Timer Counter through mtimectl ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The register mtimectl is implemented to control the behaviors of timer counting , as shown in :ref:`table_timer_2`. .. _table_timer_2: .. table:: mtimectl bit fields :widths: 45,20,55,40,150 ============ ==== ================ ========= ============================================================== Field Bits Permission | Default Description | Value **Reserved** 7:1 | Readable, N/A Reserved, ties to 0 | Write Ignored **CLKSRC** 2 RW 0 | Select the source of increment frequency. | If this field is 1, then the increment frequency | is frequency of *core_aon_clk*, otherwise the | increment frequency is controlled by *mtime_toggle_a*, | please refer to the specific datasheet of the | Nuclei processor core for details about this signal. **CMPCLREN** 1 RW 0 | Control the timer count to clear-to-zero or not. | If this field is 1, then the *mtime* register will be | cleared to zero after generated timer interrupt, | otherwise it increments normally. **TIMESTOP** 0 RW 0 | Control the timer count or pause. If this field is 1, | then the timer is paused, otherwise it increments normally. ============ ==== ================ ========= ============================================================== .. note:: If CMPCLREN is enabled, the timer interupt request will be a pulse request. In this case, timer interrupt should be set to edge-trigger mode. .. _timer_gen_swirq: Generating the Software Interrupt through msip ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The TIMER unit can be used to generate the Software Interrupt. The register msip is implemented in the TIMER unit as shown in :ref:`table_timer_3`, only the least significant bit of msip is an effective bit. This bit is used to generate the software interrupt directly: - The software generates the software interrupt by writing 1 to the msip register; - The software clears the software interrupt by writing 0 to the msip register. .. note:: the soft interrupt is connected to the ECLIC unit as unified interrupt management. Please see :ref:`eclic` for details of ECLIC. .. _table_timer_3: .. table:: msip bit fields :widths: 40,20,40,40,150 ============ ==== ================ ============= =================================================== Field Bits Permission Default Value Description **Reserved** 31:1 | Readable, N/A Reserved, ties to 0 | write ignored **MSIP** 0 RW 0 This bit is used to generate the software interrupt ============ ==== ================ ============= =================================================== Generating the Soft-Reset Request ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The TIMER unit can be used to generate the Soft-Reset request. The register msftrst is implemented in the TIMER unit as shown in :ref:`table_timer_4`, only the least significant bit of msftrst is an effective bit. This bit is used to generate the Soft-Reset request directly: - The software generates the Soft-Reset request by writing **0x80000a5f** to the **msftrst** register. Requiring to write such a complicate number is to avoid the random mis-operation of software writing. - The most significant bit of **msftrst** can only be clear by reset, so if the SoC reset the core in respond to Soft-Reset request, then msftrst register will be reset (and cleared to zero). .. note:: The core's output signal sysrstreq (active high) is used to carry out the **Soft-Reset** request, the SoC should reset the core *(assert core_reset_n, not por_reset_n)* in respond to the request. Please refer to the specific datasheet of the Nuclei processor core for details about the signals *sysrstreq, core_reset_n and por_reset_n*. .. _table_timer_4: .. table:: msftrst bit fields :widths: 40,20,40,40,150 ============ ==== =============== ============= =================================================== Field Bits Permission Default Value Description **MSFTRST** 31 RW 0 This bit is used to generate the Soft-Reset Request **Reserved** 30:0 | Readable, N/A Reserved, ties to 0 | write ignored ============ ==== =============== ============= ===================================================