.. _pmp:

PMP Introduction
================

PMP Overview
------------

Nuclei processor core can optionally support the PMP (Physical Memory
Protection) features, which is part of RISC-V standard privileged
architecture specification.

User can easily get the original copy from |nuclei_user_center|
or from other public channels.

PMP Specific Features to Nuclei Core
------------------------------------

In order to simplify the hardware implementation, or there are some
features are intrinsically hardware implementation relevant, Nuclei
processor core have some PMP specific features, which is detailed at
next sections.

Configurable PMP Entries Number
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

RISC-V standard privileged architecture specified the number of PMP
entries up to 16, but in the real hardware the PMP entries is limited.
Nuclei processor core have the PMP entries number configurable at the
build time, please refer to the specific datasheet of the Nuclei
processor core.

For those PMP CSR registers relevant to non-existed PMP entries, they
are tied to zeros. For example, if the PMP Entries Number is
configurable to 8, then the PMP entry 9 ~ 16 relevant CSR registers are
tied to zeros.

No support to TOR mode in A field of pmpcfg<x> registers
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

RISC-V standard privileged architecture specified 4 types of modes in A
field of pmpcfg<x> registers. But to simplify the hardware
implementations, Nuclei processor core does not support the TOR mode in
A field of pmpcfg<x> registers.

If the software try to write A filed to set it as TOR mode, then it will
be forcedly written as zero values in this field.

Corner cases for Boundary Crossing 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Since the RISC-V standard privileged architecture specified the PMP
regions as naturally aligned power-of-2 regions (NAPOT), but in the
Nuclei processor core hardware implementations, there might be unaligned
access crossing the boundary, which is handled in this way:

-  If it is normal load/store instructions:

   -  If the processor core is configured to not support the unaligned
      memory access, then it will trigger address misaligned exception.

   -  If the processor core is configured to support the unaligned
      memory access, then hardware will break the unaligned access into
      multiple byte or half-word aligned memory accesses (called
      micro-operations), each micro-opertation will be checked with PMP,
      if violated PMP permission, it will trigger Load or Store access
      fault exception, and the exception is imprecise.

-  If it is AMO/LR/SC instructions:

   -  Since the RISC-V standard privileged architecture specified
      AMO/LR/SC instructions definitely not support the unaligned memory
      access, hence it will trigger address misaligned exception.

-  If it is the instruction fetching, since the processor core will
   always break the instruction fetching as the aligned memory access
   (e.g., 32bits or 64bits aligned), each aligned memory access will be
   checked with PMP, if violated PMP permission, it will trigger
   instruction access fault exception, and the exception is precise.