.. _exception: Exception Handling in Nuclei processor core =========================================== Exception Overview ------------------ Exception is that the processor core suddenly encounters an abnormal situation when executing the program instruction stream, and aborts execution of the current program, and turns to handle the exception instead. The key points are as follows: - The "abnormal event" which the core encounters is called an exception. An exception is caused by an internal event in the core or an event during the execution of the program, such as a hardware failure, a program failure, or the execution of a special system call instruction. In short, it is a core-internal issue. - When the exception is taken, the core will enter the exception handler program. Exception Masking ----------------- According to the RISC-V architecture, exception cannot be masked, which means if the core encounters an exception, it must stop current execution and turns to handle the exception. .. _exception_priority: Priority of Exception --------------------- It is possible that the core encounters multiple exceptions at the same time, so exceptions also have priority. The priority of the exception is defined in RISC-V standard privileged architecture, please refer to RISC-V standard privileged architecture for more details. Entering Exception Handling Mode -------------------------------- Taking an exception, hardware behaviors of the Nuclei processor core are shown in :ref:`figure_exception_1`. Note that the following operations are done simultaneously in one cycle: - Stop the execution of the current program, and start from the PC address defined by the CSR mtvec. Update the CSR registers: mcause, mepc, mtval, and mstatus. Update the Privilege Mode. - These behaviors are following RISC-V standard privileged architecture specification. This document will not repeat its content, please refer to RISC-V standard privileged architecture specification for more details. - Update the Machine Sub-Mode of the core. - This is unique in Nuclei processor core, and will be detailed in the following section. .. _figure_exception_1: .. figure:: /asserts/media/image003.png :width: 80 % :align: center :alt: The overall process of exception The overall process of exception Update the Machine Sub-Mode ~~~~~~~~~~~~~~~~~~~~~~~~~~~ The Machine Sub-Mode of the Nuclei processor core is indicated in the msubm.TYP filed in real time. When the core takes an exception, the Machine Sub-Mode will be updated to exception handling mode, so: - The filed msubm.TYP is updated to exception handling mode, as shown in :ref:`figure_exception_2`, to reflect the current Machine Sub-Mode is "Exception Handling Mode". - The value of msubm.PTYP will be updated to the value of msub.TYP before taking the exception, as shown in :ref:`figure_exception_2`. The value of msubm.PTYP will be used to restore the value of msubm.PTYP after exiting the exception handler. .. _figure_exception_2: .. figure:: /asserts/media/image005.png :width: 60 % :align: center :alt: The CSR mstatus and msubm updating when enter/exit the exception The CSR mstatus and msubm updating when enter/exit the exception Exit the Exception Handling Mode -------------------------------- After handling the exception, the core needs to exit from the exception handler eventually. Since the exception is handling in Machine Mode, the software has to execute mret to exit the exception handler. The hardware behavior of the processor after executing mret instruction is as shown in :ref:`figure_exception_3`. Note that the following hardware behaviors are done simultaneously in one cycle: - Stop the execution of the current program, and start from the PC address defined by the CSR mepc. Update the CSR mstatus. And update the Privilege Mode. - These behaviors are following RISC-V standard privileged architecture specification. This document will not repeat its content, please refer to RISC-V standard privileged architecture specification for more details. - Update the Machine Sub-Mode of the core. - This is unique in Nuclei processor core, and will be detailed in the following section. .. _figure_exception_3: .. figure:: /asserts/media/image006.png :width: 70 % :align: center :alt: The overall process of exiting an exception The overall process of exiting an exception Update the Machine Sub-Mode ~~~~~~~~~~~~~~~~~~~~~~~~~~~ The value of msubm.TYP indicates the Machine Sub-Mode of the Nuclei processor core in real time. After executing the mret instruction, the hardware will automatically restore the core's Machine Sub-Mode by the value of msubm.PTYP: - Taking an exception, the value of msubm.PTYP is updated to the Machine Sub-Mode before taking the exception. After executing the mret instruction, the hardware will automatically restore the Machine Sub-Mode using the value of msubm.PTYP, as shown in :ref:`figure_exception_2`. Through this mechanism, the Machine Sub-Mode of the core is restored to the same mode before taking the exception. Exception Service Routine ------------------------- When the core takes one exception, it starts to execute the program starting at the address defined by mtvec, and this program is usually an exception service routine. The program can decide to jump further to the specified exception service routine by querying the exception code in the CSR mcause. For example, if the exception code in mcause is 0x2, which indicates that this exception is caused by an illegal instruction, then it can jump to the specific handler for illegal instruction fault. Note: Since there is no hardware to save and restore the execution context automatically when take or exit an exception, so the software needs to explicitly use the instruction (in assembly language) for context saving and restoring. Exception Nesting ----------------- Please see :ref:`nesting` for more details.