.. _core_csr: Nuclei processor core CSRs Descriptions ======================================= .. _core_csr_overview: .. warning:: For latest version of Nuclei ISA Spec since 2022, please get it from AE of Nuclei System Technology. This online version is out of date. CSR Overview ------------ CSR (Control and Status Registers) is part of RISC-V standard privileged architecture. Basically, Nuclei processor core are following and compatible to RISC-V standard CSR definitions, but there are some additions and enhancements to the original standard spec. To respect the RISC-V standard, this document may not repeat the contents of original RISC-V standard, but will highlight the additions and enhancements of Nuclei defined. .. _core_csr_nuclei_csr_list: Nuclei processor core CSRs List ------------------------------- :ref:`table_core_csr_1` describes the CSRs in the Nuclei processor core. In this CSRs List, there are RISC-V standard CSRs and customized CSRs in the Nuclei processor core. .. _table_core_csr_1: .. table:: CSR supported in the Nuclei processor core :widths: 40,30,30,50,200 +------------+---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | Type | Address | R & W | Name | Description | +------------+---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | RISC-V || These CSRs are following RISC-V standard privileged architecture specification. | | | Standard || This document will not repeat its content here, | | | CSRs || please refer to RISC-V standard privileged architecture specification for more details. | +------------+---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ || Nuclei | 0x307 | MRW | mtvt | ECLIC Interrupt Vector Table Base Address | || Customized+---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ || CSRs | Ox345 | MRW | mnxti | Used to enable taking the next interrupt and return the entry address of the next interrupt handler. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x346 | MRO | mintstatus | Current Interrupt Levels | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x348 | MRW | mscratchcsw | Scratch swap register for privileged mode. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x349 | MRW | mscratchcswl | Scratch swap register for interrupt levels. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x320 | MRW | mcountinhibit | Customized register used to control the on & off of counters | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7c0 | MRW | milm_ctl | Enable/Disable the ILM address space. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7c1 | MRW | mdlm_ctl | Enable/Disable the DLM address space. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7c2 | MRW | mecc_code | ECC code injection register, can be used to simulate ECC error | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7c3 | MRO | mnvec | Customized register used to indicate the NMI handler entry address | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7c4 | MRW | msubm | Customized register storing current trap type and the previous trap type before trapped. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7c9 | MRW | mdcause | Customized register storing current trap's detailed cause. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7ca | MRW | mcache_ctl | Customized register to control the cache features. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7d0 | MRW | mmisc_ctl | Customized register controlling the selection of the NMI Handler Entry Address. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7d6 | MRW | msavestatus | Customized register storing the value of mstatus. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7d7 | MRW | msaveepc1 | Customized register storing the value of mepc for the first-level preempted NMI or Exception. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7d8 | MRW | msavecause1 | Customized register storing the value of mcause for the first-level preempted NMI or Exception. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7d9 | MRW | msaveepc2 | Customized register storing the value of mepc for the second-level preempted NMI or Exception. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7da | MRW | msavecause2 | Customized register storing the value of mcause for the second-level preempted NMI or Exception. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7dd | MRW | mtlb_ctl | TLB control register | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7de | MRW | mecc_lock | To lock ECC configure registers, then all the ECC related CSRs cannot be modified, unless by reset | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7eb | MRW | pushmsubm | Customized register used to push the value of msubm into the stack memory. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7ec | MRW | mtvt2 | Customized register used to indicate the common handler entry address of non-vectored interrupts. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7ed | MRW | jalmnxti | | Customized register used to enable the ECLIC interrupt. | | | | | | | The read operation of this register will take the next interrupt, return the entry address of next | | | | | | | interrupt handler, and jump to the corresponding handler at the same time. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7ee | MRW | pushmcause | Customized register used to push the value of mcause into the stack memory. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7ef | MRW | pushmepc | Customized register used to push the value of mepc into the stack memory. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7f0 | MRO | mppicfg_info | PPI configuration information. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x7f1 | MRO | mfiocfg_info | FIO configuration information. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x811 | MRW | sleepvalue | Customized register used to indicate the WFI sleep mode. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x812 | MRW | txevt | Customized register used to send an event. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0x810 | MRW | wfe | Customized register used to control the WFE mode. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0xfc0 | MRO | micfg_info | ILM and I-Cache configuration information. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0xfc1 | MRO | mdcfg_info | DLM and D-Cache configuration information. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0xfc2 | MRO | mcfg_info | Processor configuration information. | | +---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ | | 0xfc3 | MRO | mtlbcfg_info | TLB configuration info. | +------------+---------+-------+---------------+-------------------------------------------------------------------------------------------------------+ .. note:: * MRW -- Machine Mode Readable/Writeable * MRO -- Machine Mode Read-Only * URW -- User Mode Readable/Writeable * URO -- User Mode Read-Only .. _core_csr_nuclei_core_access: Accessibility of CSRs in the Nuclei processor core --------------------------------------------------- The CSRs accessibility in the Nuclei processor core: - Read or write to a non-existent CSR will raise an **Illegal Instruction Exception**. - Write to RO CSRs will raise an **Illegal Instruction Exception**. .. note:: According to the RISC-V standard, the URO registers like cycle, cycleh, time, timeh, instret, instreth are special, the read accessibility of which are determined by the corresponding field in mcounteren. - Access the higher privilege mode CSR raise an **Illegal Instruction Exception**. For example, in User Mode accessing to MRO or MRW CSRs will raise an **Illegal Instruction Exception**. .. _core_csr_nuclei_riscv_standard_csr: RISC-V Standard CSRs Supported in the Nuclei processor core ----------------------------------------------------------- These CSRs are following RISC-V standard privileged architecture specification. This document will not repeat its content here, please refer to RISC-V standard privileged architecture specification for more details. This chapter only introduces the RISC-V Standard CSRs supported in the Nuclei processor core, but those CSRs who also have some unique differences implemented in Nuclei processor core. .. _core_csr_mie: mie ~~~ In Nuclei processor core, the format and features of CSR mie is same as RISC-V standard, please refer to RISC-V standard privileged architecture specification for more details of CSR mie. But note: the mie CSR is not effective when the core is in the CLIC mode, and the readout of mie is always 0, the writing is ignored. .. _core_csr_mip: mip ~~~ In Nuclei processor core, the format and features of CSR mip is same as RISC-V standard, please refer to RISC-V standard privileged architecture specification for more details of CSR mip. But note: the mip CSR is not effective when the core is in the CLIC mode, and the readout of mip is always 0, the writing is ignored. .. _core_csr_mhartid: mhartid ~~~~~~~ In Nuclei processor core, the format and features of CSR |csr_mhartid| is same as RISC-V standard, please refer to RISC-V standard privileged architecture specification for more details of CSR mhartid. In the Nuclei processor core, hart ID is controlled by input signal *core_mhartid*. .. note:: According to RISC-V architecture, we must ensure exactly one hart runs some code and so require one hart to have a known hart ID of 0. .. _core_csr_mepc: mepc ~~~~ mepc register is used to save PC value before enter to exception, which is used as exception return address. .. note:: * When the processor enters an exception, the mepc register is updated at the same time to reflect the PC value of the instruction currently encountering the exception. * It is worth noting that although the mepc register is automatically updated by the hardware when an exception occurs, the mepc register itself is also a (in Machine Mode) readable and writable register, so the software can also directly write this register to modify its value. .. _core_csr_mtvec: mtvec ~~~~~ The mtvec register holds the entry address of the interrupt and exception handler. Field of mtvec register is shown in :ref:`table_core_csr_2`. - When mtvec holds the exception entry address: - The value of the address field must always be aligned on a 4-byte boundary. - When mtvec holds the interrupt entry address: - When *mtvec.MODE != 6'b000011*, the processor uses the CLINT interrupt mode. - When *mtvec.MODE = 6'b000011*, the processor uses the CLIC interrupt mode. - See :ref:`interrupt_non-vectored_process_mode` for more information about non-vectored mode interrupt handler entry address. - See :ref:`interrupt_vectored_process_mode` for more information about vectored mode interrupt handler entry address. .. _table_core_csr_2: .. table:: mtvec register :widths: 40,30,200 ========= ======= ======================================== **Field** **Bit** **Description** **ADDR** 31:6 mtvec address **MODE** 5:0 - MODE field determine interrupt mode: - 000011: CLIC interrupt mode - Others: CLINT interrupt mode ========= ======= ======================================== .. _core_csr_mcause: mcause ~~~~~~ The mcause is written with a code indicating the reason that caused the trap. The format and features of CSR mcause is basically same as RISC-V standard, please refer to RISC-V standard privileged architecture specification for more details. But in CLIC mode for Nuclei processor core, there some additional fields added to support CLIC mode interrupt handling. The mcause register is formatted as shown in :ref:`table_core_csr_3`. .. _table_core_csr_3: .. table:: mcause register :widths: 50,30,110,150 ============= ======= =================================== ==================================================== **Field** **Bit** **Description** **Note** **INTERRUPT** 31 Current trap type: - 0: Exception or NMI - 1: Interrupt **MINHV** 30 | Indicate processer is reading | Note: These fields are only effect in CLIC mode. | interrupt vector table | When in CLINT mode, these field is masked read | as zero, write ignored. **MPP** 29:28 privilege mode before interrupt **MPIE** 27 Interrupt enable before interrupt **Reserved** 26:24 Reserved 0 **MPIL** 23:16 Previous interrupt level **Reserved** 15:12 Reserved 0 **EXCCODE** 11:0 Exception/Interrupt Encoding ============= ======= =================================== ==================================================== .. note:: - In CLIC mode, the mstatus.MPIE and mstatus.MPP are the mirror images of mcause.MPIE and mcause.MPP. - The mcause.EXCCODE of NMI can be 0x1 or 0xfff, the value is controlled by |csr_mmisc_ctl|. .. _core_csr_mcycle: .. _core_csr_mcycleh: .. _core_csr_mcycle_mcycleh: mcycle and mcycleh ~~~~~~~~~~~~~~~~~~ The RISC-V architecture defines a 64-bits width cycle counter which indicates how many cycles the processor has executed. Whenever the processor is working, the counter will increase automatically. The mcycle register records the lower 32-bits of counter and mcycleh records the higher 32-bits. The format and features of CSR mcycle/mcycleh are basically same as RISC-V standard, please refer to RISC-V standard privileged architecture specification for more details. But in Nuclei processor core, considering the counter increases the power consumption, there is an extra bit in the customized CSR mcountinhibit that can pause the counter to save power when users don't need to monitor the performance through the counter. See |csr_mcountinhibit| for more information. .. _core_csr_minstret: .. _core_csr_minstreth: .. _core_csr_minstret_minstreth: minstret and minstreth ~~~~~~~~~~~~~~~~~~~~~~ The RISC-V architecture defines a 64-bits width counter which records how many instructions have been executed successfully. The minstret register records the low 32-bits of counter and minstreth records the high 32-bits. The format and features of CSR minstret/minstreth are basically same as RISC-V standard, please refer to RISC-V standard privileged architecture specification for more details. But in Nuclei processor core, considering the counter has power consumption, there is an extra bit in the customized CSR mcountinhibit that can turn off the counter to save power when users don't need to learn the performance through the counter. See |csr_mcountinhibit| for more information. .. _core_csr_nuclei_customized_csr: Nuclei processor core Customized CSR ------------------------------------ This section introduces customized CSRs in the Nuclei processor core. .. _core_csr_mcountinhibit: mcountinhibit ~~~~~~~~~~~~~ The mcountinhibit register controls the counting of mcycle/mcycleh and minstret/minstreth registers to save power when users don't need them. See |csr_mcycle| and |csr_minstret| for more information. .. _table_core_csr_4: .. table:: mcountinhibit register :widths: 50,30,160 ============ ======= ================================================= **Field** **Bit** **Description** **Reserved** 31:3 Reserved 0 **IR** 2 When IR is 1, minstret/minstreth is stop counting **Reserved** 1 Reserved 0 **CY** 0 When CY is 1, mcycle/mcycleh is is stop counting ============ ======= ================================================= .. _core_csr_milm_ctl: milm_ctl ~~~~~~~~ The milm_ctl register controls the ILM (Instruction Local Memory) address space to enable or disable it based on user's application scenarios. .. _table_core_csr_milm_ctl: .. table:: milm_ctl register :widths: 100,100,400 ============== ================================ =================================================================================================== **Field** **Bit** **Description** ============== ================================ =================================================================================================== **ILM_BPA** | XLEN-1:10 | The base physical address of ILM. It has to be aligned to multiple of ILM size. | (Read-Only) | For example, to set up an instruction local memory of size 4KB starting at address 12KB (0x3000), | we simply program ILM_BPA to 0xC (take the upper 22 bits of 0x3000). **Reserved** 9:1 Reserved 0 **ILM_ENABLE** | 0 Instruction Local Memory enable bit. | (Writeable in UX class cores) - 0: ILM is disabled. - 1: ILM is enabled. (default) ============== ================================ =================================================================================================== .. note:: ILM can only be disabled in UX class core when MMU and ILM coexist. .. _core_csr_mdlm_ctl: mdlm_ctl ~~~~~~~~ The mdlm_ctl register controls the DLM (Data Local Memory) address space to enable or disable it based on user's application scenarios. .. _table_core_csr_mdlm_ctl: .. table:: mdlm_ctl register :widths: 100,100,400 ============== ================================ =================================================================================================== **Field** **Bit** **Description** ============== ================================ =================================================================================================== **DLM_BPA** | XLEN-1:10 | The base physical address of DLM. It has to be aligned to multiple of DLM size. | (Read-Only) | For example, to set up an instruction local memory of size 4KB starting at address 12KB (0x3000), | we simply program DLM_BPA to 0xC (take the upper 22 bits of 0x3000). **Reserved** 9:1 Reserved 0 **DLM_ENABLE** | 0 Data Local Memory enable bit. | (Writeable in UX class cores) - 0: DLM is disabled. - 1: DLM is enabled. (default) ============== ================================ =================================================================================================== .. note:: DLM can only be disabled in UX class core when MMU and DLM coexist. .. _core_csr_mnvec: mnvec ~~~~~ The Nuclei processor core customized CSR mnvec register holds the NMI entry address. In order to understand this register, please see :ref:`nmi` for more information. During a processor running a program, the program will be forced to jump into a new PC address when an NMI is triggered. The PC address is determined by mnvec. The value of mnvec is controlled by |csr_mmisc_ctl|. .. _core_csr_msubm: msubm ~~~~~ The Nuclei processor core customized CSR msubm register holds the current machine sub-mode and the machine sub-mode before the current trap. See :ref:`privileged_arch_nuclei_machine_submode` for more information. .. _table_core_csr_5: .. table:: msubm register :widths: 50,30,160 ============ ======= ========================================== **Field** **Bit** **Description** **Reserved** 31:10 Reserved 0 **PTYP** 9:8 Machine sub-mode before entering the trap: - 0: Normal machine mode - 1: Interrupt handling mode - 2: Exception handling mode - 3: NMI handling mode **TYP** 7:6 Current machine sub-mode: - 0: Normal machine mode - 1: Interrupt handling mode - 2: Exception handling mode - 3: NMI handling mode **Reserved** 5:0 Reserved 0 ============ ======= ========================================== .. _core_csr_mdcause: mdcause ~~~~~~~ Since there might be some exceptions share the same mcause.EXCCODE value. To further record the differences, Nuclei processor core customized CSR mdcause register to record the detailed information about the exception. .. _table_core_csr_6: .. table:: mdcause register :widths: 50,30,250 ============ ======= ================================================================================================= **Field** **Bit** **Description** **Reserved** 31: 2 Reserved 0 **mdcause** 1:0 Further record the detailed information about the exception. **When mcause.EXCCODE = 1 (Instruction access fault)** - 0: Reserved - 1: PMP permission violation - 2: Bus error - 3: Reserved **When mcause.EXCCODE = 5 (Load access fault)** - 0: Reserved - 1: PMP permission violation - 2: Bus error - 3: NICE extended long pipeline instruction return error. | **Note**: Although this error ideally is nothing to do with the Load access fault, | but they just shared the same mcause.EXCCODE to simplify the hardware implementation **When mcause.EXCCODE = 7 (Store/AMO access fault)** - 0: Reserved - 1: PMP permission violation - 2: Bus error - 3: Reserved ============ ======= ================================================================================================= .. _core_csr_mcache_ctl: mcache_ctl ~~~~~~~~~~ Nuclei processor core customized CSR mcache_ctl register to control the I-Cache and D-Cache features. .. _table_core_csr_7: .. table:: mcache_ctl register :widths: auto +--------------------+---------+-------------------------------------+ | **Field** | **Bit** | **Description** | +====================+=========+=====================================+ | **Reserved** | 31:21 | Reserved 0 | +--------------------+---------+-------------------------------------+ | **DC_RWDECC** | 20 | Controls diagnostic accesses of ECC | | | | codes of the D-Cache data rams | | | | through the mecc_code register. | | | | This bit can be turned on for | | | | injecting ECC errors to test the | | | | ECC handler. | | | | | | | | - 0: Disable diagnostic accesses | | | | of ECC codes | | | | | | | | - 1: Enable diagnostic accesses of | | | | ECC codes | | | | | | | | Notice: When D-Cache is not | | | | configured, this field is tied to | | | | 0. | +--------------------+---------+-------------------------------------+ | **DC_RWTECC** | 19 | Controls diagnostic accesses of ECC | | | | codes of the D-Cache tag rams | | | | through the mecc_code register. | | | | This bit can be turned on for | | | | injecting ECC errors to test the | | | | ECC handler. | | | | | | | | - 0: Disable diagnostic accesses | | | | of ECC codes | | | | | | | | - 1: Enable diagnostic accesses of | | | | ECC codes | | | | | | | | Notice: When D-Cache is not | | | | configured, this field is tied to | | | | 0. | +--------------------+---------+-------------------------------------+ | **DC_ECC_EXCP_EN** | 18 | D-Cache double bit ECC exception | | | | enable control: | | | | | | | | - 0: Disable double bit ECC | | | | exception | | | | | | | | - 1: Enable double bit ECC | | | | exception | | | | | | | | Notice: When D-Cache is not | | | | configured, this field is tied to | | | | 0. | +--------------------+---------+-------------------------------------+ | **DC_ECC_EN** | 17 | D-Cache ECC enable control: | | | | | | | | - 0: Disable ECC (default) | | | | | | | | - 1: Enable ECC | | | | | | | | Notice: When D-Cache is not | | | | configured, this field is tied to | | | | 0. | +--------------------+---------+-------------------------------------+ | **DC_EN** | 16 | - 0: D-Cache Disabled, default; | | | | | | | | - 1: D-Cache Enabled; | +--------------------+---------+-------------------------------------+ | **Reserved** | 15:6 | Reserved 0 | +--------------------+---------+-------------------------------------+ | **IC_RWDECC** | 5 | Controls diagnostic accesses of ECC | | | | codes of the I-Cache Data rams | | | | through the mecc_code register. | | | | This bit can be turned on for | | | | injecting ECC errors to test the | | | | ECC handler. | | | | | | | | - 0: Disable diagnostic accesses | | | | of ECC codes | | | | | | | | - 1: Enable diagnostic accesses of | | | | ECC codes | | | | | | | | Notice: When I-Cache is not | | | | configured, this field is tied to | | | | 0. | +--------------------+---------+-------------------------------------+ | **IC_RWTECC** | 4 | Controls diagnostic accesses of ECC | | | | codes of the I-Cache tag rams | | | | through the mecc_code register. | | | | This bit can be turned on for | | | | injecting ECC errors to test the | | | | ECC handler. | | | | | | | | - 0: Disable diagnostic accesses | | | | of ECC codes | | | | | | | | - 1: Enable diagnostic accesses of | | | | ECC codes | | | | | | | | Notice: When I-Cache is not | | | | configured, this field is tied to | | | | 0. | +--------------------+---------+-------------------------------------+ | **IC_ECC_EXCP_EN** | 3 | I-Cache double bit ECC exception | | | | enable control: | | | | | | | | - 0: Disable double bit ECC | | | | exception | | | | | | | | - 1: Enable double bit ECC | | | | exception | | | | | | | | Notice: When I-Cache is not | | | | configured, this field is tied to | | | | 0. | +--------------------+---------+-------------------------------------+ | **IC_ECC_EN** | 2 | I-Cache ECC enable control: | | | | | | | | - 0: Disable ECC (default) | | | | | | | | - 1: Enable ECC | | | | | | | | Notice: When I-Cache is not | | | | configured, this field is tied to | | | | 0. | +--------------------+---------+-------------------------------------+ | **IC_SCPD_MOD** | 1 | Scratchpad Mode Enable: | | | | | | | | - 0: I-Cache as the normal mode | | | | | | | | - 1: I-Cache as the Scratchpad | | | | mode. When under this mode, the | | | | Data SRAM of I-Cache will be | | | | reused and downgraded to memory | | | | mapped SRAM which can be | | | | accessed by instruction fetch | | | | and load/store access, like ILM | | | | and DLM, but called as | | | | Scratchpad here. Note: this mode | | | | only take effect when IC_EN bit | | | | is disabled by software. | | | | (default) | +--------------------+---------+-------------------------------------+ | **IC_EN** | 0 | I-Cache Enable: | | | | | | | | - 0: I-Cache disabled (default) | | | | | | | | - 1: I-Cache enabled | +--------------------+---------+-------------------------------------+ .. note:: Only when the I-Cache is disabled (IC_EN bit as 0) and scratchpad mode is enabled, i.e., mcache_ctl[1:0] is 2'b10, I-Cache really work as the Scratchpad. .. _core_csr_mmisc_ctl: mmisc_ctl ~~~~~~~~~ The Nuclei processor core customized CSR mmisc_ctl controls the value of mnvec and the mcause value of NMI, unaligned access enable/disable and BPU enable/disable. .. _table_core_csr_8: .. table:: mmisc_ctl register :widths: 100,40,400 ================= ======= ============================================================= **Field** **Bit** **Description** **Reserved** 31:10 Reserved 0 **NMI_CAUSE_FFF** 9 Control mnvec and mcause.EXCCODE of NMI: - | 0: The value of mnvec equals the PC address after reset, | mcause.EXCCODE of NMI is 0x1. - | 1: The value of mnvec is the same as the value of mtvec, | mcause.EXCCODE of NMI is 0xfff **UNALGN_ENABLE** 6 | Enable or Disable misaligned load/store access, if disabled, | accessing misaligned memory locations will trig an Address | Misaligned exception: - 0: Disable misaligned load/store access. - 1: Enable misaligned load/store access. | **Notice**: This field only takes effects for load/store | specified in I/F/D Extension, for load/store specified in A | Extension, misaligned accesses always trigger an | Address Misaligned exception. **Reserved** 5:4 Reserved 0 **BPU_ENABLE** 3 Enable or Disable the BPU Unit: - 0: Disable the BPU Unit. - 1: Enable the BPU Unit. | This bit is hard-wired to 0 if branch prediction unit that | cannot be disabled and enabled are not implemented. **Reserved** 8:0 Reserved 0 ================= ======= ============================================================= .. _core_csr_msavestatus: msavestatus ~~~~~~~~~~~ The msavestatus holds the value of mstatus and msubm which guarantee mstatus and msubm will not be flushed by NMI or exception. The msavestatus has two-stage stack, and supports up to 3-levels NMI/Exception state save. See :ref:`nesting` for more information. .. _table_core_csr_9: .. table:: msavestatus register :widths: 100,40,400 ============ ======= ====================================================================== **Field** **Bit** **Description** **Reserved** 31:16 Reserved 0 **PTYP2** 15:14 The trap type before taking the second-level NMI/Exception. **Reserved** 13:11 Reserved 0 **MPP2** 10:9 The privilege mode before taking the second-level NMI/Exception. **MPIE2** 8 The interrupt enable bit before taking the second-level NMI/Exception. **PTYP1** 7:6 The trap type before taking the first-level NMI/Exception. **Reserved** 5:3 Reserved 0 **MPP1** 2:1 The privilege mode before taking the second-level NMI/Exception. **MPIE1** 0 The interrupt enable bit before taking the second-level NMI/Exception. ============ ======= ====================================================================== .. _core_csr_msaveepc1: .. _core_csr_msaveepc2: .. _core_csr_msaveepc1_msaveepc2: msaveepc1 and msaveepc2 ~~~~~~~~~~~~~~~~~~~~~~~ msaveepc1 and msaveepc2 are registers of the first-level NMI/Exception status stack and the second-level NMI/Exception status stack, used to save the PC before the first-level NMI/Exception preemption and the second-level NMI/Exception preemption respectively. - **msaveepc2 <= msaveepc1 <= mepc <= interrupted PC <= NMI/exception PC** Executing the mret instruction, and the value of mcause.INTERRUPT is 0 (Such as NMI or exception), msaveepc1 and msaveepc2 are used to restore the PC through the first and second level NMI/Exception Status Stacks. - **msaveepc2 => msaveepc1 => mepc => PC** See :ref:`nesting` for more information. .. _core_csr_msavecause1: .. _core_csr_msavecause2: .. _core_csr_msavecause1_msavecause2: msavecause1 and msavecause2 ~~~~~~~~~~~~~~~~~~~~~~~~~~~ msavecause1 and msavecause2 are registers of the first-level NMI/Exception status stack and the second-level NMI/Exception status stack, used to save the mcause before the first-level NMI/Exception preemption and the second-level NMI/Exception preemption respectively. - **msavecause2 <= msavecause1 <= mcause <= NMI/exception cause** Executing the mret instruction, and the value of mcause.INTERRUPT is 0 (Such as NMI or exception), msavecause1 and msavecause2 are used to restore the mcause through the first and second level NMI/Exception Status Stacks. - **msavecause2 => msavecause1 => mcause** See :ref:`nesting` for more information. .. _core_csr_msavedcause1: .. _core_csr_msavedcause2: .. _core_csr_msavedcause1_msavedcause2: msavedcause1 and msavedcause2 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ msavedcause1 and msavedcause2 are registers of the first-level NMI/Exception status stack and the second-level NMI/Exception status stack, used to save the mdcause before the first-level NMI/Exception preemption and the second-level NMI/Exception preemption respectively. - **msavedcause2 <= msavedcause1 <= mdcause <= NMI/exception dcause** Executing the mret instruction, and the value of mcause.INTERRUPT is 0 (Such as NMI or exception), msavedcause1 and msavedcause2 are used to restore the mdcause through the first and second level NMI/Exception Status Stacks. - **msavedcause2 => msavedcause1 => mdcause** See :ref:`nesting` for more information. .. _core_csr_mtvt: mtvt ~~~~ This register is from the `CLIC draft`_ of RISC-V fast interrupt task group. The mtvt register holds the base address of interrupt vector table (in CLIC mode), and the base address is aligned at least 64-byte boundary. See :ref:`interrupt_eclic_vector_table` for more information. In order to improve the performance and reduce the gate count, the alignment of the base address in mtvt is determined by the actual number of interrupts, which is shown in the following table. .. _table_core_csr_10: .. table:: mtvt register :widths: 100,40,400 ==================== ============== Max interrupt number mtvt alignment 0 to 16 64-byte 17 to 32 128-byte 33 to 64 256-byte 65 to 128 512-byte 129 to 256 1KB 257 to 512 2KB 513 to 1024 4KB 1025 to 2048 8KB 2045 to 4096 16KB ==================== ============== .. _core_csr_mnxti: mnxti ~~~~~ This register is from the `CLIC draft`_ of RISC-V fast interrupt task group. The mnxti register(Next Interrupt Handler Address and Interrupt-Enable CSR)can be used by the software to service the next interrupt when it is in the same privilege mode, without incurring the full cost of an interrupt pipeline flush and context save/restore. The mnxti CSR is designed to be accessed using *CSRRSI/CSRRCI* instructions, where the value read is the next interrupt handler address and the write back updates the interrupt-enable status. .. note:: - If the next interrupt is not executed in the same privilege mode, the processor will take the next interrupt directly in a nested way, and mnxti only work when the next interrupt is in the same privilege mode. - The mnxti CSR instruction is not the same as normal CSR instructions, the return value is different. - The return value of mnxti CSR read instruction is shown below: - For the following situations, return 0 - No valid interrupt. - The highest priority interrupt is vectored. - When the interrupt non-vectored, return the interrupt entry address - The mnxti CSR write operation will update following register: - mnxti CSR register is a virtual register, i.e., the write operation will actually apply result on mstatus register, i.e., mstatus is the actual RMW(read-modify-write)operation target register. - The mcause.EXCCODE field will be updated to the value of the corresponding ID of the taken interrupt. - The mintstatus.MIL will be updated to current interrupt level. .. _core_csr_mintstatus: mintstatus ~~~~~~~~~~ This register is from the `CLIC draft`_ of RISC-V fast interrupt task group. The mintstatus register holds the active interrupt level for all the privilege mode. .. _table_core_csr_11: .. table:: minstatus register :widths: 100,40,400 ============ ======= ========================================== **Field** **Bit** **Description** **MIL** 31:24 The active interrupt level in machine mode **Reserved** 23: 8 Reserved 0 **UIL** 7:0 The active interrupt level in user mode ============ ======= ========================================== .. _core_csr_mtvt2: mtvt2 ~~~~~ mtvt2 is used to indicate the entry address of the common base handler shared by all ECLIC non-vectored interrupts. See more information about mtvt2 in :ref:`interrupt_non-vectored_feature_latency`. .. _table_core_csr_12: .. table:: mtvt2 register :widths: 100,40,400 ==================== ======= ========================================================================== **Field** **Bit** **Description** **CMMON-CODE-ENTRY** 31:2 | When mtvt2.MTVT2EN=1, this field determines the entry address | of interrupt common code in ECLIC non-vector mode. **Reserved** 1 Reserved 0 **MTVT2EN** 0 mtvt2 enable: - | 0: the entry address of interrupt common code in ECLIC | non-vector mode is determined by mtvec - | 1: the entry address of interrupt common code in ECLIC | non-vector mode is determined by mtvt2.COMMON-CODE-ENTRY ==================== ======= ========================================================================== .. _core_csr_jalmnxti: jalmnxti ~~~~~~~~ The Nuclei processor core customized CSR jalmnxti to reduce the delay for interrupt and accelerates interrupt tail-chaining. The jalmnxti included all functionality of mnxti, besides it also include enabling the interrupt, handling the next interrupt, jumping to the next interrupt entry address, and jumping to the interrupt handler. So, the jalmnxti can decrease the instruction numbers to speed up the interrupt handling and tail-chaining. See more information about |csr_mtvt2| in :ref:`interrupt_non-vectored_feature_latency`. .. _core_csr_pushmsubm: pushmsubm ~~~~~~~~~ The Nuclei processor core customized CSR pushmsubm provides a method to store the value of msubm in memory space which base address is SP with CSR instruction csrrwi. For example: ``csrrwi x0, PUSHMSUBM, 1`` This instruction stores the value of |csr_msubm| in **SP+1*4** address. .. _core_csr_pushmcause: pushmcause ~~~~~~~~~~ The Nuclei processor core customized CSR pushmcause provides a fast method to store the value of mcause in memory space which base address is SP with CSR instruction ``csrrwi``. See more information about |csr_mtvt2| in :ref:`interrupt_non-vectored_feature_latency`. For example: ``csrrwi x0, PUSHMCAUSE, 1`` This instruction stores the value of |csr_mcause| in **SP+1*4** address. .. _core_csr_pushmepc: pushmepc ~~~~~~~~ The Nuclei processor core customized CSR pushmepc provides a fast method to store the value of mepc in memory space which base address is SP with CSR instruction csrrwi. See more information about |csr_mtvt2| in :ref:`interrupt_non-vectored_feature_latency`. For example: ``csrrwi x0, PUSHMPEC, 1`` This instruction stores the value of mepc in **SP+1*4** address. .. _core_csr_mscratchcsw: mscratchcsw ~~~~~~~~~~~ This register is from the `CLIC draft`_ of RISC-V fast interrupt task group. The mscratchcsw register is useful to swap the value between the target register and mscratch when privilege mode change. Using a CSR read instruction to perform mscratchcsw, when the privilege mode is changed after taking an interrupt, following pseudo instruction operations are performed: .. code-block:: c :linenos: csrrw rd, mscratchcsw, rs1 // Pseudocode operation. if (mcause.mpp!=M-mode) { t = rs1; rd = mscratch; mscratch = t; } else { rd = rs1; // mscratch unchanged. } // Usual use: csrrw sp, mscratchcsw, sp When the processor takes an interrupt in a lower privilege mode, the processor enters a higher privilege mode to handle the interrupt and need to store the status of processor into the stack before taking the interrupt. If the processor continues to use SP in low privilege mode, data in the higher privilege mode will be saved in the memory space which is accessible in the lower privilege mode. RISC-V defines that when the processor is in a lower privilege mode, then data in SP of the higher privilege mode can be stored in mscratch. And in this way, the value of SP can be recovered from mscratch when the processor goes back to the higher privilege mode. It will cost a lot of cycles to execute the program above using standard instructions, so RISC-V defines mscratchcsw register. After entering an interrupt, the processor executes an mscratchcsw CSR instruction to swap the value between mscratch and SP to recover the value of SP of the higher privilege mode. At the same time, copy the value of SP of the lower privilege to mscratch. Before the mret instruction to exit interrupt, add an mscratchcsw instruction to swap value between mscratch and SP. It will recover the SP value of the lower privilege mode and store the higher privilege mode SP to mscratch again. In this way, only two instructions are needed to solve the stack pointer (SP) switching problem of different privileged modes, which speeds up interrupt processing. .. _core_csr_mscratchcswl: mscratchcswl ~~~~~~~~~~~~ This register is from the `CLIC draft`_ of RISC-V fast interrupt task group. The mscratchcswl register is used to exchange the destination register with the value of mscratch to speed up interrupt processing when switching between multiple interrupt levels. Using the CSR instruction to read the register mscratchcsw, with unchanged privilege mode, the following register operations are performed when there is a switch between the interrupt handler and the application program: .. code-block:: c :linenos: csrrw rd, mscratchcswl, rs1 // Pseudocode operation. if ( ( mcause.mpil==0) != ( mintstatus.mil == 0) ) { t = rs1; rd = mscratch; mscratch = t; } else { rd = rs1; // mscratch unchanged. } // Usual use: csrrw sp, mscratchcswl, sp In the same privilege mode, separating the interrupt handler task from the task space of the application task can increase robustness, reduce space usage, and facilitate system debugging. The interrupt handler has a non-zero interrupt level while the application task has a zero interrupt level. According to this feature, the RISC-V architecture defines the mscratchcswl register. Similar to mscratchcsw, adding a register instruction of mscratchcswl to the beginning and the end of the interrupt service routine enables a fast stack pointer switch between the interrupt handler and the regular application, ensuring the separation of the stack space between the interrupt handler and the regular application. .. _core_csr_sleepvalue: sleepvalue ~~~~~~~~~~ The Nuclei processor core customized CSR sleepvalue controls different sleep modes. See :ref:`lowpower_enter_sleep_mode` for more information. .. _table_core_csr_13: .. table:: sleepvalue register :widths: 100,40,400 ============== ======= ============================================================ **Field** **Bit** **Description** **SLEEPVALUE** 0 Control WFI sleep mode: (Reset default value is 0) - | 0: shallow sleep mode | (After WFI, it recommends SoC to turn ``core_clk`` off) - | 1: deep sleep mode | (After WFI, it recommends SoC to turn ``core_clk`` | and ``core_aon_clk`` both off) **Reserved** 31:1 Reserved 0 ============== ======= ============================================================ .. _core_csr_txevt: txevt ~~~~~ The Nuclei processor core customized CSR txevt controls output events. .. _table_core_csr_14: .. table:: txevt register :widths: 100,40,400 ============ ======= =================================================================== **Field** **Bit** **Description** **TXEVT** 0 Event control: (Reset default value is 0) - | If this bit is set as 1, Nuclei processor core will trigger | a single-cycle pulse output signal ``tx_evt`` as event signal. - | This bit will be automatically cleared to 0 | in the next cycle when it becomes 1. - No action, when this bit is set as 0. **Reserved** 31:1 Reserved 0 ============ ======= =================================================================== .. _core_csr_wfe: wfe ~~~ The Nuclei processor core customized CSR wfe Control whether the processor should be awakened by interrupt or event. See :ref:`lowpower_wfe` for more information. .. _table_core_csr_15: .. table:: wfe register :widths: 100,40,400 ============ ======= ========================================================================== **Field** **Bit** **Description** **WFE** 0 Control whether the processor should be awakened by interrupt or event. - 0: The processor should be awakened by interrupt and NMI in sleep mode. - 1: The processor should be awakened by event and NMI in sleep mode. Reset default value is 0. **Reserved** 31:1 Reserved 0 ============ ======= ========================================================================== .. _core_csr_ucode: ucode ~~~~~ This register is from the P-extension draft of RISC-V P-extension task group. This register is only existed when the core have been configured to support the P extension. CSR register ucode is used to record if there is overflow happened in DSP instructions. .. _table_core_csr_16: .. table:: ucode register :widths: 100,40,400 ============ ======= =========================================================== **Field** **Bit** **Description** **OV** 0 | Record if there is overflow happened in DSP instructions. | If there is overflow then this field OV is set as 1, | software can write 0 to this register to clear it. Reset default value is 0. **Reserved** 31:1 Reserved 0 ============ ======= =========================================================== .. _core_csr_mcfg_info: mcfg_info ~~~~~~~~~ This CSR is used to show the processor configuration information. .. _table_core_csr_mcfg_info: .. table:: mcfg_info register :widths: 100,50,300 ============ ======= ========================================= **Field** **Bit** **Description** ============ ======= ========================================= **Reserved** 31:11 Reserved 0 **DCACHE** 10 Global configuration for D-CACHE support: - 0: No D-CACHE support. - 1: Has D-CACHE support. **ICACHE** 9 Global configuration for I-CACHE support: - 0: No I-CACHE support. - 1: Has I-CACHE support. **DLM** 8 Global configuration for DLM support: - 0: No DLM support. - 1: Has DLM support. **ILM** 7 Global configuration for ILM support: - 0: No ILM support. - 1: Has ILM support. **NICE** 6 Global configuration for NICE support: - 0: No NICE support. - 1: Has NICE support. **PPI** 5 Global configuration for PPI support: - 0: No PPI support. - 1: Has PPI support. **FIO** 4 Global configuration for FIO support: - 0: No FIO support. - 1: Has FIO support. **PLIC** 3 Global configuration for PLIC support: - 0: No PLIC support. - 1: Has PLIC support. **CLIC** 2 Global configuration for CLICsupport: - 0: No CLIC support. - 1: Has CLIC support. **ECC** 1 Global configuration for ECC support: - 0: No ECC support. - 1: Has ECC support. **TEE** 0 Global configuration for TEE support: - 0: No TEE support. - 1: Has TEE support. ============ ======= ========================================= .. _core_csr_micfg_info: micfg_info ~~~~~~~~~~ This CSR is used to show the ILM and I-Cache configuration information. .. _table_core_csr_micfg_info: .. table:: micfg_info register :widths: 100,50,300 ============= ========= ========================================================== **Field** **Bit** **Description** ============= ========= ========================================================== **Reserved** XLEN-1:22 Reserved 0 **ILM_XONLY** 21 | Indicates if ILM is execute-only. | If ILM is execute-only, load/store instructions | cannot access the ILM region: - 0: ILM is not execute-only. - 1: ILM is execute-only. **ILM_SIZE** 20:16 Indicates the size of ILM. The size has to be power of 2: - 0: 0 Byte - 1: 256 Bytes - 2: 512 Bytes - 3: 1 KiB - 4: 2 KiB - 5: 4 KiB - 6: 8 KiB - 7: 16 KiB - 8: 32 KiB - 9: 64 KiB - 10: 128 KiB - 11: 256 KiB - 12: 512 KiB - 13: 1 MiB - 14: 2 MiB - 15: 4 MiB - 16: 8 MiB - 17: 16 MiB - 18: 32 MiB - 19: 64 MiB - 20: 128 MiB - 20: 256 MiB - 21: 512 MiB - Others: Reserved **Reserved** 15:10 - Reserved 0 **IC_LSIZE** 9:7 I-Cache line size: - 0: No I-Cache - 1: 8 bytes - 2: 16 bytes - 3: 32 bytes - 4: 64 bytes - 5: 128 bytes - Others: Reserved **IC_WAY** 6:4 I-Cache ways: - 0: Direct-mapped - 1: 2 way - 2: 3 way - 3: 4 way - 4: 5 way - 5: 6 way - 6: 7 way - 7: 8 way **IC_SET** 3:0 I-Cache sets per way: - 0: 8 - 1: 16 - 2: 32 - 3: 64 - 4: 128 - 5: 256 - 6: 512 - 7: 1024 - 8: 2048 - 9: 4096 - 10: 8192 - Others: Reserved ============= ========= ========================================================== .. _core_csr_mdcfg_info: mdcfg_info ~~~~~~~~~~ This CSR is used to show the DLM and D-Cache configuration information. .. _table_core_csr_mdcfg_info: .. table:: mdcfg_info register :widths: 100,50,300 ============ ========= ============================================= **Field** **Bit** **Description** ============ ========= ============================================= **Reserved** XLEN-1:21 Reserved 0 **DLM_SIZE** 20:16 Indicates the size of DLM. The size has to be power of 2: - 0: 0 Byte - 1: 256 Bytes - 2: 512 Bytes - 3: 1 KiB - 4: 2 KiB - 5: 4 KiB - 6: 8 KiB - 7: 16 KiB - 8: 32 KiB - 9: 64 KiB - 10: 128 KiB - 11: 256 KiB - 12: 512 KiB - 13: 1 MiB - 14: 2 MiB - 15: 4 MiB - 16: 8 MiB - 17: 16 MiB - 18: 32 MiB - 19: 64 MiB - 20: 128 MiB - 20: 256 MiB - 21: 512 MiB - Others: Reserved **Reserved** 15:10 - Reserved 0 **DC_LSIZE** 9:7 D-Cache line size: - 0: No D-Cache - 1: 8 bytes - 2: 16 bytes - 3: 32 bytes - 4: 64 bytes - 5: 128 bytes - Others: Reserved **DC_WAY** 6:4 D-Cache ways: - 0: Direct-mapped - 1: 2 way - 2: 3 way - 3: 4 way - 4: 5 way - 5: 6 way - 6: 7 way - 7: 8 way **DC_SET** 3:0 D-Cache sets per way: - 0: 8 - 1: 16 - 2: 32 - 3: 64 - 4: 128 - 5: 256 - 6: 512 - 7: 1024 - 8: 2048 - 9: 4096 - 10: 8192 - Others: Reserved ============ ========= ============================================= .. _core_csr_mtlbcfg_info: mtlbcfg_info ~~~~~~~~~~~~ This CSR is used to show the TLB configuration information. .. _table_core_csr_mtlbcfg_info: .. table:: mtlbcfg_info register :widths: auto +---------------+-----------+--------+---------------+---------------+ | **Field | **Bits** | **RW** | **Reset | **Desc\ | | Name** | | | Value** | ription** | +===============+===========+========+===============+===============+ | **Reserved** | XLEN-1:22 | RO | 0 | \- | +---------------+-----------+--------+---------------+---------------+ | **DTLB_SIZE** | 21:19 | RO | IM | DTLB size: | | | | | | | | | | | | - 0: N0 DTLB | | | | | | | | | | | | - 1: 1 entry | | | | | | | | | | | | - 2: 2 | | | | | | entries | | | | | | | | | | | | - 3: 4 | | | | | | entries | | | | | | | | | | | | - 4: 8 | | | | | | entries | | | | | | | | | | | | - 5: 16 | | | | | | entries | | | | | | | | | | | | - 6: 32 | | | | | | entries | | | | | | | | | | | | - 7: 64 | | | | | | entries | +---------------+-----------+--------+---------------+---------------+ | **ITLB_SIZE** | 18:16 | RO | IM | ITLB size: | | | | | | | | | | | | - 0: N0 ITLB | | | | | | | | | | | | - 1: 1 entry | | | | | | | | | | | | - 2: 2 | | | | | | entries | | | | | | | | | | | | - 3: 4 | | | | | | entries | | | | | | | | | | | | - 4: 8 | | | | | | entries | | | | | | | | | | | | - 5: 16 | | | | | | entries | | | | | | | | | | | | - 6: 32 | | | | | | entries | | | | | | | | | | | | - 7: 64 | | | | | | entries | +---------------+-----------+--------+---------------+---------------+ | **Reserved** | 15:11 | RO | 0 | | +---------------+-----------+--------+---------------+---------------+ | **MTLB_ECC** | 10 | RO | IM | ECC support | | | | | | for the Main | | | | | | TLB: | | | | | | | | | | | | 0 : No ECC | | | | | | support. | | | | | | | | | | | | 1: Has ECC | | | | | | support. | +---------------+-----------+--------+---------------+---------------+ | **MTLB\ | 9:7 | RO | IM | Main TLB line | | _LSIZE** | | | | size: | | | | | | | | | | | | - 0: N0 Main | | | | | | TLB | | | | | | | | | | | | - 1: 1 entry | | | | | | | | | | | | - 2: 2 | | | | | | entries | | | | | | | | | | | | - 3: 4 | | | | | | entries | | | | | | | | | | | | - 4: 8 | | | | | | entries | | | | | | | | | | | | - 5: 16 | | | | | | entries | | | | | | | | | | | | - 6: 32 | | | | | | entries | | | | | | | | | | | | - 7: 64 | | | | | | entries | +---------------+-----------+--------+---------------+---------------+ | **MTLB_WAY** | 6:4 | RO | IM | Main TLB | | | | | | ways: | | | | | | | | | | | | - 0: Direct- | | | | | | \mapped | | | | | | | | | | | | - 1: 2 way | | | | | | | | | | | | - 2: 3 way | | | | | | | | | | | | - 3: 4 way | | | | | | | | | | | | - 4: 5 way | | | | | | | | | | | | - 5: 6 way | | | | | | | | | | | | - 6: 7 way | | | | | | | | | | | | - 7: 8 way | +---------------+-----------+--------+---------------+---------------+ | **MTLB_SET** | 3:0 | RO | IM | Main TLB sets | | | | | | per way: | | | | | | | | | | | | - 0: 8 | | | | | | | | | | | | - 1: 16 | | | | | | | | | | | | - 2: 32 | | | | | | | | | | | | - 3: 64 | | | | | | | | | | | | - 4: 128 | | | | | | | | | | | | - 5: 256 | | | | | | | | | | | | - 6: 512 | | | | | | | | | | | | - 7: 1024 | | | | | | | | | | | | - 8: 2048 | | | | | | | | | | | | - 9: 4096 | | | | | | | | | | | | - 10: 8192 | | | | | | | | | | | | - Others: \ | | | | | | Reserved | +---------------+-----------+--------+---------------+---------------+ .. _core_csr_mppicfg_info: mppicfg_info ~~~~~~~~~~~~ This CSR is used to show the PPI configuration information. .. _table_core_csr_mppicfg_info: .. table:: mppicfg_info register :widths: 100,50,400 ============ ========= =================================================================== **Field** **Bit** **Description** ============ ========= =================================================================== **PPI_BPA** XLEN-1:10 The base physical address of PPI. It has to be aligned to multiple of PPI size. For example, to set up an instruction local memory of size 4KB starting at address 12KB (0x3000), we simply program DLM_BPA to 0xC (take the upper 22 bits of 0x3000). **Reserved** 9:6 Reserved 0 **PPI_SIZE** 5:1 Indicates the size of PPI. The size has to be power of 2: - 0: Reserved - 1: 1 KiB - 2: 2 KiB - 3: 4 KiB - 4: 8 KiB - 5: 16 KiB - 6: 32 KiB - 7: 64 KiB - 8: 128 KiB - 9: 256 KiB - 10: 512 KiB - 11: 1 MiB - 12: 2 MiB - 13: 4 MiB - 14: 8 MiB - 15: 16 MiB - 16: 32 MiB - 17: 64 MiB - 18: 128 MiB - 19: 256 MiB - 20: 512 MiB - 21: 1 GiB - 22: 2 GiB Others: Reserved **Reserved** 0 Reserved 1 ============ ========= =================================================================== .. note:: This CSR exists only when PPI is configured. .. _core_csr_mfiocfg_info: mfiocfg_info ~~~~~~~~~~~~ This CSR is used to show the FIO configuration information. .. _table_core_csr_mfiocfg_info: .. table:: mfiocfg_info register :widths: 100,50,400 ============ ========= ======================================================== **Field** **Bit** **Description** ============ ========= ======================================================== **FIO_BPA** XLEN-1:10 The base physical address of FIO. It has to be aligned to multiple of FIO size. For example, to set up an instruction local memory of size 4KB starting at address 12KB (0x3000), we simply program FIO_BPA to 0xC (take the upper 22 bits of 0x3000). **Reserved** 9:6 Reserved 0 **FIO_SIZE** 5:1 Indicates the size of FIO. The size has to be power of 2: - 0: Reserved - 1: 1 KiB - 2: 2 KiB - 3: 4 KiB - 4: 8 KiB - 5: 16 KiB - 6: 32 KiB - 7: 64 KiB - 8: 128 KiB - 9: 256 KiB - 10: 512 KiB - 11: 1 MiB - 12: 2 MiB - 13: 4 MiB - 14: 8 MiB - 15: 16 MiB - 16: 32 MiB - 17: 64 MiB - 18: 128 MiB - 19: 256 MiB - 20: 512 MiB - 21: 1 GiB - 22: 2 GiB Others: Reserved **Reserved** 0 Reserved 1 ============ ========= ======================================================== .. note:: This CSR exists only when FIO is configured. .. _core_csr_mecc_lock: mecc_lock ~~~~~~~~~ This CSR is used to show ECC lock info. .. _table_core_csr_mecc_lock: .. table:: mecc_lock register :widths: auto +---------------+----------+--------+---------------+---------------+ | **Field | **Bits** | **RW** | **Reset | **Descr\ | | Name** | | | Value** | iption** | +===============+==========+========+===============+===============+ | **Reserved** | XLEN-1:1 | RO | 0 | \- | +---------------+----------+--------+---------------+---------------+ | **ECC_LOCK** | 0 | RW | 0 | To lock ECC | | | | | | related CSRs | | | | | | (*mecc_lock, | | | | | | mecc_code | | | | | | [RAMID and | | | | | | SRAMID | | | | | | excluded], | | | | | | ECC shield in | | | | | | milm_ctl, | | | | | | mdlm_ctl, | | | | | | mcache_ctl, | | | | | | mtlb_ctl*), | | | | | | then cannot | | | | | | be modified: | | | | | | | | | | | | 0: not | | | | | | locked; | | | | | | | | | | | | 1: locked; | +---------------+----------+--------+---------------+---------------+ .. _core_csr_mecc_code: mecc_code ~~~~~~~~~ This CSR is used to ECC code injection, can be used for ECC error simulation. .. _table_core_csr_mecc_code: .. table:: mecc_code register :widths: auto +--------------+--------------+--------+--------------+--------------+ | **Field | **Bits** | **RW** | **Reset | **D\ | | Name** | | | Value** | escription** | +==============+==============+========+==============+==============+ | **Reserved** | XLEN-1:29 | RO | 0 | \- | +--------------+--------------+--------+--------------+--------------+ | **S\ | 28:24 | RW | 0 | The ID of | | RAMID[4:0]** | | | | RAM that has | | | | | | single bit | | | | | | ECC errors. | | | | | | | | | | | | One of these | | | | | | bits is | | | | | | updated when | | | | | | an single | | | | | | ECC error | | | | | | exception | | | | | | occurs, and | | | | | | can be | | | | | | cleared by | | | | | | software. | | | | | | | | | | | | SRAMID[0]: | | | | | | I-Cache has | | | | | | a single ECC | | | | | | error | | | | | | | | | | | | SRAMID[1]: | | | | | | D-Cache has | | | | | | a single ECC | | | | | | error | | | | | | | | | | | | SRAMID[2]: | | | | | | Main TLB has | | | | | | a single ECC | | | | | | error | | | | | | | | | | | | SRAMID[3]: | | | | | | ILM ECC has | | | | | | a single | | | | | | error | | | | | | | | | | | | SRAMID[4]: | | | | | | DLM ECC has | | | | | | a single | | | | | | error | +--------------+--------------+--------+--------------+--------------+ | **Reserved** | 23:21 | RW | 0 | \- | +--------------+--------------+--------+--------------+--------------+ | **RAM\ | 20:16 | RW | 0 | The ID of | | ID[4:0]** | | | | RAM that has | | | | | | double bit | | | | | | ECC errors. | | | | | | | | | | | | One of these | | | | | | bits is | | | | | | updated when | | | | | | a double bit | | | | | | ECC error | | | | | | exception | | | | | | occurs, and | | | | | | can be | | | | | | cleared by | | | | | | software. | | | | | | | | | | | | RAMID[0]: | | | | | | I-Cache has | | | | | | a double bit | | | | | | ECC error | | | | | | | | | | | | RAMID[1]: | | | | | | D-Cache has | | | | | | a double bit | | | | | | ECC ECC | | | | | | error | | | | | | | | | | | | RAMID[2]: | | | | | | Main TLB has | | | | | | a double bit | | | | | | ECC ECC | | | | | | error | | | | | | | | | | | | RAMID[3]: | | | | | | ILM ECC has | | | | | | a double bit | | | | | | ECC error | | | | | | | | | | | | RAMID[4]: | | | | | | DLM ECC has | | | | | | a double bit | | | | | | ECC error | +--------------+--------------+--------+--------------+--------------+ | **Reserved** | [15:7] or | RO | 0 | \- | | | [15:8] or | | | | | | [15:9] | | | | +--------------+--------------+--------+--------------+--------------+ | **Code** | [6:0] or | RW | o | ECC code for | | | [7:0] or | | | injection: | | | [8:0] | | | | | | | | | Max(TLB | | | | | | Width, Data | | | | | | Bus Width) > | | | | | | 64: | | | | | | | | | | | | The width of | | | | | | Code is 9; | | | | | | | | | | | | Max(TLB | | | | | | Width, Data | | | | | | Bus Width) > | | | | | | 32: | | | | | | | | | | | | The width of | | | | | | Code is 8; | | | | | | | | | | | | Max(TLB | | | | | | Width, Data | | | | | | Bus Width) | | | | | | <= 32: | | | | | | | | | | | | The width of | | | | | | Code is 7; | +--------------+--------------+--------+--------------+--------------+ .. _core_csr_mtlb_ctl: mtlb_ctl ~~~~~~~~ This CSR is used to show the Main TLB control info. .. _table_core_csr_mtlb_ctl: .. table:: mtlb_ctl register :widths: auto +---------------+----------+--------+---------------+---------------+ | **Field | **Bits** | **RW** | **Reset | **De\ | | Name** | | | Value** | scription** | +===============+==========+========+===============+===============+ | **Reserved** | XLEN-1:4 | RO | 0 | \- | +---------------+----------+--------+---------------+---------------+ | **TL\ | 3 | RW | 0 | Controls | | B_RWDECC** | | | | diagnostic | | | | | | accesses of | | | | | | ECC codes of | | | | | | the main TLB | | | | | | data rams | | | | | | through the | | | | | | mecc_code | | | | | | register. | | | | | | This bit can | | | | | | be turned on | | | | | | for injecting | | | | | | ECC errors to | | | | | | test the ECC | | | | | | handler. | | | | | | | | | | | | - 0: Disable | | | | | | diagnostic | | | | | | accesses | | | | | | of ECC | | | | | | codes | | | | | | | | | | | | - 1: Enable | | | | | | diagnostic | | | | | | accesses | | | | | | of ECC | | | | | | codes | | | | | | | | | | | | Notice: When | | | | | | MMU is not | | | | | | con | | | | | | figured, this | | | | | | field is tied | | | | | | to 0. | +---------------+----------+--------+---------------+---------------+ | **TLB_R\ | 2 | RW | 0 | Controls | | WTECC** | | | | diagnostic | | | | | | accesses of | | | | | | ECC codes of | | | | | | t the main | | | | | | TLB tag rams | | | | | | through the | | | | | | mecc_code | | | | | | register. | | | | | | This bit can | | | | | | be turned on | | | | | | for injecting | | | | | | ECC errors to | | | | | | test the ECC | | | | | | handler. | | | | | | | | | | | | - 0: Disable | | | | | | diagnostic | | | | | | accesses | | | | | | of ECC | | | | | | codes | | | | | | | | | | | | - 1: Enable | | | | | | diagnostic | | | | | | accesses | | | | | | of ECC | | | | | | codes | | | | | | | | | | | | Notice: When | | | | | | MMU is not | | | | | | con | | | | | | figured, this | | | | | | field is tied | | | | | | to 0. | +---------------+----------+--------+---------------+---------------+ | **TLB_\ | 1 | RW | 0 | Main TLB | | ECC_EXCP_EN** | | | | double bit | | | | | | ECC exception | | | | | | enable | | | | | | control: | | | | | | | | | | | | - 0: Disable | | | | | | double bit | | | | | | ECC | | | | | | exception | | | | | | | | | | | | - 1: Enable | | | | | | double bit | | | | | | ECC | | | | | | exception | | | | | | | | | | | | Notice: When | | | | | | MMU is not | | | | | | con | | | | | | figured, this | | | | | | field is tied | | | | | | to 0. | +---------------+----------+--------+---------------+---------------+ | **TLB_E\ | 0 | RW | 0 | Main TLB ECC | | CC_EN** | | | | enable | | | | | | control: | | | | | | | | | | | | - 0: Disable | | | | | | ECC | | | | | | (default) | | | | | | | | | | | | - 1: Enable | | | | | | ECC | | | | | | | | | | | | Notice: When | | | | | | MMU is not | | | | | | con | | | | | | figured, this | | | | | | field is tied | | | | | | to 0. | +---------------+----------+--------+---------------+---------------+ .. _CLIC draft: https://github.com/riscv/riscv-fast-interrupt/blob/master/clic.adoc