.. _isa_changelog:

Revision History
================

.. warning::

    For latest version of Nuclei ISA Spec since 2022,
    please get it from AE of Nuclei System Technology.
    This online version is out of date.

2.0.3
-----

* Change the mcache_ctl[1]/scrathpad mode default value to be 1 after reset
* Add :ref:`ecc_nuclei_csrs`
* Add :ref:`ecc`
* Update TIMER to be compatiable with CLINT mode for UX class to run Linux
* Update the PLIC registers memory map

2.0
---

* Added :ref:`MMU` chapter

* Added :ref:`CCM` chapter

* Added the following CSRs

  - :ref:`core_csr_milm_ctl`
  - :ref:`core_csr_mdlm_ctl`
  - :ref:`core_csr_mppicfg_info`
  - :ref:`core_csr_mfiocfg_info`
  - :ref:`core_csr_micfg_info`
  - :ref:`core_csr_mdcfg_info`
  - :ref:`core_csr_mcfg_info`

* Modified the following CSRs

  - :ref:`core_csr_mcache_ctl`
  - :ref:`core_csr_mmisc_ctl`

* DSP feature is upgraded to match `RISC-V "P" Extension Proposal`_ release 0.5.4

1.5
---

* First version of Nuclei RISC-V ISA in English
* DSP feature match `RISC-V "P" Extension Proposal`_ release 0.5.0

.. _RISC-V "P" Extension Proposal: https://github.com/riscv/riscv-p-spec/blob/master/P-ext-proposal.adoc