NMSIS-Core  Version 1.2.0
NMSIS-Core support for Nuclei processor-based devices
64-bit Addition & Subtraction Instructions

64-bit Addition & Subtraction Instructions More...

Functions

__STATIC_FORCEINLINE unsigned long long __RV_ADD64 (unsigned long long a, unsigned long long b)
 ADD64 (64-bit Addition) More...
 
__STATIC_FORCEINLINE long long __RV_KADD64 (long long a, long long b)
 KADD64 (64-bit Signed Saturating Addition) More...
 
__STATIC_FORCEINLINE long long __RV_KSUB64 (long long a, long long b)
 KSUB64 (64-bit Signed Saturating Subtraction) More...
 
__STATIC_FORCEINLINE long long __RV_RADD64 (long long a, long long b)
 RADD64 (64-bit Signed Halving Addition) More...
 
__STATIC_FORCEINLINE long long __RV_RSUB64 (long long a, long long b)
 RSUB64 (64-bit Signed Halving Subtraction) More...
 
__STATIC_FORCEINLINE unsigned long long __RV_SUB64 (unsigned long long a, unsigned long long b)
 SUB64 (64-bit Subtraction) More...
 
__STATIC_FORCEINLINE unsigned long long __RV_UKADD64 (unsigned long long a, unsigned long long b)
 UKADD64 (64-bit Unsigned Saturating Addition) More...
 
__STATIC_FORCEINLINE unsigned long long __RV_UKSUB64 (unsigned long long a, unsigned long long b)
 UKSUB64 (64-bit Unsigned Saturating Subtraction) More...
 
__STATIC_FORCEINLINE unsigned long long __RV_URADD64 (unsigned long long a, unsigned long long b)
 URADD64 (64-bit Unsigned Halving Addition) More...
 
__STATIC_FORCEINLINE unsigned long long __RV_URSUB64 (unsigned long long a, unsigned long long b)
 URSUB64 (64-bit Unsigned Halving Subtraction) More...
 

Detailed Description

64-bit Addition & Subtraction Instructions

there are 10 64-bit Addition & Subtraction Instructions.

Function Documentation

◆ __RV_ADD64()

__STATIC_FORCEINLINE unsigned long long __RV_ADD64 ( unsigned long long  a,
unsigned long long  b 
)

ADD64 (64-bit Addition)

Type: 64-bit Profile

Syntax:

ADD64 Rd, Rs1, Rs2

Purpose:
Add two 64-bit signed or unsigned integers.

RV32 Description:
This instruction adds the 64-bit integer of an even/odd pair of registers specified by Rs1(4,1) with the 64-bit integer of an even/odd pair of registers specified by Rs2(4,1), and then writes the 64-bit result to an even/odd pair of registers specified by Rd(4,1). Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register pair includes register 2d and 2d+1. The odd 2d+1 register of the pair contains the high 32-bit of the result and the even 2d register of the pair contains the low 32-bit of the result.

RV64 Description:
This instruction has the same behavior as the ADD instruction in RV64I.

Note:
This instruction can be used for either signed or unsigned addition.

Operations:

RV32:
t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1);
b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1);
R[t_H].R[t_L] = R[a_H].R[a_L] + R[b_H].R[b_L];
RV64:
Rd = Rs1 + Rs2;
Parameters
[in]aunsigned long long type of value stored in a
[in]bunsigned long long type of value stored in b
Returns
value stored in unsigned long long type

Definition at line 543 of file core_feature_dsp.h.

544 {
545  unsigned long long result;
546  __ASM volatile("add64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
547  return result;
548 }

References __ASM.

◆ __RV_KADD64()

__STATIC_FORCEINLINE long long __RV_KADD64 ( long long  a,
long long  b 
)

KADD64 (64-bit Signed Saturating Addition)

Type: DSP (64-bit Profile)

Syntax:

KADD64 Rd, Rs1, Rs2

Purpose:
Add two 64-bit signed integers. The result is saturated to the Q63 range.

RV32 Description:
This instruction adds the 64-bit signed integer of an even/odd pair of registers specified by Rs1(4,1) with the 64-bit signed integer of an even/odd pair of registers specified by Rs2(4,1). If the 64-bit result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The saturated result is written to an even/odd pair of registers specified by Rd(4,1). Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register pair includes register 2d and 2d+1. The odd 2d+1 register of the pair contains the high 32-bit of the result and the even 2d register of the pair contains the low 32-bit of the result.

RV64 Description:
This instruction adds the 64-bit signed integer in Rs1 with the 64-bit signed integer in Rs2. If the result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The saturated result is written to Rd.

Operations:

RV32:
t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1);
b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1);
result = R[a_H].R[a_L] + R[b_H].R[b_L];
if (result > (2^63)-1) {
result = (2^63)-1; OV = 1;
} else if (result < -2^63) {
result = -2^63; OV = 1;
}
R[t_H].R[t_L] = result;
RV64:
result = Rs1 + Rs2;
if (result > (2^63)-1) {
result = (2^63)-1; OV = 1;
} else if (result < -2^63) {
result = -2^63; OV = 1;
}
Rd = result;
Parameters
[in]along long type of value stored in a
[in]blong long type of value stored in b
Returns
value stored in long long type

Definition at line 1666 of file core_feature_dsp.h.

1667 {
1668  long long result;
1669  __ASM volatile("kadd64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
1670  return result;
1671 }

References __ASM.

◆ __RV_KSUB64()

__STATIC_FORCEINLINE long long __RV_KSUB64 ( long long  a,
long long  b 
)

KSUB64 (64-bit Signed Saturating Subtraction)

Type: DSP (64-bit Profile)

Syntax:

KSUB64 Rd, Rs1, Rs2

Purpose:
Perform a 64-bit signed integer subtraction. The result is saturated to the Q63 range.

RV32 Description:
This instruction subtracts the 64-bit signed integer of an even/odd pair of registers specified by Rs2(4,1) from the 64-bit signed integer of an even/odd pair of registers specified by Rs1(4,1). If the 64-bit result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The saturated result is then written to an even/odd pair of registers specified by Rd(4,1). Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair includes register 2d and 2d+1. The odd 2d+1 register of the pair contains the high 32-bit of the operand and the even 2d register of the pair contains the low 32-bit of the operand.

RV64 Description:
This instruction subtracts the 64-bit signed integer of Rs2 from the 64-bit signed integer of Rs1. If the 64-bit result is beyond the Q63 number range (-2^63 <= Q63 <= 2^63-1), it is saturated to the range and the OV bit is set to 1. The saturated result is then written to Rd.

Operations:

RV32:
t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1);
b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1);
result = R[a_H].R[a_L] - R[b_H].R[b_L];
if (result > (2^63)-1) {
result = (2^63)-1; OV = 1;
} else if (result < -2^63) {
result = -2^63; OV = 1;
}
R[t_H].R[t_L] = result;
RV64:
result = Rs1 - Rs2;
if (result > (2^63)-1) {
result = (2^63)-1; OV = 1;
} else if (result < -2^63) {
result = -2^63; OV = 1;
}
Rd = result;
Parameters
[in]along long type of value stored in a
[in]blong long type of value stored in b
Returns
value stored in long long type

Definition at line 5496 of file core_feature_dsp.h.

5497 {
5498  long long result;
5499  __ASM volatile("ksub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
5500  return result;
5501 }

References __ASM.

◆ __RV_RADD64()

__STATIC_FORCEINLINE long long __RV_RADD64 ( long long  a,
long long  b 
)

RADD64 (64-bit Signed Halving Addition)

Type: DSP (64-bit Profile)

Syntax:

RADD64 Rd, Rs1, Rs2

Purpose:
Add two 64-bit signed integers. The result is halved to avoid overflow or saturation.

RV32 Description:
This instruction adds the 64-bit signed integer of an even/odd pair of registers specified by Rs1(4,1) with the 64-bit signed integer of an even/odd pair of registers specified by Rs2(4,1). The 64-bit addition result is first arithmetically right-shifted by 1 bit and then written to an even/odd pair of registers specified by Rd(4,1). Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register pair includes register 2d and 2d+1. The odd 2d+1 register of the pair contains the high 32-bit of the result and the even 2d register of the pair contains the low 32-bit of the result.

RV64 Description:
This instruction adds the 64-bit signed integer in Rs1 with the 64-bit signed integer in Rs2. The 64-bit addition result is first arithmetically right-shifted by 1 bit and then written to Rd.

Operations:

RV32:
t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1);
b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1);
R[t_H].R[t_L] = (R[a_H].R[a_L] + R[b_H].R[b_L]) s>> 1;
RV64:
Rd = (Rs1 + Rs2) s>> 1;
Parameters
[in]along long type of value stored in a
[in]blong long type of value stored in b
Returns
value stored in long long type

Definition at line 6401 of file core_feature_dsp.h.

6402 {
6403  long long result;
6404  __ASM volatile("radd64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
6405  return result;
6406 }

References __ASM.

◆ __RV_RSUB64()

__STATIC_FORCEINLINE long long __RV_RSUB64 ( long long  a,
long long  b 
)

RSUB64 (64-bit Signed Halving Subtraction)

Type: DSP (64-bit Profile)

Syntax:

RSUB64 Rd, Rs1, Rs2

Purpose:
Perform a 64-bit signed integer subtraction. The result is halved to avoid overflow or saturation.

RV32 Description:
This instruction subtracts the 64-bit signed integer of an even/odd pair of registers specified by Rb(4,1) from the 64-bit signed integer of an even/odd pair of registers specified by Ra(4,1). The subtraction result is first arithmetically right-shifted by 1 bit and then written to an even/odd pair of registers specified by Rt(4,1). Rx(4,1), i.e., value d, determines the even/odd pair group of two registers. Specifically, the register pair includes register 2d and 2d+1. The odd 2d+1 register of the pair contains the high 32-bit of the result and the even 2d register of the pair contains the low 32-bit of the result.

RV64 Description:
This instruction subtracts the 64-bit signed integer in Rs2 from the 64-bit signed integer in Rs1. The 64-bit subtraction result is first arithmetically right-shifted by 1 bit and then written to Rd.

Operations:

RV32:
t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1);
b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1);
R[t_H].R[t_L] = (R[a_H].R[a_L] - R[b_H].R[b_L]) s>> 1;
RV64:
Rd = (Rs1 - Rs2) s>> 1;
Parameters
[in]along long type of value stored in a
[in]blong long type of value stored in b
Returns
value stored in long long type

Definition at line 6820 of file core_feature_dsp.h.

6821 {
6822  long long result;
6823  __ASM volatile("rsub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
6824  return result;
6825 }

References __ASM.

◆ __RV_SUB64()

__STATIC_FORCEINLINE unsigned long long __RV_SUB64 ( unsigned long long  a,
unsigned long long  b 
)

SUB64 (64-bit Subtraction)

Type: DSP (64-bit Profile)

Syntax:

SUB64 Rd, Rs1, Rs2

Purpose:
Perform a 64-bit signed or unsigned integer subtraction.

RV32 Description:
This instruction subtracts the 64-bit integer of an even/odd pair of registers specified by Rs2(4,1) from the 64-bit integer of an even/odd pair of registers specified by Rs1(4,1), and then writes the 64-bit result to an even/odd pair of registers specified by Rd(4,1). Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair includes register 2d and 2d+1. The odd 2d+1 register of the pair contains the high 32-bit of the operand and the even 2d register of the pair contains the low 32-bit of the operand.

RV64 Description:
This instruction subtracts the 64-bit integer of Rs2 from the 64-bit integer of Rs1, and then writes the 64-bit result to Rd.

Note:
This instruction can be used for either signed or unsigned subtraction.

Operations:

* RV32:
t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1);
b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1);
R[t_H].R[t_L] = R[a_H].R[a_L] - R[b_H].R[b_L];
* RV64:
Rd = Rs1 - Rs2;
Parameters
[in]aunsigned long long type of value stored in a
[in]bunsigned long long type of value stored in b
Returns
value stored in unsigned long long type

Definition at line 10763 of file core_feature_dsp.h.

10764 {
10765  unsigned long long result;
10766  __ASM volatile("sub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
10767  return result;
10768 }

References __ASM.

◆ __RV_UKADD64()

__STATIC_FORCEINLINE unsigned long long __RV_UKADD64 ( unsigned long long  a,
unsigned long long  b 
)

UKADD64 (64-bit Unsigned Saturating Addition)

Type: DSP (64-bit Profile)

Syntax:

UKADD64 Rd, Rs1, Rs2

Purpose:
Add two 64-bit unsigned integers. The result is saturated to the U64 range.

RV32 Description:
This instruction adds the 64-bit unsigned integer of an even/odd pair of registers specified by Rs1(4,1) with the 64-bit unsigned integer of an even/odd pair of registers specified by Rs2(4,1). If the 64-bit result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is saturated to the range and the OV bit is set to 1. The saturated result is written to an even/odd pair of registers specified by Rd(4,1). Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair includes register 2d and 2d+1. The odd 2d+1 register of the pair contains the high 32-bit of the result and the even 2d register of the pair contains the low 32-bit of the result.

RV64 Description:
This instruction adds the 64-bit unsigned integer in Rs1 with the 64-bit unsigned integer in Rs2. If the 64-bit result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is saturated to the range and the OV bit is set to 1. The saturated result is written to Rd.

Operations:

* RV32:
t_L = CONCAT(Rt(4,1),1'b0); t_H = CONCAT(Rt(4,1),1'b1);
a_L = CONCAT(Ra(4,1),1'b0); a_H = CONCAT(Ra(4,1),1'b1);
b_L = CONCAT(Rb(4,1),1'b0); b_H = CONCAT(Rb(4,1),1'b1);
result = R[a_H].R[a_L] + R[b_H].R[b_L];
if (result > (2^64)-1) {
result = (2^64)-1; OV = 1;
}
R[t_H].R[t_L] = result;
* RV64:
result = Rs1 + Rs2;
if (result > (2^64)-1) {
result = (2^64)-1; OV = 1;
}
Rd = result;
Parameters
[in]aunsigned long long type of value stored in a
[in]bunsigned long long type of value stored in b
Returns
value stored in unsigned long long type

Definition at line 11524 of file core_feature_dsp.h.

11525 {
11526  unsigned long long result;
11527  __ASM volatile("ukadd64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
11528  return result;
11529 }

References __ASM.

◆ __RV_UKSUB64()

__STATIC_FORCEINLINE unsigned long long __RV_UKSUB64 ( unsigned long long  a,
unsigned long long  b 
)

UKSUB64 (64-bit Unsigned Saturating Subtraction)

Type: DSP (64-bit Profile)

Syntax:

UKSUB64 Rd, Rs1, Rs2

Purpose:
Perform a 64-bit signed integer subtraction. The result is saturated to the U64 range.

RV32 Description:
This instruction subtracts the 64-bit unsigned integer of an even/odd pair of registers specified by Rs2(4,1) from the 64-bit unsigned integer of an even/odd pair of registers specified by Rs1(4,1). If the 64-bit result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is saturated to the range and the OV bit is set to 1. The saturated result is then written to an even/odd pair of registers specified by Rd(4,1). Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair includes register 2d and 2d+1. The odd 2d+1 register of the pair contains the high 32-bit of the operand and the even 2d register of the pair contains the low 32-bit of the operand.

RV64 Description:
This instruction subtracts the 64-bit unsigned integer of Rs2 from the 64-bit unsigned integer of an even/odd pair of Rs1. If the 64-bit result is beyond the U64 number range (0 <= U64 <= 2^64-1), it is saturated to the range and the OV bit is set to 1. The saturated result is then written to Rd.

Operations:

* RV32:
t_L = CONCAT(Rd(4,1),1'b0); t_H = CONCAT(Rd(4,1),1'b1);
a_L = CONCAT(Rs1(4,1),1'b0); a_H = CONCAT(Rs1(4,1),1'b1);
b_L = CONCAT(Rs2(4,1),1'b0); b_H = CONCAT(Rs2(4,1),1'b1);
result = R[a_H].R[a_L] - R[b_H].R[b_L];
if (result < 0) {
result = 0; OV = 1;
}
R[t_H].R[t_L] = result;
* RV64
result = Rs1 - Rs2;
if (result < 0) {
result = 0; OV = 1;
}
Rd = result;
Parameters
[in]aunsigned long long type of value stored in a
[in]bunsigned long long type of value stored in b
Returns
value stored in unsigned long long type

Definition at line 12113 of file core_feature_dsp.h.

12114 {
12115  unsigned long long result;
12116  __ASM volatile("uksub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
12117  return result;
12118 }

References __ASM.

◆ __RV_URADD64()

__STATIC_FORCEINLINE unsigned long long __RV_URADD64 ( unsigned long long  a,
unsigned long long  b 
)

URADD64 (64-bit Unsigned Halving Addition)

Type: DSP (64-bit Profile)

Syntax:

URADD64 Rd, Rs1, Rs2

Purpose:
Add two 64-bit unsigned integers. The result is halved to avoid overflow or saturation.

RV32 Description:
This instruction adds the 64-bit unsigned integer of an even/odd pair of registers specified by Rs1(4,1) with the 64-bit unsigned integer of an even/odd pair of registers specified by Rs2(4,1). The 64-bit addition result is first logically right-shifted by 1 bit and then written to an even/odd pair of registers specified by Rd(4,1). Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair includes register 2d and 2d+1. The odd 2d+1 register of the pair contains the high 32-bit of the result and the even 2d register of the pair contains the low 32-bit of the result.

RV64 Description:
This instruction adds the 64-bit unsigned integer in Rs1 with the 64-bit unsigned integer Rs2. The 64-bit addition result is first logically right-shifted by 1 bit and then written to Rd.

Operations:

* RV32:
t_L = CONCAT(Rt(4,1),1'b0); t_H = CONCAT(Rt(4,1),1'b1);
a_L = CONCAT(Ra(4,1),1'b0); a_H = CONCAT(Ra(4,1),1'b1);
b_L = CONCAT(Rb(4,1),1'b0); b_H = CONCAT(Rb(4,1),1'b1);
R[t_H].R[t_L] = (R[a_H].R[a_L] + R[b_H].R[b_L]) u>> 1;
* RV64:
Rd = (Rs1 + Rs2) u>> 1;
Parameters
[in]aunsigned long long type of value stored in a
[in]bunsigned long long type of value stored in b
Returns
value stored in unsigned long long type

Definition at line 12993 of file core_feature_dsp.h.

12994 {
12995  unsigned long long result;
12996  __ASM volatile("uradd64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
12997  return result;
12998 }

References __ASM.

◆ __RV_URSUB64()

__STATIC_FORCEINLINE unsigned long long __RV_URSUB64 ( unsigned long long  a,
unsigned long long  b 
)

URSUB64 (64-bit Unsigned Halving Subtraction)

Type: DSP (64-bit Profile)

Syntax:

URSUB64 Rd, Rs1, Rs2

Purpose:
Perform a 64-bit unsigned integer subtraction. The result is halved to avoid overflow or saturation.

RV32 Description:
This instruction subtracts the 64-bit unsigned integer of an even/odd pair of registers specified by Rs2(4,1) from the 64-bit unsigned integer of an even/odd pair of registers specified by Rs1(4,1). The subtraction result is first logically right-shifted by 1 bit and then written to an even/odd pair of registers specified by Rd(4,1). Rx(4,1), i.e., d, determines the even/odd pair group of two registers. Specifically, the register pair includes register 2d and 2d+1. The odd 2d+1 register of the pair contains the high 32-bit of the result and the even 2d register of the pair contains the low 32-bit of the result.

RV64 Description:
This instruction subtracts the 64-bit unsigned integer in Rs2 from the 64-bit unsigned integer in Rs1. The subtraction result is first logically right-shifted by 1 bit and then written to Rd.

Operations:

* RV32:
t_L = CONCAT(Rt(4,1),1'b0); t_H = CONCAT(Rt(4,1),1'b1);
a_L = CONCAT(Ra(4,1),1'b0); a_H = CONCAT(Ra(4,1),1'b1);
b_L = CONCAT(Rb(4,1),1'b0); b_H = CONCAT(Rb(4,1),1'b1);
R[t_H].R[t_L] = (R[a_H].R[a_L] - R[b_H].R[b_L]) u>> 1;
* RV64:
Rd = (Rs1 - Rs2) u>> 1;
Parameters
[in]aunsigned long long type of value stored in a
[in]bunsigned long long type of value stored in b
Returns
value stored in unsigned long long type

Definition at line 13385 of file core_feature_dsp.h.

13386 {
13387  unsigned long long result;
13388  __ASM volatile("ursub64 %0, %1, %2" : "=r"(result) : "r"(a), "r"(b));
13389  return result;
13390 }

References __ASM.

__ASM
#define __ASM
Pass information from the compiler to the assembler.
Definition: nmsis_gcc.h:55